| 1 | /* Disassemble AVR instructions.
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| 2 | Copyright 1999, 2000 Free Software Foundation, Inc.
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| 3 |
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| 4 | Contributed by Denis Chertykov <denisc@overta.ru>
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| 5 |
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| 6 | This program is free software; you can redistribute it and/or modify
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| 7 | it under the terms of the GNU General Public License as published by
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| 8 | the Free Software Foundation; either version 2 of the License, or
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| 9 | (at your option) any later version.
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| 10 |
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| 11 | This program is distributed in the hope that it will be useful,
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| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 14 | GNU General Public License for more details.
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| 15 |
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| 16 | You should have received a copy of the GNU General Public License
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| 17 | along with this program; if not, write to the Free Software
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| 18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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| 19 |
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| 20 | #include <assert.h>
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| 21 | #include "sysdep.h"
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| 22 | #include "dis-asm.h"
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| 23 | #include "opintl.h"
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| 24 | #include "libiberty.h"
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| 25 |
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| 26 | struct avr_opcodes_s
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| 27 | {
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| 28 | char *name;
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| 29 | char *constraints;
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| 30 | char *opcode;
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| 31 | int insn_size; /* in words */
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| 32 | int isa;
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| 33 | unsigned int bin_opcode;
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| 34 | };
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| 35 |
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| 36 | #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
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| 37 | {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
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| 38 |
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| 39 | const struct avr_opcodes_s avr_opcodes[] =
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| 40 | {
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| 41 | #include "opcode/avr.h"
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| 42 | {NULL, NULL, NULL, 0, 0, 0}
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| 43 | };
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| 44 |
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| 45 | static int avr_operand PARAMS ((unsigned int, unsigned int,
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| 46 | unsigned int, int, char *, char *, int));
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| 47 |
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| 48 | static int
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| 49 | avr_operand (insn, insn2, pc, constraint, buf, comment, regs)
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| 50 | unsigned int insn;
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| 51 | unsigned int insn2;
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| 52 | unsigned int pc;
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| 53 | int constraint;
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| 54 | char *buf;
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| 55 | char *comment;
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| 56 | int regs;
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| 57 | {
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| 58 | int ok = 1;
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| 59 |
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| 60 | switch (constraint)
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| 61 | {
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| 62 | /* Any register operand. */
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| 63 | case 'r':
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| 64 | if (regs)
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| 65 | insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* source register */
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| 66 | else
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| 67 | insn = (insn & 0x01f0) >> 4; /* destination register */
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| 68 |
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| 69 | sprintf (buf, "r%d", insn);
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| 70 | break;
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| 71 |
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| 72 | case 'd':
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| 73 | if (regs)
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| 74 | sprintf (buf, "r%d", 16 + (insn & 0xf));
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| 75 | else
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| 76 | sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4));
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| 77 | break;
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| 78 |
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| 79 | case 'w':
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| 80 | sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3));
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| 81 | break;
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| 82 |
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| 83 | case 'a':
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| 84 | if (regs)
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| 85 | sprintf (buf, "r%d", 16 + (insn & 7));
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| 86 | else
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| 87 | sprintf (buf, "r%d", 16 + ((insn >> 4) & 7));
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| 88 | break;
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| 89 |
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| 90 | case 'v':
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| 91 | if (regs)
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| 92 | sprintf (buf, "r%d", (insn & 0xf) * 2);
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| 93 | else
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| 94 | sprintf (buf, "r%d", ((insn & 0xf0) >> 3));
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| 95 | break;
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| 96 |
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| 97 | case 'e':
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| 98 | {
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| 99 | char *xyz;
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| 100 |
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| 101 | switch (insn & 0x100f)
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| 102 | {
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| 103 | case 0x0000: xyz = "Z"; break;
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| 104 | case 0x1001: xyz = "Z+"; break;
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| 105 | case 0x1002: xyz = "-Z"; break;
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| 106 | case 0x0008: xyz = "Y"; break;
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| 107 | case 0x1009: xyz = "Y+"; break;
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| 108 | case 0x100a: xyz = "-Y"; break;
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| 109 | case 0x100c: xyz = "X"; break;
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| 110 | case 0x100d: xyz = "X+"; break;
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| 111 | case 0x100e: xyz = "-X"; break;
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| 112 | default: xyz = "??"; ok = 0;
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| 113 | }
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| 114 | sprintf (buf, xyz);
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| 115 |
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| 116 | if (AVR_UNDEF_P (insn))
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| 117 | sprintf (comment, _("undefined"));
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| 118 | }
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| 119 | break;
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| 120 |
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| 121 | case 'z':
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| 122 | *buf++ = 'Z';
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| 123 | if (insn & 0x1)
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| 124 | *buf++ = '+';
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| 125 | *buf = '\0';
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| 126 | if (AVR_UNDEF_P (insn))
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| 127 | sprintf (comment, _("undefined"));
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| 128 | break;
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| 129 |
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| 130 | case 'b':
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| 131 | {
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| 132 | unsigned int x;
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| 133 |
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| 134 | x = (insn & 7);
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| 135 | x |= (insn >> 7) & (3 << 3);
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| 136 | x |= (insn >> 8) & (1 << 5);
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| 137 |
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| 138 | if (insn & 0x8)
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| 139 | *buf++ = 'Y';
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| 140 | else
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| 141 | *buf++ = 'Z';
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| 142 | sprintf (buf, "+%d", x);
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| 143 | sprintf (comment, "0x%02x", x);
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| 144 | }
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| 145 | break;
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| 146 |
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| 147 | case 'h':
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| 148 | sprintf (buf, "0x%x",
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| 149 | ((((insn & 1) | ((insn & 0x1f0) >> 3)) << 16) | insn2) * 2);
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| 150 | break;
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| 151 |
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| 152 | case 'L':
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| 153 | {
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| 154 | int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2;
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| 155 | sprintf (buf, ".%+-8d", rel_addr);
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| 156 | sprintf (comment, "0x%x", pc + 2 + rel_addr);
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| 157 | }
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| 158 | break;
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| 159 |
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| 160 | case 'l':
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| 161 | {
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| 162 | int rel_addr = ((((insn >> 3) & 0x7f) ^ 0x40) - 0x40) * 2;
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| 163 | sprintf (buf, ".%+-8d", rel_addr);
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| 164 | sprintf (comment, "0x%x", pc + 2 + rel_addr);
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| 165 | }
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| 166 | break;
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| 167 |
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| 168 | case 'i':
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| 169 | sprintf (buf, "0x%04X", insn2);
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| 170 | break;
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| 171 |
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| 172 | case 'M':
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| 173 | sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf));
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| 174 | sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf));
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| 175 | break;
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| 176 |
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| 177 | case 'n':
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| 178 | sprintf (buf, "??");
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| 179 | fprintf (stderr, _("Internal disassembler error"));
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| 180 | ok = 0;
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| 181 | break;
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| 182 |
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| 183 | case 'K':
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| 184 | {
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| 185 | unsigned int x;
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| 186 |
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| 187 | x = (insn & 0xf) | ((insn >> 2) & 0x30);
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| 188 | sprintf (buf, "0x%02x", x);
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| 189 | sprintf (comment, "%d", x);
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| 190 | }
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| 191 | break;
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| 192 |
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| 193 | case 's':
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| 194 | sprintf (buf, "%d", insn & 7);
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| 195 | break;
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| 196 |
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| 197 | case 'S':
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| 198 | sprintf (buf, "%d", (insn >> 4) & 7);
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| 199 | break;
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| 200 |
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| 201 | case 'P':
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| 202 | {
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| 203 | unsigned int x;
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| 204 | x = (insn & 0xf);
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| 205 | x |= (insn >> 5) & 0x30;
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| 206 | sprintf (buf, "0x%02x", x);
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| 207 | sprintf (comment, "%d", x);
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| 208 | }
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| 209 | break;
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| 210 |
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| 211 | case 'p':
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| 212 | {
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| 213 | unsigned int x;
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| 214 |
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| 215 | x = (insn >> 3) & 0x1f;
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| 216 | sprintf (buf, "0x%02x", x);
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| 217 | sprintf (comment, "%d", x);
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| 218 | }
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| 219 | break;
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| 220 |
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| 221 | case '?':
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| 222 | *buf = '\0';
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| 223 | break;
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| 224 |
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| 225 | default:
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| 226 | sprintf (buf, "??");
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| 227 | fprintf (stderr, _("unknown constraint `%c'"), constraint);
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| 228 | ok = 0;
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| 229 | }
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| 230 |
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| 231 | return ok;
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| 232 | }
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| 233 |
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| 234 | static unsigned short avrdis_opcode PARAMS ((bfd_vma, disassemble_info *));
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| 235 |
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| 236 | static unsigned short
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| 237 | avrdis_opcode (addr, info)
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| 238 | bfd_vma addr;
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| 239 | disassemble_info *info;
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| 240 | {
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| 241 | bfd_byte buffer[2];
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| 242 | int status;
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| 243 | status = info->read_memory_func(addr, buffer, 2, info);
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| 244 | if (status != 0)
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| 245 | {
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| 246 | info->memory_error_func(status, addr, info);
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| 247 | return -1;
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| 248 | }
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| 249 | return bfd_getl16 (buffer);
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| 250 | }
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| 251 |
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| 252 |
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| 253 | int
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| 254 | print_insn_avr(addr, info)
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| 255 | bfd_vma addr;
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| 256 | disassemble_info *info;
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| 257 | {
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| 258 | unsigned int insn, insn2;
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| 259 | const struct avr_opcodes_s *opcode;
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| 260 | static unsigned int *maskptr;
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| 261 | void *stream = info->stream;
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| 262 | fprintf_ftype prin = info->fprintf_func;
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| 263 | static unsigned int *avr_bin_masks;
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| 264 | static int initialized;
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| 265 | int cmd_len = 2;
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| 266 | int ok = 0;
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| 267 | char op1[20], op2[20], comment1[40], comment2[40];
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| 268 |
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| 269 | if (!initialized)
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| 270 | {
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| 271 | unsigned int nopcodes;
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| 272 |
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| 273 | nopcodes = sizeof (avr_opcodes) / sizeof (struct avr_opcodes_s);
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| 274 |
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| 275 | avr_bin_masks = (unsigned int *)
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| 276 | xmalloc (nopcodes * sizeof (unsigned int));
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| 277 |
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| 278 | for (opcode = avr_opcodes, maskptr = avr_bin_masks;
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| 279 | opcode->name;
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| 280 | opcode++, maskptr++)
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| 281 | {
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| 282 | char * s;
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| 283 | unsigned int bin = 0;
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| 284 | unsigned int mask = 0;
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| 285 |
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| 286 | for (s = opcode->opcode; *s; ++s)
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| 287 | {
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| 288 | bin <<= 1;
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| 289 | mask <<= 1;
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| 290 | bin |= (*s == '1');
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| 291 | mask |= (*s == '1' || *s == '0');
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| 292 | }
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| 293 | assert (s - opcode->opcode == 16);
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| 294 | assert (opcode->bin_opcode == bin);
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| 295 | *maskptr = mask;
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| 296 | }
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| 297 |
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| 298 | initialized = 1;
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| 299 | }
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| 300 |
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| 301 | insn = avrdis_opcode (addr, info);
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| 302 |
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| 303 | for (opcode = avr_opcodes, maskptr = avr_bin_masks;
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| 304 | opcode->name;
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| 305 | opcode++, maskptr++)
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| 306 | {
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| 307 | if ((insn & *maskptr) == opcode->bin_opcode)
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| 308 | break;
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| 309 | }
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| 310 |
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| 311 | /* Special case: disassemble `ldd r,b+0' as `ld r,b', and
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| 312 | `std b+0,r' as `st b,r' (next entry in the table). */
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| 313 |
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| 314 | if (AVR_DISP0_P (insn))
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| 315 | opcode++;
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| 316 |
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| 317 | op1[0] = 0;
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| 318 | op2[0] = 0;
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| 319 | comment1[0] = 0;
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| 320 | comment2[0] = 0;
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| 321 |
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| 322 | if (opcode->name)
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| 323 | {
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| 324 | char *op = opcode->constraints;
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| 325 |
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| 326 | insn2 = 0;
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| 327 | ok = 1;
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| 328 |
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| 329 | if (opcode->insn_size > 1)
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| 330 | {
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| 331 | insn2 = avrdis_opcode (addr + 2, info);
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| 332 | cmd_len = 4;
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| 333 | }
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| 334 |
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| 335 | if (*op && *op != '?')
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| 336 | {
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| 337 | int regs = REGISTER_P (*op);
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| 338 |
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| 339 | ok = avr_operand (insn, insn2, addr, *op, op1, comment1, 0);
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| 340 |
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| 341 | if (ok && *(++op) == ',')
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| 342 | ok = avr_operand (insn, insn2, addr, *(++op), op2,
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| 343 | *comment1 ? comment2 : comment1, regs);
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| 344 | }
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| 345 | }
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| 346 |
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| 347 | if (!ok)
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| 348 | {
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| 349 | /* Unknown opcode, or invalid combination of operands. */
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| 350 | sprintf (op1, "0x%04x", insn);
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| 351 | op2[0] = 0;
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| 352 | sprintf (comment1, "????");
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| 353 | comment2[0] = 0;
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| 354 | }
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| 355 |
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| 356 | (*prin) (stream, "%s", ok ? opcode->name : ".word");
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| 357 |
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| 358 | if (*op1)
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| 359 | (*prin) (stream, "\t%s", op1);
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| 360 |
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| 361 | if (*op2)
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| 362 | (*prin) (stream, ", %s", op2);
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| 363 |
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| 364 | if (*comment1)
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| 365 | (*prin) (stream, "\t; %s", comment1);
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| 366 |
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| 367 | if (*comment2)
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| 368 | (*prin) (stream, " %s", comment2);
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| 369 |
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| 370 | return cmd_len;
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| 371 | }
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