| 1 | /* Opcode table for the ARM.
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| 2 |
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| 3 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2003
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| 4 | Free Software Foundation, Inc.
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| 5 |
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| 6 | This program is free software; you can redistribute it and/or modify
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| 7 | it under the terms of the GNU General Public License as published by
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| 8 | the Free Software Foundation; either version 2, or (at your option)
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| 9 | any later version.
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| 10 |
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| 11 | This program is distributed in the hope that it will be useful,
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| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 14 | GNU General Public License for more details.
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| 15 |
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| 16 | You should have received a copy of the GNU General Public License
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| 17 | along with this program; if not, write to the Free Software
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| 18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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| 19 |
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| 20 |
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| 21 | struct arm_opcode {
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| 22 | unsigned long value, mask; /* recognise instruction if (op&mask)==value */
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| 23 | char *assembler; /* how to disassemble this instruction */
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| 24 | };
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| 25 |
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| 26 | struct thumb_opcode
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| 27 | {
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| 28 | unsigned short value, mask; /* recognise instruction if (op&mask)==value */
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| 29 | char * assembler; /* how to disassemble this instruction */
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| 30 | };
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| 31 |
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| 32 | /* format of the assembler string :
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| 33 |
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| 34 | %% %
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| 35 | %<bitfield>d print the bitfield in decimal
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| 36 | %<bitfield>x print the bitfield in hex
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| 37 | %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
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| 38 | %<bitfield>r print as an ARM register
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| 39 | %<bitfield>f print a floating point constant if >7 else a
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| 40 | floating point register
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| 41 | %<code>y print a single precision VFP reg.
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| 42 | Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
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| 43 | %<code>z print a double precision VFP reg
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| 44 | Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
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| 45 | %c print condition code (always bits 28-31)
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| 46 | %P print floating point precision in arithmetic insn
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| 47 | %Q print floating point precision in ldf/stf insn
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| 48 | %R print floating point rounding mode
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| 49 | %<bitnum>'c print specified char iff bit is one
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| 50 | %<bitnum>`c print specified char iff bit is zero
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| 51 | %<bitnum>?ab print a if bit is one else print b
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| 52 | %p print 'p' iff bits 12-15 are 15
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| 53 | %t print 't' iff bit 21 set and bit 24 clear
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| 54 | %o print operand2 (immediate or register + shift)
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| 55 | %a print address for ldr/str instruction
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| 56 | %s print address for ldr/str halfword/signextend instruction
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| 57 | %b print branch destination
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| 58 | %B print arm BLX(1) destination
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| 59 | %A print address for ldc/stc/ldf/stf instruction
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| 60 | %m print register mask for ldm/stm instruction
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| 61 | %C print the PSR sub type.
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| 62 | %F print the COUNT field of a LFM/SFM instruction.
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| 63 | IWMMXT specific format options:
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| 64 | %<bitfield>g print as an iWMMXt 64-bit register
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| 65 | %<bitfield>G print as an iWMMXt general purpose or control register
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| 66 | %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
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| 67 | %Z print the Immediate of a WSHUFH instruction.
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| 68 | %L print as an iWMMXt N/M width field.
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| 69 | %l like 'A' except use byte offsets for 'B' & 'H' versions
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| 70 | Thumb specific format options:
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| 71 | %D print Thumb register (bits 0..2 as high number if bit 7 set)
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| 72 | %S print Thumb register (bits 3..5 as high number if bit 6 set)
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| 73 | %<bitfield>I print bitfield as a signed decimal
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| 74 | (top bit of range being the sign bit)
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| 75 | %M print Thumb register mask
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| 76 | %N print Thumb register mask (with LR)
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| 77 | %O print Thumb register mask (with PC)
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| 78 | %T print Thumb condition code (always bits 8-11)
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| 79 | %I print cirrus signed shift immediate: bits 0..3|4..6
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| 80 | %<bitfield>B print Thumb branch destination (signed displacement)
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| 81 | %<bitfield>W print (bitfield * 4) as a decimal
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| 82 | %<bitfield>H print (bitfield * 2) as a decimal
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| 83 | %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
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| 84 | */
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| 85 |
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| 86 | /* Note: There is a partial ordering in this table - it must be searched from
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| 87 | the top to obtain a correct match. */
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| 88 |
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| 89 | static const struct arm_opcode arm_opcodes[] =
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| 90 | {
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| 91 | /* ARM instructions. */
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| 92 | {0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
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| 93 | {0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
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| 94 | {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"},
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| 95 | {0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"},
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| 96 | {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
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| 97 | {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
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| 98 | {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
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| 99 |
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| 100 | /* V5J instruction. */
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| 101 | {0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"},
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| 102 |
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| 103 | /* XScale instructions. */
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| 104 | {0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
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| 105 | {0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
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| 106 | {0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
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| 107 | {0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
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| 108 | {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
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| 109 | {0xf450f000, 0xfc70f000, "pld\t%a"},
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| 110 |
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| 111 | /* Intel Wireless MMX technology instructions. */
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| 112 | #define FIRST_IWMMXT_INSN 0x0e130130
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| 113 | #define IWMMXT_INSN_COUNT 47
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| 114 | {0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
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| 115 | {0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
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| 116 | {0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
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| 117 | {0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
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| 118 | {0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
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| 119 | {0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
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| 120 | {0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
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| 121 | {0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
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| 122 | {0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
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| 123 | {0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
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| 124 | {0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
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| 125 | {0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
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| 126 | {0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
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| 127 | {0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
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| 128 | {0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
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| 129 | {0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
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| 130 | {0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
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| 131 | {0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
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| 132 | {0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
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| 133 | {0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
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| 134 | {0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
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| 135 | {0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
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| 136 | {0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
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| 137 | {0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
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| 138 | {0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
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| 139 | {0x0e800100, 0x0fd00ff0, "wmadd%21?su%c\t%12-15g, %16-19g, %0-3g"},
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| 140 | {0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
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| 141 | {0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
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| 142 | {0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%c\t%12-15g, %16-19g, %0-3g"},
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| 143 | {0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
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| 144 | {0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
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| 145 | {0x0e300040, 0x0f300ff0, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
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| 146 | {0x0e300148, 0x0f300ffc, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
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| 147 | {0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
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| 148 | {0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
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| 149 | {0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
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| 150 | {0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
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| 151 | {0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
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| 152 | {0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
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| 153 | {0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
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| 154 | {0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
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| 155 | {0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
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| 156 | {0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
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| 157 | {0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
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| 158 | {0x0e0000c0, 0x0f100fff, "wunpckeh%21?su%22-23w%c\t%12-15g, %16-19g"},
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| 159 | {0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
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| 160 | {0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
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| 161 | {0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
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| 162 | {0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
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| 163 |
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| 164 | /* V5 Instructions. */
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| 165 | {0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
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| 166 | {0xfa000000, 0xfe000000, "blx\t%B"},
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| 167 | {0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"},
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| 168 | {0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"},
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| 169 | {0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"},
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| 170 | {0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"},
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| 171 | {0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
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| 172 | {0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
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| 173 | {0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
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| 174 |
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| 175 | /* V5E "El Segundo" Instructions. */
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| 176 | {0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"},
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| 177 | {0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"},
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| 178 | {0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
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| 179 | {0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
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| 180 | {0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
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| 181 | {0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
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| 182 |
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| 183 | {0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
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| 184 | {0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
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| 185 |
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| 186 | {0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
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| 187 | {0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
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| 188 | {0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
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| 189 | {0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
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| 190 |
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| 191 | {0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"},
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| 192 | {0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"},
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| 193 | {0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"},
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| 194 | {0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"},
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| 195 |
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| 196 | {0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"},
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| 197 | {0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"},
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| 198 |
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| 199 | {0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"},
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| 200 | {0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
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| 201 | {0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"},
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| 202 | {0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
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| 203 |
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| 204 | {0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
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| 205 | {0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
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| 206 |
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| 207 | /* ARM Instructions. */
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| 208 | {0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"},
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| 209 | {0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"},
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| 210 | {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},
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| 211 | {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"},
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| 212 | {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"},
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| 213 | {0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"},
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| 214 | {0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"},
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| 215 | {0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"},
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| 216 | {0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"},
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| 217 | {0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"},
|
|---|
| 218 | {0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
|
|---|
| 219 | {0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
|
|---|
| 220 | {0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"},
|
|---|
| 221 | {0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"},
|
|---|
| 222 | {0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"},
|
|---|
| 223 | {0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"},
|
|---|
| 224 | {0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"},
|
|---|
| 225 | {0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"},
|
|---|
| 226 | {0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"},
|
|---|
| 227 | {0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"},
|
|---|
| 228 | {0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"},
|
|---|
| 229 | {0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"},
|
|---|
| 230 | {0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"},
|
|---|
| 231 | {0x06000010, 0x0e000010, "undefined"},
|
|---|
| 232 | {0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"},
|
|---|
| 233 | {0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
|
|---|
| 234 | {0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
|
|---|
| 235 | {0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
|
|---|
| 236 | {0x0f000000, 0x0f000000, "swi%c\t%0-23x"},
|
|---|
| 237 |
|
|---|
| 238 | /* Floating point coprocessor (FPA) instructions */
|
|---|
| 239 | {0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|---|
| 240 | {0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|---|
| 241 | {0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|---|
| 242 | {0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|---|
| 243 | {0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|---|
| 244 | {0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|---|
| 245 | {0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|---|
| 246 | {0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|---|
| 247 | {0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|---|
| 248 | {0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|---|
| 249 | {0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|---|
| 250 | {0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|---|
| 251 | {0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|---|
| 252 | {0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 253 | {0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 254 | {0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 255 | {0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 256 | {0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 257 | {0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 258 | {0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 259 | {0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 260 | {0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 261 | {0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 262 | {0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 263 | {0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 264 | {0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 265 | {0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 266 | {0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 267 | {0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
|
|---|
| 268 | {0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
|
|---|
| 269 | {0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
|
|---|
| 270 | {0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
|
|---|
| 271 | {0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
|
|---|
| 272 | {0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
|
|---|
| 273 | {0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
|
|---|
| 274 | {0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
|
|---|
| 275 | {0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
|
|---|
| 276 | {0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
|
|---|
| 277 | {0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
|
|---|
| 278 | {0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
|
|---|
| 279 | {0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
|
|---|
| 280 | {0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
|
|---|
| 281 | {0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
|
|---|
| 282 |
|
|---|
| 283 | /* Floating point coprocessor (VFP) instructions */
|
|---|
| 284 | {0x0eb00bc0, 0x0fff0ff0, "fabsd%c\t%1z, %0z"},
|
|---|
| 285 | {0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%1y, %0y"},
|
|---|
| 286 | {0x0e300b00, 0x0ff00ff0, "faddd%c\t%1z, %2z, %0z"},
|
|---|
| 287 | {0x0e300a00, 0x0fb00f50, "fadds%c\t%1y, %2y, %1y"},
|
|---|
| 288 | {0x0eb40b40, 0x0fff0f70, "fcmp%7'ed%c\t%1z, %0z"},
|
|---|
| 289 | {0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%1y, %0y"},
|
|---|
| 290 | {0x0eb50b40, 0x0fff0f70, "fcmp%7'ezd%c\t%1z"},
|
|---|
| 291 | {0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%1y"},
|
|---|
| 292 | {0x0eb00b40, 0x0fff0ff0, "fcpyd%c\t%1z, %0z"},
|
|---|
| 293 | {0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%1y, %0y"},
|
|---|
| 294 | {0x0eb70ac0, 0x0fff0fd0, "fcvtds%c\t%1z, %0y"},
|
|---|
| 295 | {0x0eb70bc0, 0x0fbf0ff0, "fcvtsd%c\t%1y, %0z"},
|
|---|
| 296 | {0x0e800b00, 0x0ff00ff0, "fdivd%c\t%1z, %2z, %0z"},
|
|---|
| 297 | {0x0e800a00, 0x0fb00f50, "fdivs%c\t%1y, %2y, %0y"},
|
|---|
| 298 | {0x0d100b00, 0x0f700f00, "fldd%c\t%1z, %A"},
|
|---|
| 299 | {0x0c900b00, 0x0fd00f00, "fldmia%0?xd%c\t%16-19r%21'!, %3z"},
|
|---|
| 300 | {0x0d300b00, 0x0ff00f00, "fldmdb%0?xd%c\t%16-19r!, %3z"},
|
|---|
| 301 | {0x0d100a00, 0x0f300f00, "flds%c\t%1y, %A"},
|
|---|
| 302 | {0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %3y"},
|
|---|
| 303 | {0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %3y"},
|
|---|
| 304 | {0x0e000b00, 0x0ff00ff0, "fmacd%c\t%1z, %2z, %0z"},
|
|---|
| 305 | {0x0e000a00, 0x0fb00f50, "fmacs%c\t%1y, %2y, %0y"},
|
|---|
| 306 | {0x0e200b10, 0x0ff00fff, "fmdhr%c\t%2z, %12-15r"},
|
|---|
| 307 | {0x0e000b10, 0x0ff00fff, "fmdlr%c\t%2z, %12-15r"},
|
|---|
| 308 | {0x0c400b10, 0x0ff00ff0, "fmdrr%c\t%0z, %12-15r, %16-19r"},
|
|---|
| 309 | {0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %2z"},
|
|---|
| 310 | {0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %2z"},
|
|---|
| 311 | {0x0c500b10, 0x0ff00ff0, "fmrrd%c\t%12-15r, %16-19r, %0z"},
|
|---|
| 312 | {0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %4y"},
|
|---|
| 313 | {0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %2y"},
|
|---|
| 314 | {0x0ef1fa10, 0x0fffffff, "fmstat%c"},
|
|---|
| 315 | {0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"},
|
|---|
| 316 | {0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"},
|
|---|
| 317 | {0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"},
|
|---|
| 318 | {0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"},
|
|---|
| 319 | {0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"},
|
|---|
| 320 | {0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def 0x%16-19x>"},
|
|---|
| 321 | {0x0e100b00, 0x0ff00ff0, "fmscd%c\t%1z, %2z, %0z"},
|
|---|
| 322 | {0x0e100a00, 0x0fb00f50, "fmscs%c\t%1y, %2y, %0y"},
|
|---|
| 323 | {0x0e000a10, 0x0ff00f7f, "fmsr%c\t%2y, %12-15r"},
|
|---|
| 324 | {0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%12-15r, %16-19r, %4y"},
|
|---|
| 325 | {0x0e200b00, 0x0ff00ff0, "fmuld%c\t%1z, %2z, %0z"},
|
|---|
| 326 | {0x0e200a00, 0x0fb00f50, "fmuls%c\t%1y, %2y, %0y"},
|
|---|
| 327 | {0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"},
|
|---|
| 328 | {0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"},
|
|---|
| 329 | {0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"},
|
|---|
| 330 | {0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"},
|
|---|
| 331 | {0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"},
|
|---|
| 332 | {0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def 0x%16-19x>, %12-15r"},
|
|---|
| 333 | {0x0eb10b40, 0x0fff0ff0, "fnegd%c\t%1z, %0z"},
|
|---|
| 334 | {0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%1y, %0y"},
|
|---|
| 335 | {0x0e000b40, 0x0ff00ff0, "fnmacd%c\t%1z, %2z, %0z"},
|
|---|
| 336 | {0x0e000a40, 0x0fb00f50, "fnmacs%c\t%1y, %2y, %0y"},
|
|---|
| 337 | {0x0e100b40, 0x0ff00ff0, "fnmscd%c\t%1z, %2z, %0z"},
|
|---|
| 338 | {0x0e100a40, 0x0fb00f50, "fnmscs%c\t%1y, %2y, %0y"},
|
|---|
| 339 | {0x0e200b40, 0x0ff00ff0, "fnmuld%c\t%1z, %2z, %0z"},
|
|---|
| 340 | {0x0e200a40, 0x0fb00f50, "fnmuls%c\t%1y, %2y, %0y"},
|
|---|
| 341 | {0x0eb80bc0, 0x0fff0fd0, "fsitod%c\t%1z, %0y"},
|
|---|
| 342 | {0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%1y, %0y"},
|
|---|
| 343 | {0x0eb10bc0, 0x0fff0ff0, "fsqrtd%c\t%1z, %0z"},
|
|---|
| 344 | {0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%1y, %0y"},
|
|---|
| 345 | {0x0d000b00, 0x0f700f00, "fstd%c\t%1z, %A"},
|
|---|
| 346 | {0x0c800b00, 0x0fd00f00, "fstmia%0?xd%c\t%16-19r%21'!, %3z"},
|
|---|
| 347 | {0x0d200b00, 0x0ff00f00, "fstmdb%0?xd%c\t%16-19r!, %3z"},
|
|---|
| 348 | {0x0d000a00, 0x0f300f00, "fsts%c\t%1y, %A"},
|
|---|
| 349 | {0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %3y"},
|
|---|
| 350 | {0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %3y"},
|
|---|
| 351 | {0x0e300b40, 0x0ff00ff0, "fsubd%c\t%1z, %2z, %0z"},
|
|---|
| 352 | {0x0e300a40, 0x0fb00f50, "fsubs%c\t%1y, %2y, %0y"},
|
|---|
| 353 | {0x0ebc0b40, 0x0fbe0f70, "fto%16?sui%7'zd%c\t%1y, %0z"},
|
|---|
| 354 | {0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%1y, %0y"},
|
|---|
| 355 | {0x0eb80b40, 0x0fff0fd0, "fuitod%c\t%1z, %0y"},
|
|---|
| 356 | {0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%1y, %0y"},
|
|---|
| 357 |
|
|---|
| 358 | /* Cirrus coprocessor instructions. */
|
|---|
| 359 | {0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
|
|---|
| 360 | {0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
|
|---|
| 361 | {0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
|
|---|
| 362 | {0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
|
|---|
| 363 | {0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
|
|---|
| 364 | {0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
|
|---|
| 365 | {0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
|
|---|
| 366 | {0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
|
|---|
| 367 | {0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
|
|---|
| 368 | {0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
|
|---|
| 369 | {0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
|
|---|
| 370 | {0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
|
|---|
| 371 | {0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
|
|---|
| 372 | {0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
|
|---|
| 373 | {0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
|
|---|
| 374 | {0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
|
|---|
| 375 | {0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
|
|---|
| 376 | {0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
|
|---|
| 377 | {0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
|
|---|
| 378 | {0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
|
|---|
| 379 | {0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
|
|---|
| 380 | {0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
|
|---|
| 381 | {0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
|
|---|
| 382 | {0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
|
|---|
| 383 | {0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
|
|---|
| 384 | {0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
|
|---|
| 385 | {0x0e100610, 0x0ff0fff0, "cfmval32%c\tmvax%0-3d, mvfx%16-19d"},
|
|---|
| 386 | {0x0e000610, 0x0ff0fff0, "cfmv32al%c\tmvfx%0-3d, mvax%16-19d"},
|
|---|
| 387 | {0x0e100630, 0x0ff0fff0, "cfmvam32%c\tmvax%0-3d, mvfx%16-19d"},
|
|---|
| 388 | {0x0e000630, 0x0ff0fff0, "cfmv32am%c\tmvfx%0-3d, mvax%16-19d"},
|
|---|
| 389 | {0x0e100650, 0x0ff0fff0, "cfmvah32%c\tmvax%0-3d, mvfx%16-19d"},
|
|---|
| 390 | {0x0e000650, 0x0ff0fff0, "cfmv32ah%c\tmvfx%0-3d, mvax%16-19d"},
|
|---|
| 391 | {0x0e000670, 0x0ff0fff0, "cfmv32a%c\tmvfx%0-3d, mvax%16-19d"},
|
|---|
| 392 | {0x0e100670, 0x0ff0fff0, "cfmva32%c\tmvax%0-3d, mvfx%16-19d"},
|
|---|
| 393 | {0x0e000690, 0x0ff0fff0, "cfmv64a%c\tmvdx%0-3d, mvax%16-19d"},
|
|---|
| 394 | {0x0e100690, 0x0ff0fff0, "cfmva64%c\tmvax%0-3d, mvdx%16-19d"},
|
|---|
| 395 | {0x0e1006b0, 0x0ff0fff0, "cfmvsc32%c\tdspsc, mvfx%16-19d"},
|
|---|
| 396 | {0x0e0006b0, 0x0ff0fff0, "cfmv32sc%c\tmvfx%0-3d, dspsc"},
|
|---|
| 397 | {0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
|
|---|
| 398 | {0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
|
|---|
| 399 | {0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
|
|---|
| 400 | {0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
|
|---|
| 401 | {0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
|
|---|
| 402 | {0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
|
|---|
| 403 | {0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
|
|---|
| 404 | {0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
|
|---|
| 405 | {0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
|
|---|
| 406 | {0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
|
|---|
| 407 | {0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
|
|---|
| 408 | {0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
|
|---|
| 409 | {0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
|
|---|
| 410 | {0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
|
|---|
| 411 | {0x0e000500, 0x0ff00f00, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
|
|---|
| 412 | {0x0e200500, 0x0ff00f00, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
|
|---|
| 413 | {0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
|
|---|
| 414 | {0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
|
|---|
| 415 | {0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
|
|---|
| 416 | {0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
|
|---|
| 417 | {0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
|
|---|
| 418 | {0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
|
|---|
| 419 | {0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
|
|---|
| 420 | {0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
|
|---|
| 421 | {0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
|
|---|
| 422 | {0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
|
|---|
| 423 | {0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
|
|---|
| 424 | {0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
|
|---|
| 425 | {0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
|
|---|
| 426 | {0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
|
|---|
| 427 | {0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
|
|---|
| 428 | {0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
|
|---|
| 429 | {0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
|
|---|
| 430 | {0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
|
|---|
| 431 | {0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|---|
| 432 | {0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
|
|---|
| 433 | {0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|---|
| 434 | {0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
|
|---|
| 435 | {0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|---|
| 436 | {0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
|
|---|
| 437 | {0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|---|
| 438 | {0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|---|
| 439 | {0x0e000600, 0x0ff00f00, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|---|
| 440 | {0x0e100600, 0x0ff00f00, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|---|
| 441 | {0x0e200600, 0x0ff00f00, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|---|
| 442 | {0x0e300600, 0x0ff00f00, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|---|
| 443 |
|
|---|
| 444 | /* Generic coprocessor instructions */
|
|---|
| 445 | {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
|
|---|
| 446 | {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
|
|---|
| 447 | {0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
|
|---|
| 448 | {0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"},
|
|---|
| 449 | {0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"},
|
|---|
| 450 |
|
|---|
| 451 | /* The rest. */
|
|---|
| 452 | {0x00000000, 0x00000000, "undefined instruction %0-31x"},
|
|---|
| 453 | {0x00000000, 0x00000000, 0}
|
|---|
| 454 | };
|
|---|
| 455 |
|
|---|
| 456 | #define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) /* 26 bit */
|
|---|
| 457 |
|
|---|
| 458 | static const struct thumb_opcode thumb_opcodes[] =
|
|---|
| 459 | {
|
|---|
| 460 | /* Thumb instructions. */
|
|---|
| 461 |
|
|---|
| 462 | /* ARM V5 ISA extends Thumb. */
|
|---|
| 463 | {0xbe00, 0xff00, "bkpt\t%0-7x"},
|
|---|
| 464 | {0x4780, 0xff87, "blx\t%3-6r"}, /* note: 4 bit register number. */
|
|---|
| 465 | /* Note: this is BLX(2). BLX(1) is done in arm-dis.c/print_insn_thumb()
|
|---|
| 466 | as an extension of the special processing there for Thumb BL.
|
|---|
| 467 | BL and BLX(1) involve 2 successive 16-bit instructions, which must
|
|---|
| 468 | always appear together in the correct order. So, the empty
|
|---|
| 469 | string is put in this table, and the string interpreter takes <empty>
|
|---|
| 470 | to mean it has a pair of BL-ish instructions. */
|
|---|
| 471 | {0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"},
|
|---|
| 472 | /* Format 5 instructions do not update the PSR. */
|
|---|
| 473 | {0x1C00, 0xFFC0, "mov\t%0-2r, %3-5r\t\t(add %0-2r, %3-5r, #%6-8d)"},
|
|---|
| 474 | /* Format 4. */
|
|---|
| 475 | {0x4000, 0xFFC0, "and\t%0-2r, %3-5r"},
|
|---|
| 476 | {0x4040, 0xFFC0, "eor\t%0-2r, %3-5r"},
|
|---|
| 477 | {0x4080, 0xFFC0, "lsl\t%0-2r, %3-5r"},
|
|---|
| 478 | {0x40C0, 0xFFC0, "lsr\t%0-2r, %3-5r"},
|
|---|
| 479 | {0x4100, 0xFFC0, "asr\t%0-2r, %3-5r"},
|
|---|
| 480 | {0x4140, 0xFFC0, "adc\t%0-2r, %3-5r"},
|
|---|
| 481 | {0x4180, 0xFFC0, "sbc\t%0-2r, %3-5r"},
|
|---|
| 482 | {0x41C0, 0xFFC0, "ror\t%0-2r, %3-5r"},
|
|---|
| 483 | {0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"},
|
|---|
| 484 | {0x4240, 0xFFC0, "neg\t%0-2r, %3-5r"},
|
|---|
| 485 | {0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"},
|
|---|
| 486 | {0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"},
|
|---|
| 487 | {0x4300, 0xFFC0, "orr\t%0-2r, %3-5r"},
|
|---|
| 488 | {0x4340, 0xFFC0, "mul\t%0-2r, %3-5r"},
|
|---|
| 489 | {0x4380, 0xFFC0, "bic\t%0-2r, %3-5r"},
|
|---|
| 490 | {0x43C0, 0xFFC0, "mvn\t%0-2r, %3-5r"},
|
|---|
| 491 | /* format 13 */
|
|---|
| 492 | {0xB000, 0xFF80, "add\tsp, #%0-6W"},
|
|---|
| 493 | {0xB080, 0xFF80, "sub\tsp, #%0-6W"},
|
|---|
| 494 | /* format 5 */
|
|---|
| 495 | {0x4700, 0xFF80, "bx\t%S"},
|
|---|
| 496 | {0x4400, 0xFF00, "add\t%D, %S"},
|
|---|
| 497 | {0x4500, 0xFF00, "cmp\t%D, %S"},
|
|---|
| 498 | {0x4600, 0xFF00, "mov\t%D, %S"},
|
|---|
| 499 | /* format 14 */
|
|---|
| 500 | {0xB400, 0xFE00, "push\t%N"},
|
|---|
| 501 | {0xBC00, 0xFE00, "pop\t%O"},
|
|---|
| 502 | /* format 2 */
|
|---|
| 503 | {0x1800, 0xFE00, "add\t%0-2r, %3-5r, %6-8r"},
|
|---|
| 504 | {0x1A00, 0xFE00, "sub\t%0-2r, %3-5r, %6-8r"},
|
|---|
| 505 | {0x1C00, 0xFE00, "add\t%0-2r, %3-5r, #%6-8d"},
|
|---|
| 506 | {0x1E00, 0xFE00, "sub\t%0-2r, %3-5r, #%6-8d"},
|
|---|
| 507 | /* format 8 */
|
|---|
| 508 | {0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"},
|
|---|
| 509 | {0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"},
|
|---|
| 510 | {0x5600, 0xF600, "ldrs%11?hb\t%0-2r, [%3-5r, %6-8r]"},
|
|---|
| 511 | /* format 7 */
|
|---|
| 512 | {0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"},
|
|---|
| 513 | {0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"},
|
|---|
| 514 | /* format 1 */
|
|---|
| 515 | {0x0000, 0xF800, "lsl\t%0-2r, %3-5r, #%6-10d"},
|
|---|
| 516 | {0x0800, 0xF800, "lsr\t%0-2r, %3-5r, #%6-10d"},
|
|---|
| 517 | {0x1000, 0xF800, "asr\t%0-2r, %3-5r, #%6-10d"},
|
|---|
| 518 | /* format 3 */
|
|---|
| 519 | {0x2000, 0xF800, "mov\t%8-10r, #%0-7d"},
|
|---|
| 520 | {0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"},
|
|---|
| 521 | {0x3000, 0xF800, "add\t%8-10r, #%0-7d"},
|
|---|
| 522 | {0x3800, 0xF800, "sub\t%8-10r, #%0-7d"},
|
|---|
| 523 | /* format 6 */
|
|---|
| 524 | {0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
|
|---|
| 525 | /* format 9 */
|
|---|
| 526 | {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
|
|---|
| 527 | {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"},
|
|---|
| 528 | {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"},
|
|---|
| 529 | {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"},
|
|---|
| 530 | /* format 10 */
|
|---|
| 531 | {0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"},
|
|---|
| 532 | {0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"},
|
|---|
| 533 | /* format 11 */
|
|---|
| 534 | {0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"},
|
|---|
| 535 | {0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"},
|
|---|
| 536 | /* format 12 */
|
|---|
| 537 | {0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"},
|
|---|
| 538 | {0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"},
|
|---|
| 539 | /* format 15 */
|
|---|
| 540 | {0xC000, 0xF800, "stmia\t%8-10r!,%M"},
|
|---|
| 541 | {0xC800, 0xF800, "ldmia\t%8-10r!,%M"},
|
|---|
| 542 | /* format 18 */
|
|---|
| 543 | {0xE000, 0xF800, "b\t%0-10B"},
|
|---|
| 544 | {0xE800, 0xF800, "undefined"},
|
|---|
| 545 | /* format 19 */
|
|---|
| 546 | {0xF000, 0xF800, ""}, /* special processing required in disassembler */
|
|---|
| 547 | {0xF800, 0xF800, "second half of BL instruction %0-15x"},
|
|---|
| 548 | /* format 16 */
|
|---|
| 549 | {0xD000, 0xFF00, "beq\t%0-7B"},
|
|---|
| 550 | {0xD100, 0xFF00, "bne\t%0-7B"},
|
|---|
| 551 | {0xD200, 0xFF00, "bcs\t%0-7B"},
|
|---|
| 552 | {0xD300, 0xFF00, "bcc\t%0-7B"},
|
|---|
| 553 | {0xD400, 0xFF00, "bmi\t%0-7B"},
|
|---|
| 554 | {0xD500, 0xFF00, "bpl\t%0-7B"},
|
|---|
| 555 | {0xD600, 0xFF00, "bvs\t%0-7B"},
|
|---|
| 556 | {0xD700, 0xFF00, "bvc\t%0-7B"},
|
|---|
| 557 | {0xD800, 0xFF00, "bhi\t%0-7B"},
|
|---|
| 558 | {0xD900, 0xFF00, "bls\t%0-7B"},
|
|---|
| 559 | {0xDA00, 0xFF00, "bge\t%0-7B"},
|
|---|
| 560 | {0xDB00, 0xFF00, "blt\t%0-7B"},
|
|---|
| 561 | {0xDC00, 0xFF00, "bgt\t%0-7B"},
|
|---|
| 562 | {0xDD00, 0xFF00, "ble\t%0-7B"},
|
|---|
| 563 | /* format 17 */
|
|---|
| 564 | {0xDE00, 0xFF00, "bal\t%0-7B"},
|
|---|
| 565 | {0xDF00, 0xFF00, "swi\t%0-7d"},
|
|---|
| 566 | /* format 9 */
|
|---|
| 567 | {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
|
|---|
| 568 | {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"},
|
|---|
| 569 | {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"},
|
|---|
| 570 | {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"},
|
|---|
| 571 | /* the rest */
|
|---|
| 572 | {0x0000, 0x0000, "undefined instruction %0-15x"},
|
|---|
| 573 | {0x0000, 0x0000, 0}
|
|---|
| 574 | };
|
|---|
| 575 |
|
|---|
| 576 | #define BDISP23(x) ((((((x) & 0x07ff) << 11) | (((x) & 0x07ff0000) >> 16)) \
|
|---|
| 577 | ^ 0x200000) - 0x200000) /* 23bit */
|
|---|
| 578 |
|
|---|
