| 1 | /* Xtensa configuration settings.
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| 2 | Copyright (C) 2003 Free Software Foundation, Inc.
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| 3 | Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
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| 4 |
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| 5 | This program is free software; you can redistribute it and/or modify
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| 6 | it under the terms of the GNU General Public License as published by
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| 7 | the Free Software Foundation; either version 2, or (at your option)
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| 8 | any later version.
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| 9 |
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| 10 | This program is distributed in the hope that it will be useful, but
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| 11 | WITHOUT ANY WARRANTY; without even the implied warranty of
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| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 13 | General Public License for more details.
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| 14 |
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| 15 | You should have received a copy of the GNU General Public License
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| 16 | along with this program; if not, write to the Free Software
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| 17 | Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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| 18 |
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| 19 | #ifndef XTENSA_CONFIG_H
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| 20 | #define XTENSA_CONFIG_H
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| 21 |
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| 22 | /* The macros defined here match those with the same names in the Xtensa
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| 23 | compile-time HAL (Hardware Abstraction Layer). Please refer to the
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| 24 | Xtensa System Software Reference Manual for documentation of these
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| 25 | macros. */
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| 26 |
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| 27 | #define XCHAL_HAVE_BE 1
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| 28 | #define XCHAL_HAVE_DENSITY 1
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| 29 | #define XCHAL_HAVE_MAC16 0
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| 30 | #define XCHAL_HAVE_MUL16 0
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| 31 | #define XCHAL_HAVE_MUL32 0
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| 32 | #define XCHAL_HAVE_DIV32 0
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| 33 | #define XCHAL_HAVE_NSA 1
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| 34 | #define XCHAL_HAVE_MINMAX 0
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| 35 | #define XCHAL_HAVE_SEXT 0
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| 36 | #define XCHAL_HAVE_LOOPS 1
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| 37 | #define XCHAL_HAVE_BOOLEANS 0
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| 38 | #define XCHAL_HAVE_FP 0
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| 39 | #define XCHAL_HAVE_FP_DIV 0
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| 40 | #define XCHAL_HAVE_FP_RECIP 0
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| 41 | #define XCHAL_HAVE_FP_SQRT 0
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| 42 | #define XCHAL_HAVE_FP_RSQRT 0
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| 43 | #define XCHAL_HAVE_WINDOWED 1
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| 44 |
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| 45 | #define XCHAL_ICACHE_SIZE 8192
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| 46 | #define XCHAL_DCACHE_SIZE 8192
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| 47 | #define XCHAL_ICACHE_LINESIZE 16
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| 48 | #define XCHAL_DCACHE_LINESIZE 16
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| 49 | #define XCHAL_ICACHE_LINEWIDTH 4
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| 50 | #define XCHAL_DCACHE_LINEWIDTH 4
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| 51 | #define XCHAL_DCACHE_IS_WRITEBACK 0
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| 52 |
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| 53 | #define XCHAL_HAVE_MMU 1
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| 54 | #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
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| 55 |
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| 56 | #define XCHAL_HAVE_DEBUG 1
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| 57 | #define XCHAL_NUM_IBREAK 2
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| 58 | #define XCHAL_NUM_DBREAK 2
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| 59 | #define XCHAL_DEBUGLEVEL 4
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| 60 |
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| 61 | #define XCHAL_EXTRA_SA_SIZE 0
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| 62 | #define XCHAL_EXTRA_SA_ALIGN 1
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| 63 |
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| 64 | #endif /* !XTENSA_CONFIG_H */
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