| 1 | /* Definitions for opcode table for the sparc.
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| 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002
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| 3 | Free Software Foundation, Inc.
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| 4 |
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| 5 | This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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| 6 | the GNU Binutils.
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| 7 |
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| 8 | GAS/GDB is free software; you can redistribute it and/or modify
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| 9 | it under the terms of the GNU General Public License as published by
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| 10 | the Free Software Foundation; either version 2, or (at your option)
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| 11 | any later version.
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| 12 |
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| 13 | GAS/GDB is distributed in the hope that it will be useful,
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| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 16 | GNU General Public License for more details.
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| 17 |
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| 18 | You should have received a copy of the GNU General Public License
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| 19 | along with GAS or GDB; see the file COPYING. If not, write to
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| 20 | the Free Software Foundation, 59 Temple Place - Suite 330,
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| 21 | Boston, MA 02111-1307, USA. */
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| 22 |
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| 23 | #include "ansidecl.h"
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| 24 |
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| 25 | /* The SPARC opcode table (and other related data) is defined in
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| 26 | the opcodes library in sparc-opc.c. If you change anything here, make
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| 27 | sure you fix up that file, and vice versa. */
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| 28 |
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| 29 | /* FIXME-someday: perhaps the ,a's and such should be embedded in the
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| 30 | instruction's name rather than the args. This would make gas faster, pinsn
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| 31 | slower, but would mess up some macros a bit. xoxorich. */
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| 32 |
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| 33 | /* List of instruction sets variations.
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| 34 | These values are such that each element is either a superset of a
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| 35 | preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
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| 36 | returns non-zero.
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| 37 | The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
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| 38 | Don't change this without updating sparc-opc.c. */
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| 39 |
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| 40 | enum sparc_opcode_arch_val {
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| 41 | SPARC_OPCODE_ARCH_V6 = 0,
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| 42 | SPARC_OPCODE_ARCH_V7,
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| 43 | SPARC_OPCODE_ARCH_V8,
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| 44 | SPARC_OPCODE_ARCH_SPARCLET,
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| 45 | SPARC_OPCODE_ARCH_SPARCLITE,
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| 46 | /* v9 variants must appear last */
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| 47 | SPARC_OPCODE_ARCH_V9,
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| 48 | SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */
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| 49 | SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */
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| 50 | SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */
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| 51 | };
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| 52 |
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| 53 | /* The highest architecture in the table. */
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| 54 | #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
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| 55 |
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| 56 | /* Given an enum sparc_opcode_arch_val, return the bitmask to use in
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| 57 | insn encoding/decoding. */
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| 58 | #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
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| 59 |
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| 60 | /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
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| 61 | #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
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| 62 |
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| 63 | /* Table of cpu variants. */
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| 64 |
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| 65 | struct sparc_opcode_arch {
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| 66 | const char *name;
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| 67 | /* Mask of sparc_opcode_arch_val's supported.
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| 68 | EG: For v7 this would be
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| 69 | (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
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| 70 | These are short's because sparc_opcode.architecture is. */
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| 71 | short supported;
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| 72 | };
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| 73 |
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| 74 | extern const struct sparc_opcode_arch sparc_opcode_archs[];
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| 75 |
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| 76 | /* Given architecture name, look up it's sparc_opcode_arch_val value. */
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| 77 | extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch
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| 78 | PARAMS ((const char *));
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| 79 |
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| 80 | /* Return the bitmask of supported architectures for ARCH. */
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| 81 | #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
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| 82 |
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| 83 | /* Non-zero if ARCH1 conflicts with ARCH2.
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| 84 | IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
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| 85 | #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
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| 86 | (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
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| 87 | != SPARC_OPCODE_SUPPORTED (ARCH1)) \
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| 88 | && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
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| 89 | != SPARC_OPCODE_SUPPORTED (ARCH2)))
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| 90 |
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| 91 | /* Structure of an opcode table entry. */
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| 92 |
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| 93 | struct sparc_opcode {
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| 94 | const char *name;
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| 95 | unsigned long match; /* Bits that must be set. */
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| 96 | unsigned long lose; /* Bits that must not be set. */
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| 97 | const char *args;
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| 98 | /* This was called "delayed" in versions before the flags. */
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| 99 | char flags;
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| 100 | short architecture; /* Bitmask of sparc_opcode_arch_val's. */
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| 101 | };
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| 102 |
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| 103 | #define F_DELAYED 1 /* Delayed branch */
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| 104 | #define F_ALIAS 2 /* Alias for a "real" instruction */
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| 105 | #define F_UNBR 4 /* Unconditional branch */
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| 106 | #define F_CONDBR 8 /* Conditional branch */
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| 107 | #define F_JSR 16 /* Subroutine call */
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| 108 | #define F_FLOAT 32 /* Floating point instruction (not a branch) */
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| 109 | #define F_FBR 64 /* Floating point branch */
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| 110 | /* FIXME: Add F_ANACHRONISTIC flag for v9. */
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| 111 |
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| 112 | /*
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| 113 |
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| 114 | All sparc opcodes are 32 bits, except for the `set' instruction (really a
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| 115 | macro), which is 64 bits. It is handled as a special case.
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| 116 |
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| 117 | The match component is a mask saying which bits must match a particular
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| 118 | opcode in order for an instruction to be an instance of that opcode.
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| 119 |
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| 120 | The args component is a string containing one character for each operand of the
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| 121 | instruction.
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| 122 |
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| 123 | Kinds of operands:
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| 124 | # Number used by optimizer. It is ignored.
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| 125 | 1 rs1 register.
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| 126 | 2 rs2 register.
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| 127 | d rd register.
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| 128 | e frs1 floating point register.
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| 129 | v frs1 floating point register (double/even).
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| 130 | V frs1 floating point register (quad/multiple of 4).
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| 131 | f frs2 floating point register.
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| 132 | B frs2 floating point register (double/even).
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| 133 | R frs2 floating point register (quad/multiple of 4).
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| 134 | g frsd floating point register.
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| 135 | H frsd floating point register (double/even).
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| 136 | J frsd floating point register (quad/multiple of 4).
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| 137 | b crs1 coprocessor register
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| 138 | c crs2 coprocessor register
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| 139 | D crsd coprocessor register
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| 140 | m alternate space register (asr) in rd
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| 141 | M alternate space register (asr) in rs1
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| 142 | h 22 high bits.
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| 143 | X 5 bit unsigned immediate
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| 144 | Y 6 bit unsigned immediate
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| 145 | 3 SIAM mode (3 bits). (v9b)
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| 146 | K MEMBAR mask (7 bits). (v9)
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| 147 | j 10 bit Immediate. (v9)
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| 148 | I 11 bit Immediate. (v9)
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| 149 | i 13 bit Immediate.
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| 150 | n 22 bit immediate.
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| 151 | k 2+14 bit PC relative immediate. (v9)
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| 152 | G 19 bit PC relative immediate. (v9)
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| 153 | l 22 bit PC relative immediate.
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| 154 | L 30 bit PC relative immediate.
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| 155 | a Annul. The annul bit is set.
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| 156 | A Alternate address space. Stored as 8 bits.
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| 157 | C Coprocessor state register.
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| 158 | F floating point state register.
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| 159 | p Processor state register.
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| 160 | N Branch predict clear ",pn" (v9)
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| 161 | T Branch predict set ",pt" (v9)
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| 162 | z %icc. (v9)
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| 163 | Z %xcc. (v9)
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| 164 | q Floating point queue.
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| 165 | r Single register that is both rs1 and rd.
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| 166 | O Single register that is both rs2 and rd.
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| 167 | Q Coprocessor queue.
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| 168 | S Special case.
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| 169 | t Trap base register.
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| 170 | w Window invalid mask register.
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| 171 | y Y register.
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| 172 | u sparclet coprocessor registers in rd position
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| 173 | U sparclet coprocessor registers in rs1 position
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| 174 | E %ccr. (v9)
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| 175 | s %fprs. (v9)
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| 176 | P %pc. (v9)
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| 177 | W %tick. (v9)
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| 178 | o %asi. (v9)
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| 179 | 6 %fcc0. (v9)
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| 180 | 7 %fcc1. (v9)
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| 181 | 8 %fcc2. (v9)
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| 182 | 9 %fcc3. (v9)
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| 183 | ! Privileged Register in rd (v9)
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| 184 | ? Privileged Register in rs1 (v9)
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| 185 | * Prefetch function constant. (v9)
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| 186 | x OPF field (v9 impdep).
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| 187 | 0 32/64 bit immediate for set or setx (v9) insns
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| 188 | _ Ancillary state register in rd (v9a)
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| 189 | / Ancillary state register in rs1 (v9a)
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| 190 |
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| 191 | The following chars are unused: (note: ,[] are used as punctuation)
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| 192 | [45]
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| 193 |
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| 194 | */
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| 195 |
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| 196 | #define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */
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| 197 | #define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */
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| 198 | #define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */
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| 199 | #define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */
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| 200 | #define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */
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| 201 | #define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
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| 202 | #define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */
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| 203 | #define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */
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| 204 | #define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */
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| 205 | #define F1(x) (OP(x))
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| 206 | #define DISP30(x) ((x)&0x3fffffff)
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| 207 | #define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */
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| 208 | #define RS2(x) ((x)&0x1f) /* rs2 field */
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| 209 | #define SIMM13(x) ((x)&0x1fff) /* simm13 field */
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| 210 | #define RD(x) (((x)&0x1f) << 25) /* destination register field */
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| 211 | #define RS1(x) (((x)&0x1f) << 14) /* rs1 field */
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| 212 | #define ASI_RS2(x) (SIMM13(x))
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| 213 | #define MEMBAR(x) ((x)&0x7f)
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| 214 | #define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */
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| 215 |
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| 216 | #define ANNUL (1<<29)
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| 217 | #define BPRED (1<<19) /* v9 */
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| 218 | #define IMMED F3I(1)
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| 219 | #define RD_G0 RD(~0)
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| 220 | #define RS1_G0 RS1(~0)
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| 221 | #define RS2_G0 RS2(~0)
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| 222 |
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| 223 | extern const struct sparc_opcode sparc_opcodes[];
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| 224 | extern const int sparc_num_opcodes;
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| 225 |
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| 226 | extern int sparc_encode_asi PARAMS ((const char *));
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| 227 | extern const char *sparc_decode_asi PARAMS ((int));
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| 228 | extern int sparc_encode_membar PARAMS ((const char *));
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| 229 | extern const char *sparc_decode_membar PARAMS ((int));
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| 230 | extern int sparc_encode_prefetch PARAMS ((const char *));
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| 231 | extern const char *sparc_decode_prefetch PARAMS ((int));
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| 232 | extern int sparc_encode_sparclet_cpreg PARAMS ((const char *));
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| 233 | extern const char *sparc_decode_sparclet_cpreg PARAMS ((int));
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| 234 |
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| 235 | /*
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| 236 | * Local Variables:
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| 237 | * fill-column: 131
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| 238 | * comment-column: 0
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| 239 | * End:
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| 240 | */
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| 241 |
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| 242 | /* end of sparc.h */
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