source: trunk/binutils/include/opcode/mips.h@ 2672

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1/* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Ralph Campbell and OSF
5 Commented and modified by Ian Lance Taylor, Cygnus Support
6
7This file is part of GDB, GAS, and the GNU binutils.
8
9GDB, GAS, and the GNU binutils are free software; you can redistribute
10them and/or modify them under the terms of the GNU General Public
11License as published by the Free Software Foundation; either version
121, or (at your option) any later version.
13
14GDB, GAS, and the GNU binutils are distributed in the hope that they
15will be useful, but WITHOUT ANY WARRANTY; without even the implied
16warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
17the GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with this file; see the file COPYING. If not, write to the Free
21Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22
23#ifndef _MIPS_H_
24#define _MIPS_H_
25
26/* These are bit masks and shift counts to use to access the various
27 fields of an instruction. To retrieve the X field of an
28 instruction, use the expression
29 (i >> OP_SH_X) & OP_MASK_X
30 To set the same field (to j), use
31 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
32
33 Make sure you use fields that are appropriate for the instruction,
34 of course.
35
36 The 'i' format uses OP, RS, RT and IMMEDIATE.
37
38 The 'j' format uses OP and TARGET.
39
40 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
41
42 The 'b' format uses OP, RS, RT and DELTA.
43
44 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
45
46 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
47
48 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
49 breakpoint instruction are not defined; Kane says the breakpoint
50 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
51 only use ten bits). An optional two-operand form of break/sdbbp
52 allows the lower ten bits to be set too, and MIPS32 and later
53 architectures allow 20 bits to be set with a signal operand
54 (using CODE20).
55
56 The syscall instruction uses CODE20.
57
58 The general coprocessor instructions use COPZ. */
59
60#define OP_MASK_OP 0x3f
61#define OP_SH_OP 26
62#define OP_MASK_RS 0x1f
63#define OP_SH_RS 21
64#define OP_MASK_FR 0x1f
65#define OP_SH_FR 21
66#define OP_MASK_FMT 0x1f
67#define OP_SH_FMT 21
68#define OP_MASK_BCC 0x7
69#define OP_SH_BCC 18
70#define OP_MASK_CODE 0x3ff
71#define OP_SH_CODE 16
72#define OP_MASK_CODE2 0x3ff
73#define OP_SH_CODE2 6
74#define OP_MASK_RT 0x1f
75#define OP_SH_RT 16
76#define OP_MASK_FT 0x1f
77#define OP_SH_FT 16
78#define OP_MASK_CACHE 0x1f
79#define OP_SH_CACHE 16
80#define OP_MASK_RD 0x1f
81#define OP_SH_RD 11
82#define OP_MASK_FS 0x1f
83#define OP_SH_FS 11
84#define OP_MASK_PREFX 0x1f
85#define OP_SH_PREFX 11
86#define OP_MASK_CCC 0x7
87#define OP_SH_CCC 8
88#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
89#define OP_SH_CODE20 6
90#define OP_MASK_SHAMT 0x1f
91#define OP_SH_SHAMT 6
92#define OP_MASK_FD 0x1f
93#define OP_SH_FD 6
94#define OP_MASK_TARGET 0x3ffffff
95#define OP_SH_TARGET 0
96#define OP_MASK_COPZ 0x1ffffff
97#define OP_SH_COPZ 0
98#define OP_MASK_IMMEDIATE 0xffff
99#define OP_SH_IMMEDIATE 0
100#define OP_MASK_DELTA 0xffff
101#define OP_SH_DELTA 0
102#define OP_MASK_FUNCT 0x3f
103#define OP_SH_FUNCT 0
104#define OP_MASK_SPEC 0x3f
105#define OP_SH_SPEC 0
106#define OP_SH_LOCC 8 /* FP condition code. */
107#define OP_SH_HICC 18 /* FP condition code. */
108#define OP_MASK_CC 0x7
109#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
110#define OP_MASK_COP1NORM 0x1 /* a single bit. */
111#define OP_SH_COP1SPEC 21 /* COP1 encodings. */
112#define OP_MASK_COP1SPEC 0xf
113#define OP_MASK_COP1SCLR 0x4
114#define OP_MASK_COP1CMP 0x3
115#define OP_SH_COP1CMP 4
116#define OP_SH_FORMAT 21 /* FP short format field. */
117#define OP_MASK_FORMAT 0x7
118#define OP_SH_TRUE 16
119#define OP_MASK_TRUE 0x1
120#define OP_SH_GE 17
121#define OP_MASK_GE 0x01
122#define OP_SH_UNSIGNED 16
123#define OP_MASK_UNSIGNED 0x1
124#define OP_SH_HINT 16
125#define OP_MASK_HINT 0x1f
126#define OP_SH_MMI 0 /* Multimedia (parallel) op. */
127#define OP_MASK_MMI 0x3f
128#define OP_SH_MMISUB 6
129#define OP_MASK_MMISUB 0x1f
130#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
131#define OP_SH_PERFREG 1
132#define OP_SH_SEL 0 /* Coprocessor select field. */
133#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
134#define OP_SH_CODE19 6 /* 19 bit wait code. */
135#define OP_MASK_CODE19 0x7ffff
136#define OP_SH_ALN 21
137#define OP_MASK_ALN 0x7
138#define OP_SH_VSEL 21
139#define OP_MASK_VSEL 0x1f
140#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
141 but 0x8-0xf don't select bytes. */
142#define OP_SH_VECBYTE 22
143#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
144#define OP_SH_VECALIGN 21
145#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
146#define OP_SH_INSMSB 11
147#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
148#define OP_SH_EXTMSBD 11
149
150#define OP_OP_COP0 0x10
151#define OP_OP_COP1 0x11
152#define OP_OP_COP2 0x12
153#define OP_OP_COP3 0x13
154#define OP_OP_LWC1 0x31
155#define OP_OP_LWC2 0x32
156#define OP_OP_LWC3 0x33 /* a.k.a. pref */
157#define OP_OP_LDC1 0x35
158#define OP_OP_LDC2 0x36
159#define OP_OP_LDC3 0x37 /* a.k.a. ld */
160#define OP_OP_SWC1 0x39
161#define OP_OP_SWC2 0x3a
162#define OP_OP_SWC3 0x3b
163#define OP_OP_SDC1 0x3d
164#define OP_OP_SDC2 0x3e
165#define OP_OP_SDC3 0x3f /* a.k.a. sd */
166
167/* Values in the 'VSEL' field. */
168#define MDMX_FMTSEL_IMM_QH 0x1d
169#define MDMX_FMTSEL_IMM_OB 0x1e
170#define MDMX_FMTSEL_VEC_QH 0x15
171#define MDMX_FMTSEL_VEC_OB 0x16
172
173/* This structure holds information for a particular instruction. */
174
175struct mips_opcode
176{
177 /* The name of the instruction. */
178 const char *name;
179 /* A string describing the arguments for this instruction. */
180 const char *args;
181 /* The basic opcode for the instruction. When assembling, this
182 opcode is modified by the arguments to produce the actual opcode
183 that is used. If pinfo is INSN_MACRO, then this is 0. */
184 unsigned long match;
185 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
186 relevant portions of the opcode when disassembling. If the
187 actual opcode anded with the match field equals the opcode field,
188 then we have found the correct instruction. If pinfo is
189 INSN_MACRO, then this field is the macro identifier. */
190 unsigned long mask;
191 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
192 of bits describing the instruction, notably any relevant hazard
193 information. */
194 unsigned long pinfo;
195 /* A collection of bits describing the instruction sets of which this
196 instruction or macro is a member. */
197 unsigned long membership;
198};
199
200/* These are the characters which may appear in the args field of an
201 instruction. They appear in the order in which the fields appear
202 when the instruction is used. Commas and parentheses in the args
203 string are ignored when assembling, and written into the output
204 when disassembling.
205
206 Each of these characters corresponds to a mask field defined above.
207
208 "<" 5 bit shift amount (OP_*_SHAMT)
209 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
210 "a" 26 bit target address (OP_*_TARGET)
211 "b" 5 bit base register (OP_*_RS)
212 "c" 10 bit breakpoint code (OP_*_CODE)
213 "d" 5 bit destination register specifier (OP_*_RD)
214 "h" 5 bit prefx hint (OP_*_PREFX)
215 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
216 "j" 16 bit signed immediate (OP_*_DELTA)
217 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
218 Also used for immediate operands in vr5400 vector insns.
219 "o" 16 bit signed offset (OP_*_DELTA)
220 "p" 16 bit PC relative branch target address (OP_*_DELTA)
221 "q" 10 bit extra breakpoint code (OP_*_CODE2)
222 "r" 5 bit same register used as both source and target (OP_*_RS)
223 "s" 5 bit source register specifier (OP_*_RS)
224 "t" 5 bit target register (OP_*_RT)
225 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
226 "v" 5 bit same register used as both source and destination (OP_*_RS)
227 "w" 5 bit same register used as both target and destination (OP_*_RT)
228 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
229 (used by clo and clz)
230 "C" 25 bit coprocessor function code (OP_*_COPZ)
231 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
232 "J" 19 bit wait function code (OP_*_CODE19)
233 "x" accept and ignore register name
234 "z" must be zero register
235 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
236 "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
237 Enforces: 0 <= pos < 32.
238 "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
239 Requires that "+A" occur first to set position.
240 Enforces: 0 < (pos+size) <= 32.
241 "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
242 Requires that "+A" occur first to set position.
243 Enforces: 0 < (pos+size) <= 32.
244
245 Floating point instructions:
246 "D" 5 bit destination register (OP_*_FD)
247 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
248 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
249 "S" 5 bit fs source 1 register (OP_*_FS)
250 "T" 5 bit ft source 2 register (OP_*_FT)
251 "R" 5 bit fr source 3 register (OP_*_FR)
252 "V" 5 bit same register used as floating source and destination (OP_*_FS)
253 "W" 5 bit same register used as floating target and destination (OP_*_FT)
254
255 Coprocessor instructions:
256 "E" 5 bit target register (OP_*_RT)
257 "G" 5 bit destination register (OP_*_RD)
258 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
259 "P" 5 bit performance-monitor register (OP_*_PERFREG)
260 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
261 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
262 see also "k" above
263 "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
264 for pretty-printing in disassembly only.
265
266 Macro instructions:
267 "A" General 32 bit expression
268 "I" 32 bit immediate
269 "F" 64 bit floating point constant in .rdata
270 "L" 64 bit floating point constant in .lit8
271 "f" 32 bit floating point constant
272 "l" 32 bit floating point constant in .lit4
273
274 MDMX instruction operands (note that while these use the FP register
275 fields, they accept both $fN and $vN names for the registers):
276 "O" MDMX alignment offset (OP_*_ALN)
277 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
278 "X" MDMX destination register (OP_*_FD)
279 "Y" MDMX source register (OP_*_FS)
280 "Z" MDMX source register (OP_*_FT)
281
282 Other:
283 "()" parens surrounding optional value
284 "," separates operands
285 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
286 "+" Start of extension sequence.
287
288 Characters used so far, for quick reference when adding more:
289 "%[]<>(),+"
290 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
291 "abcdefhijklopqrstuvwxz"
292
293 Extension character sequences used so far ("+" followed by the
294 following), for quick reference when adding more:
295 "ABCD"
296*/
297
298/* These are the bits which may be set in the pinfo field of an
299 instructions, if it is not equal to INSN_MACRO. */
300
301/* Modifies the general purpose register in OP_*_RD. */
302#define INSN_WRITE_GPR_D 0x00000001
303/* Modifies the general purpose register in OP_*_RT. */
304#define INSN_WRITE_GPR_T 0x00000002
305/* Modifies general purpose register 31. */
306#define INSN_WRITE_GPR_31 0x00000004
307/* Modifies the floating point register in OP_*_FD. */
308#define INSN_WRITE_FPR_D 0x00000008
309/* Modifies the floating point register in OP_*_FS. */
310#define INSN_WRITE_FPR_S 0x00000010
311/* Modifies the floating point register in OP_*_FT. */
312#define INSN_WRITE_FPR_T 0x00000020
313/* Reads the general purpose register in OP_*_RS. */
314#define INSN_READ_GPR_S 0x00000040
315/* Reads the general purpose register in OP_*_RT. */
316#define INSN_READ_GPR_T 0x00000080
317/* Reads the floating point register in OP_*_FS. */
318#define INSN_READ_FPR_S 0x00000100
319/* Reads the floating point register in OP_*_FT. */
320#define INSN_READ_FPR_T 0x00000200
321/* Reads the floating point register in OP_*_FR. */
322#define INSN_READ_FPR_R 0x00000400
323/* Modifies coprocessor condition code. */
324#define INSN_WRITE_COND_CODE 0x00000800
325/* Reads coprocessor condition code. */
326#define INSN_READ_COND_CODE 0x00001000
327/* TLB operation. */
328#define INSN_TLB 0x00002000
329/* Reads coprocessor register other than floating point register. */
330#define INSN_COP 0x00004000
331/* Instruction loads value from memory, requiring delay. */
332#define INSN_LOAD_MEMORY_DELAY 0x00008000
333/* Instruction loads value from coprocessor, requiring delay. */
334#define INSN_LOAD_COPROC_DELAY 0x00010000
335/* Instruction has unconditional branch delay slot. */
336#define INSN_UNCOND_BRANCH_DELAY 0x00020000
337/* Instruction has conditional branch delay slot. */
338#define INSN_COND_BRANCH_DELAY 0x00040000
339/* Conditional branch likely: if branch not taken, insn nullified. */
340#define INSN_COND_BRANCH_LIKELY 0x00080000
341/* Moves to coprocessor register, requiring delay. */
342#define INSN_COPROC_MOVE_DELAY 0x00100000
343/* Loads coprocessor register from memory, requiring delay. */
344#define INSN_COPROC_MEMORY_DELAY 0x00200000
345/* Reads the HI register. */
346#define INSN_READ_HI 0x00400000
347/* Reads the LO register. */
348#define INSN_READ_LO 0x00800000
349/* Modifies the HI register. */
350#define INSN_WRITE_HI 0x01000000
351/* Modifies the LO register. */
352#define INSN_WRITE_LO 0x02000000
353/* Takes a trap (easier to keep out of delay slot). */
354#define INSN_TRAP 0x04000000
355/* Instruction stores value into memory. */
356#define INSN_STORE_MEMORY 0x08000000
357/* Instruction uses single precision floating point. */
358#define FP_S 0x10000000
359/* Instruction uses double precision floating point. */
360#define FP_D 0x20000000
361/* Instruction is part of the tx39's integer multiply family. */
362#define INSN_MULT 0x40000000
363/* Instruction synchronize shared memory. */
364#define INSN_SYNC 0x80000000
365/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */
366#define INSN_READ_MDMX_ACC 0
367/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */
368#define INSN_WRITE_MDMX_ACC 0
369
370/* Instruction is actually a macro. It should be ignored by the
371 disassembler, and requires special treatment by the assembler. */
372#define INSN_MACRO 0xffffffff
373
374/* Masks used to mark instructions to indicate which MIPS ISA level
375 they were introduced in. ISAs, as defined below, are logical
376 ORs of these bits, indicating that they support the instructions
377 defined at the given level. */
378
379#define INSN_ISA_MASK 0x00000fff
380#define INSN_ISA1 0x00000001
381#define INSN_ISA2 0x00000002
382#define INSN_ISA3 0x00000004
383#define INSN_ISA4 0x00000008
384#define INSN_ISA5 0x00000010
385#define INSN_ISA32 0x00000020
386#define INSN_ISA64 0x00000040
387#define INSN_ISA32R2 0x00000080
388
389/* Masks used for MIPS-defined ASEs. */
390#define INSN_ASE_MASK 0x0000f000
391
392/* MIPS 16 ASE */
393#define INSN_MIPS16 0x00002000
394/* MIPS-3D ASE */
395#define INSN_MIPS3D 0x00004000
396/* MDMX ASE */
397#define INSN_MDMX 0x00008000
398
399/* Chip specific instructions. These are bitmasks. */
400
401/* MIPS R4650 instruction. */
402#define INSN_4650 0x00010000
403/* LSI R4010 instruction. */
404#define INSN_4010 0x00020000
405/* NEC VR4100 instruction. */
406#define INSN_4100 0x00040000
407/* Toshiba R3900 instruction. */
408#define INSN_3900 0x00080000
409/* MIPS R10000 instruction. */
410#define INSN_10000 0x00100000
411/* Broadcom SB-1 instruction. */
412#define INSN_SB1 0x00200000
413/* NEC VR4111/VR4181 instruction. */
414#define INSN_4111 0x00400000
415/* NEC VR4120 instruction. */
416#define INSN_4120 0x00800000
417/* NEC VR5400 instruction. */
418#define INSN_5400 0x01000000
419/* NEC VR5500 instruction. */
420#define INSN_5500 0x02000000
421
422/* MIPS ISA defines, use instead of hardcoding ISA level. */
423
424#define ISA_UNKNOWN 0 /* Gas internal use. */
425#define ISA_MIPS1 (INSN_ISA1)
426#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
427#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
428#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
429#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
430
431#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
432#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
433
434#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
435
436/* CPU defines, use instead of hardcoding processor number. Keep this
437 in sync with bfd/archures.c in order for machine selection to work. */
438#define CPU_UNKNOWN 0 /* Gas internal use. */
439#define CPU_R3000 3000
440#define CPU_R3900 3900
441#define CPU_R4000 4000
442#define CPU_R4010 4010
443#define CPU_VR4100 4100
444#define CPU_R4111 4111
445#define CPU_VR4120 4120
446#define CPU_R4300 4300
447#define CPU_R4400 4400
448#define CPU_R4600 4600
449#define CPU_R4650 4650
450#define CPU_R5000 5000
451#define CPU_VR5400 5400
452#define CPU_VR5500 5500
453#define CPU_R6000 6000
454#define CPU_R8000 8000
455#define CPU_R10000 10000
456#define CPU_R12000 12000
457#define CPU_MIPS16 16
458#define CPU_MIPS32 32
459#define CPU_MIPS32R2 33
460#define CPU_MIPS5 5
461#define CPU_MIPS64 64
462#define CPU_SB1 12310201 /* octal 'SB', 01. */
463
464/* Test for membership in an ISA including chip specific ISAs. INSN
465 is pointer to an element of the opcode table; ISA is the specified
466 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
467 test, or zero if no CPU specific ISA test is desired. */
468
469#define OPCODE_IS_MEMBER(insn, isa, cpu) \
470 (((insn)->membership & isa) != 0 \
471 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
472 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
473 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
474 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
475 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
476 && ((insn)->membership & INSN_10000) != 0) \
477 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
478 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
479 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
480 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
481 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
482 || 0) /* Please keep this term for easier source merging. */
483
484/* This is a list of macro expanded instructions.
485
486 _I appended means immediate
487 _A appended means address
488 _AB appended means address with base register
489 _D appended means 64 bit floating point constant
490 _S appended means 32 bit floating point constant. */
491
492enum
493{
494 M_ABS,
495 M_ADD_I,
496 M_ADDU_I,
497 M_AND_I,
498 M_BEQ,
499 M_BEQ_I,
500 M_BEQL_I,
501 M_BGE,
502 M_BGEL,
503 M_BGE_I,
504 M_BGEL_I,
505 M_BGEU,
506 M_BGEUL,
507 M_BGEU_I,
508 M_BGEUL_I,
509 M_BGT,
510 M_BGTL,
511 M_BGT_I,
512 M_BGTL_I,
513 M_BGTU,
514 M_BGTUL,
515 M_BGTU_I,
516 M_BGTUL_I,
517 M_BLE,
518 M_BLEL,
519 M_BLE_I,
520 M_BLEL_I,
521 M_BLEU,
522 M_BLEUL,
523 M_BLEU_I,
524 M_BLEUL_I,
525 M_BLT,
526 M_BLTL,
527 M_BLT_I,
528 M_BLTL_I,
529 M_BLTU,
530 M_BLTUL,
531 M_BLTU_I,
532 M_BLTUL_I,
533 M_BNE,
534 M_BNE_I,
535 M_BNEL_I,
536 M_DABS,
537 M_DADD_I,
538 M_DADDU_I,
539 M_DDIV_3,
540 M_DDIV_3I,
541 M_DDIVU_3,
542 M_DDIVU_3I,
543 M_DIV_3,
544 M_DIV_3I,
545 M_DIVU_3,
546 M_DIVU_3I,
547 M_DLA_AB,
548 M_DLI,
549 M_DMUL,
550 M_DMUL_I,
551 M_DMULO,
552 M_DMULO_I,
553 M_DMULOU,
554 M_DMULOU_I,
555 M_DREM_3,
556 M_DREM_3I,
557 M_DREMU_3,
558 M_DREMU_3I,
559 M_DSUB_I,
560 M_DSUBU_I,
561 M_DSUBU_I_2,
562 M_J_A,
563 M_JAL_1,
564 M_JAL_2,
565 M_JAL_A,
566 M_L_DOB,
567 M_L_DAB,
568 M_LA_AB,
569 M_LB_A,
570 M_LB_AB,
571 M_LBU_A,
572 M_LBU_AB,
573 M_LD_A,
574 M_LD_OB,
575 M_LD_AB,
576 M_LDC1_AB,
577 M_LDC2_AB,
578 M_LDC3_AB,
579 M_LDL_AB,
580 M_LDR_AB,
581 M_LH_A,
582 M_LH_AB,
583 M_LHU_A,
584 M_LHU_AB,
585 M_LI,
586 M_LI_D,
587 M_LI_DD,
588 M_LI_S,
589 M_LI_SS,
590 M_LL_AB,
591 M_LLD_AB,
592 M_LS_A,
593 M_LW_A,
594 M_LW_AB,
595 M_LWC0_A,
596 M_LWC0_AB,
597 M_LWC1_A,
598 M_LWC1_AB,
599 M_LWC2_A,
600 M_LWC2_AB,
601 M_LWC3_A,
602 M_LWC3_AB,
603 M_LWL_A,
604 M_LWL_AB,
605 M_LWR_A,
606 M_LWR_AB,
607 M_LWU_AB,
608 M_MOVE,
609 M_MUL,
610 M_MUL_I,
611 M_MULO,
612 M_MULO_I,
613 M_MULOU,
614 M_MULOU_I,
615 M_NOR_I,
616 M_OR_I,
617 M_REM_3,
618 M_REM_3I,
619 M_REMU_3,
620 M_REMU_3I,
621 M_DROL,
622 M_ROL,
623 M_DROL_I,
624 M_ROL_I,
625 M_DROR,
626 M_ROR,
627 M_DROR_I,
628 M_ROR_I,
629 M_S_DA,
630 M_S_DOB,
631 M_S_DAB,
632 M_S_S,
633 M_SC_AB,
634 M_SCD_AB,
635 M_SD_A,
636 M_SD_OB,
637 M_SD_AB,
638 M_SDC1_AB,
639 M_SDC2_AB,
640 M_SDC3_AB,
641 M_SDL_AB,
642 M_SDR_AB,
643 M_SEQ,
644 M_SEQ_I,
645 M_SGE,
646 M_SGE_I,
647 M_SGEU,
648 M_SGEU_I,
649 M_SGT,
650 M_SGT_I,
651 M_SGTU,
652 M_SGTU_I,
653 M_SLE,
654 M_SLE_I,
655 M_SLEU,
656 M_SLEU_I,
657 M_SLT_I,
658 M_SLTU_I,
659 M_SNE,
660 M_SNE_I,
661 M_SB_A,
662 M_SB_AB,
663 M_SH_A,
664 M_SH_AB,
665 M_SW_A,
666 M_SW_AB,
667 M_SWC0_A,
668 M_SWC0_AB,
669 M_SWC1_A,
670 M_SWC1_AB,
671 M_SWC2_A,
672 M_SWC2_AB,
673 M_SWC3_A,
674 M_SWC3_AB,
675 M_SWL_A,
676 M_SWL_AB,
677 M_SWR_A,
678 M_SWR_AB,
679 M_SUB_I,
680 M_SUBU_I,
681 M_SUBU_I_2,
682 M_TEQ_I,
683 M_TGE_I,
684 M_TGEU_I,
685 M_TLT_I,
686 M_TLTU_I,
687 M_TNE_I,
688 M_TRUNCWD,
689 M_TRUNCWS,
690 M_ULD,
691 M_ULD_A,
692 M_ULH,
693 M_ULH_A,
694 M_ULHU,
695 M_ULHU_A,
696 M_ULW,
697 M_ULW_A,
698 M_USH,
699 M_USH_A,
700 M_USW,
701 M_USW_A,
702 M_USD,
703 M_USD_A,
704 M_XOR_I,
705 M_COP0,
706 M_COP1,
707 M_COP2,
708 M_COP3,
709 M_NUM_MACROS
710};
711
712
713/* The order of overloaded instructions matters. Label arguments and
714 register arguments look the same. Instructions that can have either
715 for arguments must apear in the correct order in this table for the
716 assembler to pick the right one. In other words, entries with
717 immediate operands must apear after the same instruction with
718 registers.
719
720 Many instructions are short hand for other instructions (i.e., The
721 jal <register> instruction is short for jalr <register>). */
722
723extern const struct mips_opcode mips_builtin_opcodes[];
724extern const int bfd_mips_num_builtin_opcodes;
725extern struct mips_opcode *mips_opcodes;
726extern int bfd_mips_num_opcodes;
727#define NUMOPCODES bfd_mips_num_opcodes
728
729
730
731/* The rest of this file adds definitions for the mips16 TinyRISC
732 processor. */
733
734/* These are the bitmasks and shift counts used for the different
735 fields in the instruction formats. Other than OP, no masks are
736 provided for the fixed portions of an instruction, since they are
737 not needed.
738
739 The I format uses IMM11.
740
741 The RI format uses RX and IMM8.
742
743 The RR format uses RX, and RY.
744
745 The RRI format uses RX, RY, and IMM5.
746
747 The RRR format uses RX, RY, and RZ.
748
749 The RRI_A format uses RX, RY, and IMM4.
750
751 The SHIFT format uses RX, RY, and SHAMT.
752
753 The I8 format uses IMM8.
754
755 The I8_MOVR32 format uses RY and REGR32.
756
757 The IR_MOV32R format uses REG32R and MOV32Z.
758
759 The I64 format uses IMM8.
760
761 The RI64 format uses RY and IMM5.
762 */
763
764#define MIPS16OP_MASK_OP 0x1f
765#define MIPS16OP_SH_OP 11
766#define MIPS16OP_MASK_IMM11 0x7ff
767#define MIPS16OP_SH_IMM11 0
768#define MIPS16OP_MASK_RX 0x7
769#define MIPS16OP_SH_RX 8
770#define MIPS16OP_MASK_IMM8 0xff
771#define MIPS16OP_SH_IMM8 0
772#define MIPS16OP_MASK_RY 0x7
773#define MIPS16OP_SH_RY 5
774#define MIPS16OP_MASK_IMM5 0x1f
775#define MIPS16OP_SH_IMM5 0
776#define MIPS16OP_MASK_RZ 0x7
777#define MIPS16OP_SH_RZ 2
778#define MIPS16OP_MASK_IMM4 0xf
779#define MIPS16OP_SH_IMM4 0
780#define MIPS16OP_MASK_REGR32 0x1f
781#define MIPS16OP_SH_REGR32 0
782#define MIPS16OP_MASK_REG32R 0x1f
783#define MIPS16OP_SH_REG32R 3
784#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
785#define MIPS16OP_MASK_MOVE32Z 0x7
786#define MIPS16OP_SH_MOVE32Z 0
787#define MIPS16OP_MASK_IMM6 0x3f
788#define MIPS16OP_SH_IMM6 5
789
790/* These are the characters which may appears in the args field of an
791 instruction. They appear in the order in which the fields appear
792 when the instruction is used. Commas and parentheses in the args
793 string are ignored when assembling, and written into the output
794 when disassembling.
795
796 "y" 3 bit register (MIPS16OP_*_RY)
797 "x" 3 bit register (MIPS16OP_*_RX)
798 "z" 3 bit register (MIPS16OP_*_RZ)
799 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
800 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
801 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
802 "0" zero register ($0)
803 "S" stack pointer ($sp or $29)
804 "P" program counter
805 "R" return address register ($ra or $31)
806 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
807 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
808 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
809 "a" 26 bit jump address
810 "e" 11 bit extension value
811 "l" register list for entry instruction
812 "L" register list for exit instruction
813
814 The remaining codes may be extended. Except as otherwise noted,
815 the full extended operand is a 16 bit signed value.
816 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
817 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
818 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
819 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
820 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
821 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
822 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
823 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
824 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
825 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
826 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
827 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
828 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
829 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
830 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
831 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
832 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
833 "q" 11 bit branch address (MIPS16OP_*_IMM11)
834 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
835 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
836 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
837 */
838
839/* For the mips16, we use the same opcode table format and a few of
840 the same flags. However, most of the flags are different. */
841
842/* Modifies the register in MIPS16OP_*_RX. */
843#define MIPS16_INSN_WRITE_X 0x00000001
844/* Modifies the register in MIPS16OP_*_RY. */
845#define MIPS16_INSN_WRITE_Y 0x00000002
846/* Modifies the register in MIPS16OP_*_RZ. */
847#define MIPS16_INSN_WRITE_Z 0x00000004
848/* Modifies the T ($24) register. */
849#define MIPS16_INSN_WRITE_T 0x00000008
850/* Modifies the SP ($29) register. */
851#define MIPS16_INSN_WRITE_SP 0x00000010
852/* Modifies the RA ($31) register. */
853#define MIPS16_INSN_WRITE_31 0x00000020
854/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
855#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
856/* Reads the register in MIPS16OP_*_RX. */
857#define MIPS16_INSN_READ_X 0x00000080
858/* Reads the register in MIPS16OP_*_RY. */
859#define MIPS16_INSN_READ_Y 0x00000100
860/* Reads the register in MIPS16OP_*_MOVE32Z. */
861#define MIPS16_INSN_READ_Z 0x00000200
862/* Reads the T ($24) register. */
863#define MIPS16_INSN_READ_T 0x00000400
864/* Reads the SP ($29) register. */
865#define MIPS16_INSN_READ_SP 0x00000800
866/* Reads the RA ($31) register. */
867#define MIPS16_INSN_READ_31 0x00001000
868/* Reads the program counter. */
869#define MIPS16_INSN_READ_PC 0x00002000
870/* Reads the general purpose register in MIPS16OP_*_REGR32. */
871#define MIPS16_INSN_READ_GPR_X 0x00004000
872/* Is a branch insn. */
873#define MIPS16_INSN_BRANCH 0x00010000
874
875/* The following flags have the same value for the mips16 opcode
876 table:
877 INSN_UNCOND_BRANCH_DELAY
878 INSN_COND_BRANCH_DELAY
879 INSN_COND_BRANCH_LIKELY (never used)
880 INSN_READ_HI
881 INSN_READ_LO
882 INSN_WRITE_HI
883 INSN_WRITE_LO
884 INSN_TRAP
885 INSN_ISA3
886 */
887
888extern const struct mips_opcode mips16_opcodes[];
889extern const int bfd_mips16_num_opcodes;
890
891#endif /* _MIPS_H_ */
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