| 1 | /* Opcode table header for m680[01234]0/m6888[12]/m68851.
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| 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001
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| 3 | Free Software Foundation, Inc.
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| 4 |
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| 5 | This file is part of GDB, GAS, and the GNU binutils.
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| 6 |
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| 7 | GDB, GAS, and the GNU binutils are free software; you can redistribute
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| 8 | them and/or modify them under the terms of the GNU General Public
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| 9 | License as published by the Free Software Foundation; either version
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| 10 | 1, or (at your option) any later version.
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| 11 |
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| 12 | GDB, GAS, and the GNU binutils are distributed in the hope that they
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| 13 | will be useful, but WITHOUT ANY WARRANTY; without even the implied
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| 14 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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| 15 | the GNU General Public License for more details.
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| 16 |
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| 17 | You should have received a copy of the GNU General Public License
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| 18 | along with this file; see the file COPYING. If not, write to the Free
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| 19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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| 20 | 02111-1307, USA. */
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| 21 |
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| 22 | /* These are used as bit flags for the arch field in the m68k_opcode
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| 23 | structure. */
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| 24 | #define _m68k_undef 0
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| 25 | #define m68000 0x001
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| 26 | #define m68008 m68000 /* synonym for -m68000. otherwise unused. */
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| 27 | #define m68010 0x002
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| 28 | #define m68020 0x004
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| 29 | #define m68030 0x008
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| 30 | #define m68ec030 m68030 /* similar enough to -m68030 to ignore differences;
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| 31 | gas will deal with the few differences. */
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| 32 | #define m68040 0x010
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| 33 | /* there is no 68050 */
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| 34 | #define m68060 0x020
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| 35 | #define m68881 0x040
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| 36 | #define m68882 m68881 /* synonym for -m68881. otherwise unused. */
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| 37 | #define m68851 0x080
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| 38 | #define cpu32 0x100 /* e.g., 68332 */
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| 39 | #define mcf5200 0x200
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| 40 | #define mcf5206e 0x400
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| 41 | #define mcf5307 0x800
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| 42 | #define mcf5407 0x1000
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| 43 |
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| 44 | /* handy aliases */
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| 45 | #define m68040up (m68040 | m68060)
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| 46 | #define m68030up (m68030 | m68040up)
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| 47 | #define m68020up (m68020 | m68030up)
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| 48 | #define m68010up (m68010 | cpu32 | m68020up)
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| 49 | #define m68000up (m68000 | m68010up)
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| 50 | #define mcf (mcf5200 | mcf5206e | mcf5307 | mcf5407)
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| 51 | #define mcf5307up (mcf5307 | mcf5407)
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| 52 |
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| 53 | #define mfloat (m68881 | m68882 | m68040 | m68060)
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| 54 | #define mmmu (m68851 | m68030 | m68040 | m68060)
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| 55 |
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| 56 | /* The structure used to hold information for an opcode. */
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| 57 |
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| 58 | struct m68k_opcode
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| 59 | {
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| 60 | /* The opcode name. */
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| 61 | const char *name;
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| 62 | /* The opcode itself. */
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| 63 | unsigned long opcode;
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| 64 | /* The mask used by the disassembler. */
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| 65 | unsigned long match;
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| 66 | /* The arguments. */
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| 67 | const char *args;
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| 68 | /* The architectures which support this opcode. */
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| 69 | unsigned int arch;
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| 70 | };
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| 71 |
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| 72 | /* The structure used to hold information for an opcode alias. */
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| 73 |
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| 74 | struct m68k_opcode_alias
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| 75 | {
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| 76 | /* The alias name. */
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| 77 | const char *alias;
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| 78 | /* The instruction for which this is an alias. */
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| 79 | const char *primary;
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| 80 | };
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| 81 |
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| 82 | /* We store four bytes of opcode for all opcodes because that is the
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| 83 | most any of them need. The actual length of an instruction is
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| 84 | always at least 2 bytes, and is as much longer as necessary to hold
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| 85 | the operands it has.
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| 86 |
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| 87 | The match field is a mask saying which bits must match particular
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| 88 | opcode in order for an instruction to be an instance of that
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| 89 | opcode.
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| 90 |
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| 91 | The args field is a string containing two characters for each
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| 92 | operand of the instruction. The first specifies the kind of
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| 93 | operand; the second, the place it is stored. */
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| 94 |
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| 95 | /* Kinds of operands:
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| 96 | Characters used: AaBCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWXYZ0123|*~%;@!&$?/<>#^+-
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| 97 |
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| 98 | D data register only. Stored as 3 bits.
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| 99 | A address register only. Stored as 3 bits.
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| 100 | a address register indirect only. Stored as 3 bits.
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| 101 | R either kind of register. Stored as 4 bits.
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| 102 | r either kind of register indirect only. Stored as 4 bits.
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| 103 | At the moment, used only for cas2 instruction.
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| 104 | F floating point coprocessor register only. Stored as 3 bits.
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| 105 | O an offset (or width): immediate data 0-31 or data register.
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| 106 | Stored as 6 bits in special format for BF... insns.
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| 107 | + autoincrement only. Stored as 3 bits (number of the address register).
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| 108 | - autodecrement only. Stored as 3 bits (number of the address register).
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| 109 | Q quick immediate data. Stored as 3 bits.
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| 110 | This matches an immediate operand only when value is in range 1 .. 8.
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| 111 | M moveq immediate data. Stored as 8 bits.
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| 112 | This matches an immediate operand only when value is in range -128..127
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| 113 | T trap vector immediate data. Stored as 4 bits.
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| 114 |
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| 115 | k K-factor for fmove.p instruction. Stored as a 7-bit constant or
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| 116 | a three bit register offset, depending on the field type.
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| 117 |
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| 118 | # immediate data. Stored in special places (b, w or l)
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| 119 | which say how many bits to store.
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| 120 | ^ immediate data for floating point instructions. Special places
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| 121 | are offset by 2 bytes from '#'...
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| 122 | B pc-relative address, converted to an offset
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| 123 | that is treated as immediate data.
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| 124 | d displacement and register. Stores the register as 3 bits
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| 125 | and stores the displacement in the entire second word.
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| 126 |
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| 127 | C the CCR. No need to store it; this is just for filtering validity.
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| 128 | S the SR. No need to store, just as with CCR.
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| 129 | U the USP. No need to store, just as with CCR.
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| 130 | E the ACC. No need to store, just as with CCR.
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| 131 | G the MACSR. No need to store, just as with CCR.
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| 132 | H the MASK. No need to store, just as with CCR.
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| 133 |
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| 134 | I Coprocessor ID. Not printed if 1. The Coprocessor ID is always
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| 135 | extracted from the 'd' field of word one, which means that an extended
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| 136 | coprocessor opcode can be skipped using the 'i' place, if needed.
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| 137 |
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| 138 | s System Control register for the floating point coprocessor.
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| 139 |
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| 140 | J Misc register for movec instruction, stored in 'j' format.
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| 141 | Possible values:
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| 142 | 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10]
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| 143 | 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10]
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| 144 | 0x002 CACR Cache Control Register [60, 40, 30, 20]
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| 145 | 0x003 TC MMU Translation Control [60, 40]
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| 146 | 0x004 ITT0 Instruction Transparent
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| 147 | Translation reg 0 [60, 40]
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| 148 | 0x005 ITT1 Instruction Transparent
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| 149 | Translation reg 1 [60, 40]
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| 150 | 0x006 DTT0 Data Transparent
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| 151 | Translation reg 0 [60, 40]
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| 152 | 0x007 DTT1 Data Transparent
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| 153 | Translation reg 1 [60, 40]
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| 154 | 0x008 BUSCR Bus Control Register [60]
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| 155 | 0x800 USP User Stack Pointer [60, 40, 30, 20, 10]
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| 156 | 0x801 VBR Vector Base reg [60, 40, 30, 20, 10]
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| 157 | 0x802 CAAR Cache Address Register [ 30, 20]
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| 158 | 0x803 MSP Master Stack Pointer [ 40, 30, 20]
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| 159 | 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20]
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| 160 | 0x805 MMUSR MMU Status reg [ 40]
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| 161 | 0x806 URP User Root Pointer [60, 40]
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| 162 | 0x807 SRP Supervisor Root Pointer [60, 40]
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| 163 | 0x808 PCR Processor Configuration reg [60]
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| 164 | 0xC00 ROMBAR ROM Base Address Register [520X]
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| 165 | 0xC04 RAMBAR0 RAM Base Address Register 0 [520X]
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| 166 | 0xC05 RAMBAR1 RAM Base Address Register 0 [520X]
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| 167 | 0xC0F MBAR0 RAM Base Address Register 0 [520X]
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| 168 |
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| 169 | L Register list of the type d0-d7/a0-a7 etc.
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| 170 | (New! Improved! Can also hold fp0-fp7, as well!)
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| 171 | The assembler tries to see if the registers match the insn by
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| 172 | looking at where the insn wants them stored.
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| 173 |
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| 174 | l Register list like L, but with all the bits reversed.
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| 175 | Used for going the other way. . .
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| 176 |
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| 177 | c cache identifier which may be "nc" for no cache, "ic"
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| 178 | for instruction cache, "dc" for data cache, or "bc"
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| 179 | for both caches. Used in cinv and cpush. Always
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| 180 | stored in position "d".
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| 181 |
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| 182 | u Any register, with ``upper'' or ``lower'' specification. Used
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| 183 | in the mac instructions with size word.
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| 184 |
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| 185 | The remainder are all stored as 6 bits using an address mode and a
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| 186 | register number; they differ in which addressing modes they match.
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| 187 |
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| 188 | * all (modes 0-6,7.0-4)
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| 189 | ~ alterable memory (modes 2-6,7.0,7.1)
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| 190 | (not 0,1,7.2-4)
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| 191 | % alterable (modes 0-6,7.0,7.1)
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| 192 | (not 7.2-4)
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| 193 | ; data (modes 0,2-6,7.0-4)
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| 194 | (not 1)
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| 195 | @ data, but not immediate (modes 0,2-6,7.0-3)
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| 196 | (not 1,7.4)
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| 197 | ! control (modes 2,5,6,7.0-3)
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| 198 | (not 0,1,3,4,7.4)
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| 199 | & alterable control (modes 2,5,6,7.0,7.1)
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| 200 | (not 0,1,7.2-4)
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| 201 | $ alterable data (modes 0,2-6,7.0,7.1)
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| 202 | (not 1,7.2-4)
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| 203 | ? alterable control, or data register (modes 0,2,5,6,7.0,7.1)
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| 204 | (not 1,3,4,7.2-4)
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| 205 | / control, or data register (modes 0,2,5,6,7.0-3)
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| 206 | (not 1,3,4,7.4)
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| 207 | > *save operands (modes 2,4,5,6,7.0,7.1)
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| 208 | (not 0,1,3,7.2-4)
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| 209 | < *restore operands (modes 2,3,5,6,7.0-3)
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| 210 | (not 0,1,4,7.4)
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| 211 |
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| 212 | coldfire move operands:
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| 213 | m (modes 0-4)
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| 214 | n (modes 5,7.2)
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| 215 | o (modes 6,7.0,7.1,7.3,7.4)
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| 216 | p (modes 0-5)
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| 217 |
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| 218 | coldfire bset/bclr/btst/mulsl/mulul operands:
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| 219 | q (modes 0,2-5)
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| 220 | v (modes 0,2-5,7.0,7.1)
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| 221 | */
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| 222 |
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| 223 | /* For the 68851: */
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| 224 | /*
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| 225 | I didn't use much imagination in choosing the
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| 226 | following codes, so many of them aren't very
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| 227 | mnemonic. -rab
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| 228 |
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| 229 | 0 32 bit pmmu register
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| 230 | Possible values:
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| 231 | 000 TC Translation Control Register (68030, 68851)
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| 232 |
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| 233 | 1 16 bit pmmu register
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| 234 | 111 AC Access Control (68851)
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| 235 |
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| 236 | 2 8 bit pmmu register
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| 237 | 100 CAL Current Access Level (68851)
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| 238 | 101 VAL Validate Access Level (68851)
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| 239 | 110 SCC Stack Change Control (68851)
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| 240 |
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| 241 | 3 68030-only pmmu registers (32 bit)
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| 242 | 010 TT0 Transparent Translation reg 0
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| 243 | (aka Access Control reg 0 -- AC0 -- on 68ec030)
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| 244 | 011 TT1 Transparent Translation reg 1
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| 245 | (aka Access Control reg 1 -- AC1 -- on 68ec030)
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| 246 |
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| 247 | W wide pmmu registers
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| 248 | Possible values:
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| 249 | 001 DRP Dma Root Pointer (68851)
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| 250 | 010 SRP Supervisor Root Pointer (68030, 68851)
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| 251 | 011 CRP Cpu Root Pointer (68030, 68851)
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| 252 |
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| 253 | f function code register (68030, 68851)
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| 254 | 0 SFC
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| 255 | 1 DFC
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| 256 |
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| 257 | V VAL register only (68851)
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| 258 |
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| 259 | X BADx, BACx (16 bit)
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| 260 | 100 BAD Breakpoint Acknowledge Data (68851)
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| 261 | 101 BAC Breakpoint Acknowledge Control (68851)
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| 262 |
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| 263 | Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
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| 264 | Z PCSR (68851)
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| 265 |
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| 266 | | memory (modes 2-6, 7.*)
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| 267 |
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| 268 | t address test level (68030 only)
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| 269 | Stored as 3 bits, range 0-7.
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| 270 | Also used for breakpoint instruction now.
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| 271 |
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| 272 | */
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| 273 |
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| 274 | /* Places to put an operand, for non-general operands:
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| 275 | Characters used: BbCcDdghijkLlMmNnostWw123456789
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| 276 |
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| 277 | s source, low bits of first word.
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| 278 | d dest, shifted 9 in first word
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| 279 | 1 second word, shifted 12
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| 280 | 2 second word, shifted 6
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| 281 | 3 second word, shifted 0
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| 282 | 4 third word, shifted 12
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| 283 | 5 third word, shifted 6
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| 284 | 6 third word, shifted 0
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| 285 | 7 second word, shifted 7
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| 286 | 8 second word, shifted 10
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| 287 | 9 second word, shifted 5
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| 288 | D store in both place 1 and place 3; for divul and divsl.
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| 289 | B first word, low byte, for branch displacements
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| 290 | W second word (entire), for branch displacements
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| 291 | L second and third words (entire), for branch displacements
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| 292 | (also overloaded for move16)
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| 293 | b second word, low byte
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| 294 | w second word (entire) [variable word/long branch offset for dbra]
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| 295 | W second word (entire) (must be signed 16 bit value)
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| 296 | l second and third word (entire)
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| 297 | g variable branch offset for bra and similar instructions.
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| 298 | The place to store depends on the magnitude of offset.
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| 299 | t store in both place 7 and place 8; for floating point operations
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| 300 | c branch offset for cpBcc operations.
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| 301 | The place to store is word two if bit six of word one is zero,
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| 302 | and words two and three if bit six of word one is one.
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| 303 | i Increment by two, to skip over coprocessor extended operands. Only
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| 304 | works with the 'I' format.
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| 305 | k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number.
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| 306 | Also used for dynamic fmovem instruction.
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| 307 | C floating point coprocessor constant - 7 bits. Also used for static
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| 308 | K-factors...
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| 309 | j Movec register #, stored in 12 low bits of second word.
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| 310 | m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
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| 311 | and remaining 3 bits of register shifted 9 bits in first word.
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| 312 | Indicate upper/lower in 1 bit shifted 7 bits in second word.
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| 313 | Use with `R' or `u' format.
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| 314 | n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
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| 315 | with MSB shifted 6 bits in first word and remaining 3 bits of
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| 316 | register shifted 9 bits in first word. No upper/lower
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| 317 | indication is done.) Use with `R' or `u' format.
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| 318 | o For M[S]ACw; 4 bits shifted 12 in second word (like `1').
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| 319 | Indicate upper/lower in 1 bit shifted 7 bits in second word.
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| 320 | Use with `R' or `u' format.
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| 321 | M For M[S]ACw; 4 bits in low bits of first word. Indicate
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| 322 | upper/lower in 1 bit shifted 6 bits in second word. Use with
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| 323 | `R' or `u' format.
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| 324 | N For M[S]ACw; 4 bits in low bits of second word. Indicate
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| 325 | upper/lower in 1 bit shifted 6 bits in second word. Use with
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| 326 | `R' or `u' format.
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| 327 | h shift indicator (scale factor), 1 bit shifted 10 in second word
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| 328 |
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| 329 | Places to put operand, for general operands:
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| 330 | d destination, shifted 6 bits in first word
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| 331 | b source, at low bit of first word, and immediate uses one byte
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| 332 | w source, at low bit of first word, and immediate uses two bytes
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| 333 | l source, at low bit of first word, and immediate uses four bytes
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| 334 | s source, at low bit of first word.
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| 335 | Used sometimes in contexts where immediate is not allowed anyway.
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| 336 | f single precision float, low bit of 1st word, immediate uses 4 bytes
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| 337 | F double precision float, low bit of 1st word, immediate uses 8 bytes
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| 338 | x extended precision float, low bit of 1st word, immediate uses 12 bytes
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| 339 | p packed float, low bit of 1st word, immediate uses 12 bytes
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| 340 | */
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| 341 |
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| 342 | extern const struct m68k_opcode m68k_opcodes[];
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| 343 | extern const struct m68k_opcode_alias m68k_opcode_aliases[];
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| 344 |
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| 345 | extern const int m68k_numopcodes, m68k_numaliases;
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| 346 |
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| 347 | /* end of m68k-opcode.h */
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