source: trunk/binutils/include/opcode/a29k.h@ 3450

Last change on this file since 3450 was 610, checked in by bird, 22 years ago

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1/* Table of opcodes for the AMD 29000 family.
2 Copyright 1990, 1991, 1993, 1994, 2002 Free Software Foundation, Inc.
3
4This file is part of GDB and GAS.
5
6This program is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2 of the License, or
9(at your option) any later version.
10
11This program is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with this program; if not, write to the Free Software
18Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19
20struct a29k_opcode {
21 /* Name of the instruction. */
22 char *name;
23
24 /* Opcode word */
25 unsigned long opcode;
26
27 /* A string of characters which describe the operands.
28 Valid characters are:
29 , Itself. The character appears in the assembly code.
30 a RA. The register number is in bits 8-15 of the instruction.
31 b RB. The register number is in bits 0-7 of the instruction.
32 c RC. The register number is in bits 16-23 of the instruction.
33 i An immediate operand is in bits 0-7 of the instruction.
34 x Bits 0-7 and 16-23 of the instruction are bits 0-7 and 8-15
35 (respectively) of the immediate operand.
36 h Same as x but the instruction contains bits 16-31 of the
37 immediate operand.
38 X Same as x but bits 16-31 of the signed immediate operand
39 are set to 1 (thus the operand is always negative).
40 P,A Bits 0-7 and 16-23 of the instruction are bits 2-9 and 10-17
41 (respectively) of the immediate operand.
42 P=PC-relative, sign-extended to 32 bits.
43 A=Absolute, zero-extended to 32 bits.
44 e CE bit (bit 23) for a load/store instruction.
45 n Control field (bits 16-22) for a load/store instruction.
46 v Immediate operand in bits 16-23 of the instruction.
47 (used for trap numbers).
48 s SA. Special-purpose register number in bits 8-15
49 of the instruction.
50 u UI--bit 7 of the instruction.
51 r RND--bits 4-6 of the instruction.
52 d FD--bits 2-3 of the instruction.
53 f FS--bits 0-1 of the instruction.
54 I ID--bits 16-17 of the instruction.
55
56 Extensions for 29050:
57
58 d FMT--bits 2-3 of the instruction (not really new).
59 f ACN--bits 0-1 of the instruction (not really new).
60 F FUNC--Special function in bits 18-21 of the instruction.
61 C ACN--bits 16-17 specifying the accumlator register. */
62 char *args;
63};
64
65static const struct a29k_opcode a29k_opcodes[] =
66{
67
68{ "add", 0x14000000, "c,a,b" },
69{ "add", 0x15000000, "c,a,i" },
70{ "addc", 0x1c000000, "c,a,b" },
71{ "addc", 0x1d000000, "c,a,i" },
72{ "addcs", 0x18000000, "c,a,b" },
73{ "addcs", 0x19000000, "c,a,i" },
74{ "addcu", 0x1a000000, "c,a,b" },
75{ "addcu", 0x1b000000, "c,a,i" },
76{ "adds", 0x10000000, "c,a,b" },
77{ "adds", 0x11000000, "c,a,i" },
78{ "addu", 0x12000000, "c,a,b" },
79{ "addu", 0x13000000, "c,a,i" },
80{ "and", 0x90000000, "c,a,b" },
81{ "and", 0x91000000, "c,a,i" },
82{ "andn", 0x9c000000, "c,a,b" },
83{ "andn", 0x9d000000, "c,a,i" },
84{ "aseq", 0x70000000, "v,a,b" },
85{ "aseq", 0x71000000, "v,a,i" },
86{ "asge", 0x5c000000, "v,a,b" },
87{ "asge", 0x5d000000, "v,a,i" },
88{ "asgeu", 0x5e000000, "v,a,b" },
89{ "asgeu", 0x5f000000, "v,a,i" },
90{ "asgt", 0x58000000, "v,a,b" },
91{ "asgt", 0x59000000, "v,a,i" },
92{ "asgtu", 0x5a000000, "v,a,b" },
93{ "asgtu", 0x5b000000, "v,a,i" },
94{ "asle", 0x54000000, "v,a,b" },
95{ "asle", 0x55000000, "v,a,i" },
96{ "asleu", 0x56000000, "v,a,b" },
97{ "asleu", 0x57000000, "v,a,i" },
98{ "aslt", 0x50000000, "v,a,b" },
99{ "aslt", 0x51000000, "v,a,i" },
100{ "asltu", 0x52000000, "v,a,b" },
101{ "asltu", 0x53000000, "v,a,i" },
102{ "asneq", 0x72000000, "v,a,b" },
103{ "asneq", 0x73000000, "v,a,i" },
104{ "call", 0xa8000000, "a,P" },
105{ "call", 0xa9000000, "a,A" },
106{ "calli", 0xc8000000, "a,b" },
107{ "class", 0xe6000000, "c,a,f" },
108{ "clz", 0x08000000, "c,b" },
109{ "clz", 0x09000000, "c,i" },
110{ "const", 0x03000000, "a,x" },
111{ "consth", 0x02000000, "a,h" },
112{ "consthz", 0x05000000, "a,h" },
113{ "constn", 0x01000000, "a,X" },
114{ "convert", 0xe4000000, "c,a,u,r,d,f" },
115{ "cpbyte", 0x2e000000, "c,a,b" },
116{ "cpbyte", 0x2f000000, "c,a,i" },
117{ "cpeq", 0x60000000, "c,a,b" },
118{ "cpeq", 0x61000000, "c,a,i" },
119{ "cpge", 0x4c000000, "c,a,b" },
120{ "cpge", 0x4d000000, "c,a,i" },
121{ "cpgeu", 0x4e000000, "c,a,b" },
122{ "cpgeu", 0x4f000000, "c,a,i" },
123{ "cpgt", 0x48000000, "c,a,b" },
124{ "cpgt", 0x49000000, "c,a,i" },
125{ "cpgtu", 0x4a000000, "c,a,b" },
126{ "cpgtu", 0x4b000000, "c,a,i" },
127{ "cple", 0x44000000, "c,a,b" },
128{ "cple", 0x45000000, "c,a,i" },
129{ "cpleu", 0x46000000, "c,a,b" },
130{ "cpleu", 0x47000000, "c,a,i" },
131{ "cplt", 0x40000000, "c,a,b" },
132{ "cplt", 0x41000000, "c,a,i" },
133{ "cpltu", 0x42000000, "c,a,b" },
134{ "cpltu", 0x43000000, "c,a,i" },
135{ "cpneq", 0x62000000, "c,a,b" },
136{ "cpneq", 0x63000000, "c,a,i" },
137{ "dadd", 0xf1000000, "c,a,b" },
138{ "ddiv", 0xf7000000, "c,a,b" },
139{ "deq", 0xeb000000, "c,a,b" },
140{ "dge", 0xef000000, "c,a,b" },
141{ "dgt", 0xed000000, "c,a,b" },
142{ "div", 0x6a000000, "c,a,b" },
143{ "div", 0x6b000000, "c,a,i" },
144{ "div0", 0x68000000, "c,b" },
145{ "div0", 0x69000000, "c,i" },
146{ "divide", 0xe1000000, "c,a,b" },
147{ "dividu", 0xe3000000, "c,a,b" },
148{ "divl", 0x6c000000, "c,a,b" },
149{ "divl", 0x6d000000, "c,a,i" },
150{ "divrem", 0x6e000000, "c,a,b" },
151{ "divrem", 0x6f000000, "c,a,i" },
152{ "dmac", 0xd9000000, "F,C,a,b" },
153{ "dmsm", 0xdb000000, "c,a,b" },
154{ "dmul", 0xf5000000, "c,a,b" },
155{ "dsub", 0xf3000000, "c,a,b" },
156{ "emulate", 0xd7000000, "v,a,b" },
157{ "exbyte", 0x0a000000, "c,a,b" },
158{ "exbyte", 0x0b000000, "c,a,i" },
159{ "exhw", 0x7c000000, "c,a,b" },
160{ "exhw", 0x7d000000, "c,a,i" },
161{ "exhws", 0x7e000000, "c,a" },
162{ "extract", 0x7a000000, "c,a,b" },
163{ "extract", 0x7b000000, "c,a,i" },
164{ "fadd", 0xf0000000, "c,a,b" },
165{ "fdiv", 0xf6000000, "c,a,b" },
166{ "fdmul", 0xf9000000, "c,a,b" },
167{ "feq", 0xea000000, "c,a,b" },
168{ "fge", 0xee000000, "c,a,b" },
169{ "fgt", 0xec000000, "c,a,b" },
170{ "fmac", 0xd8000000, "F,C,a,b" },
171{ "fmsm", 0xda000000, "c,a,b" },
172{ "fmul", 0xf4000000, "c,a,b" },
173{ "fsub", 0xf2000000, "c,a,b" },
174{ "halt", 0x89000000, "" },
175{ "inbyte", 0x0c000000, "c,a,b" },
176{ "inbyte", 0x0d000000, "c,a,i" },
177{ "inhw", 0x78000000, "c,a,b" },
178{ "inhw", 0x79000000, "c,a,i" },
179{ "inv", 0x9f000000, "I" },
180{ "iret", 0x88000000, "" },
181{ "iretinv", 0x8c000000, "I" },
182{ "jmp", 0xa0000000, "P" },
183{ "jmp", 0xa1000000, "A" },
184{ "jmpf", 0xa4000000, "a,P" },
185{ "jmpf", 0xa5000000, "a,A" },
186{ "jmpfdec", 0xb4000000, "a,P" },
187{ "jmpfdec", 0xb5000000, "a,A" },
188{ "jmpfi", 0xc4000000, "a,b" },
189{ "jmpi", 0xc0000000, "b" },
190{ "jmpt", 0xac000000, "a,P" },
191{ "jmpt", 0xad000000, "a,A" },
192{ "jmpti", 0xcc000000, "a,b" },
193{ "load", 0x16000000, "e,n,a,b" },
194{ "load", 0x17000000, "e,n,a,i" },
195{ "loadl", 0x06000000, "e,n,a,b" },
196{ "loadl", 0x07000000, "e,n,a,i" },
197{ "loadm", 0x36000000, "e,n,a,b" },
198{ "loadm", 0x37000000, "e,n,a,i" },
199{ "loadset", 0x26000000, "e,n,a,b" },
200{ "loadset", 0x27000000, "e,n,a,i" },
201{ "mfacc", 0xe9000100, "c,d,f" },
202{ "mfsr", 0xc6000000, "c,s" },
203{ "mftlb", 0xb6000000, "c,a" },
204{ "mtacc", 0xe8010000, "a,d,f" },
205{ "mtsr", 0xce000000, "s,b" },
206{ "mtsrim", 0x04000000, "s,x" },
207{ "mttlb", 0xbe000000, "a,b" },
208{ "mul", 0x64000000, "c,a,b" },
209{ "mul", 0x65000000, "c,a,i" },
210{ "mull", 0x66000000, "c,a,b" },
211{ "mull", 0x67000000, "c,a,i" },
212{ "multiplu", 0xe2000000, "c,a,b" },
213{ "multiply", 0xe0000000, "c,a,b" },
214{ "multm", 0xde000000, "c,a,b" },
215{ "multmu", 0xdf000000, "c,a,b" },
216{ "mulu", 0x74000000, "c,a,b" },
217{ "mulu", 0x75000000, "c,a,i" },
218{ "nand", 0x9a000000, "c,a,b" },
219{ "nand", 0x9b000000, "c,a,i" },
220{ "nop", 0x70400101, "" },
221{ "nor", 0x98000000, "c,a,b" },
222{ "nor", 0x99000000, "c,a,i" },
223{ "or", 0x92000000, "c,a,b" },
224{ "or", 0x93000000, "c,a,i" },
225{ "orn", 0xaa000000, "c,a,b" },
226{ "orn", 0xab000000, "c,a,i" },
227
228/* The description of "setip" in Chapter 8 ("instruction set") of the user's
229 manual claims that these are absolute register numbers. But section
230 7.2.1 explains that they are not. The latter is correct, so print
231 these normally ("lr0", "lr5", etc.). */
232{ "setip", 0x9e000000, "c,a,b" },
233
234{ "sll", 0x80000000, "c,a,b" },
235{ "sll", 0x81000000, "c,a,i" },
236{ "sqrt", 0xe5000000, "c,a,f" },
237{ "sra", 0x86000000, "c,a,b" },
238{ "sra", 0x87000000, "c,a,i" },
239{ "srl", 0x82000000, "c,a,b" },
240{ "srl", 0x83000000, "c,a,i" },
241{ "store", 0x1e000000, "e,n,a,b" },
242{ "store", 0x1f000000, "e,n,a,i" },
243{ "storel", 0x0e000000, "e,n,a,b" },
244{ "storel", 0x0f000000, "e,n,a,i" },
245{ "storem", 0x3e000000, "e,n,a,b" },
246{ "storem", 0x3f000000, "e,n,a,i" },
247{ "sub", 0x24000000, "c,a,b" },
248{ "sub", 0x25000000, "c,a,i" },
249{ "subc", 0x2c000000, "c,a,b" },
250{ "subc", 0x2d000000, "c,a,i" },
251{ "subcs", 0x28000000, "c,a,b" },
252{ "subcs", 0x29000000, "c,a,i" },
253{ "subcu", 0x2a000000, "c,a,b" },
254{ "subcu", 0x2b000000, "c,a,i" },
255{ "subr", 0x34000000, "c,a,b" },
256{ "subr", 0x35000000, "c,a,i" },
257{ "subrc", 0x3c000000, "c,a,b" },
258{ "subrc", 0x3d000000, "c,a,i" },
259{ "subrcs", 0x38000000, "c,a,b" },
260{ "subrcs", 0x39000000, "c,a,i" },
261{ "subrcu", 0x3a000000, "c,a,b" },
262{ "subrcu", 0x3b000000, "c,a,i" },
263{ "subrs", 0x30000000, "c,a,b" },
264{ "subrs", 0x31000000, "c,a,i" },
265{ "subru", 0x32000000, "c,a,b" },
266{ "subru", 0x33000000, "c,a,i" },
267{ "subs", 0x20000000, "c,a,b" },
268{ "subs", 0x21000000, "c,a,i" },
269{ "subu", 0x22000000, "c,a,b" },
270{ "subu", 0x23000000, "c,a,i" },
271{ "xnor", 0x96000000, "c,a,b" },
272{ "xnor", 0x97000000, "c,a,i" },
273{ "xor", 0x94000000, "c,a,b" },
274{ "xor", 0x95000000, "c,a,i" },
275
276{ "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES. This
277 lets code examine entry i+1 without checking
278 if we've run off the end of the table. */
279};
280
281const unsigned int num_opcodes = (((sizeof a29k_opcodes) / (sizeof a29k_opcodes[0])) - 1);
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