| 1 | /* This file defines the interface between the sh simulator and gdb.
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| 2 | Copyright (C) 2000, 2002 Free Software Foundation, Inc.
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| 3 |
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| 4 | This file is part of GDB.
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| 5 |
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| 6 | This program is free software; you can redistribute it and/or modify
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| 7 | it under the terms of the GNU General Public License as published by
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| 8 | the Free Software Foundation; either version 2 of the License, or
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| 9 | (at your option) any later version.
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| 10 |
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| 11 | This program is distributed in the hope that it will be useful,
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| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 14 | GNU General Public License for more details.
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| 15 |
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| 16 | You should have received a copy of the GNU General Public License
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| 17 | along with this program; if not, write to the Free Software
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| 18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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| 19 |
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| 20 | #if !defined (SIM_SH_H)
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| 21 | #define SIM_SH_H
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| 22 |
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| 23 | #ifdef __cplusplus
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| 24 | extern "C" { // }
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| 25 | #endif
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| 26 |
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| 27 | /* The simulator makes use of the following register information. */
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| 28 |
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| 29 | enum
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| 30 | {
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| 31 | SIM_SH_R0_REGNUM = 0,
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| 32 | SIM_SH_R1_REGNUM,
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| 33 | SIM_SH_R2_REGNUM,
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| 34 | SIM_SH_R3_REGNUM,
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| 35 | SIM_SH_R4_REGNUM,
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| 36 | SIM_SH_R5_REGNUM,
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| 37 | SIM_SH_R6_REGNUM,
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| 38 | SIM_SH_R7_REGNUM,
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| 39 | SIM_SH_R8_REGNUM,
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| 40 | SIM_SH_R9_REGNUM,
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| 41 | SIM_SH_R10_REGNUM,
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| 42 | SIM_SH_R11_REGNUM,
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| 43 | SIM_SH_R12_REGNUM,
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| 44 | SIM_SH_R13_REGNUM,
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| 45 | SIM_SH_R14_REGNUM,
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| 46 | SIM_SH_R15_REGNUM,
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| 47 | SIM_SH_PC_REGNUM,
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| 48 | SIM_SH_PR_REGNUM,
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| 49 | SIM_SH_GBR_REGNUM,
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| 50 | SIM_SH_VBR_REGNUM,
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| 51 | SIM_SH_MACH_REGNUM,
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| 52 | SIM_SH_MACL_REGNUM,
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| 53 | SIM_SH_SR_REGNUM,
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| 54 | SIM_SH_FPUL_REGNUM,
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| 55 | SIM_SH_FPSCR_REGNUM,
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| 56 | SIM_SH_FR0_REGNUM, /* FRn registers: sh3e / sh4 */
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| 57 | SIM_SH_FR1_REGNUM,
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| 58 | SIM_SH_FR2_REGNUM,
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| 59 | SIM_SH_FR3_REGNUM,
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| 60 | SIM_SH_FR4_REGNUM,
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| 61 | SIM_SH_FR5_REGNUM,
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| 62 | SIM_SH_FR6_REGNUM,
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| 63 | SIM_SH_FR7_REGNUM,
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| 64 | SIM_SH_FR8_REGNUM,
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| 65 | SIM_SH_FR9_REGNUM,
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| 66 | SIM_SH_FR10_REGNUM,
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| 67 | SIM_SH_FR11_REGNUM,
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| 68 | SIM_SH_FR12_REGNUM,
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| 69 | SIM_SH_FR13_REGNUM,
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| 70 | SIM_SH_FR14_REGNUM,
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| 71 | SIM_SH_FR15_REGNUM,
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| 72 | SIM_SH_SSR_REGNUM, /* sh3{,e,-dsp}, sh4 */
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| 73 | SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */
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| 74 | SIM_SH_R0_BANK0_REGNUM, /* SIM_SH_Rn_BANKm_REGNUM: sh3[e] / sh4 */
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| 75 | SIM_SH_R1_BANK0_REGNUM,
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| 76 | SIM_SH_R2_BANK0_REGNUM,
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| 77 | SIM_SH_R3_BANK0_REGNUM,
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| 78 | SIM_SH_R4_BANK0_REGNUM,
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| 79 | SIM_SH_R5_BANK0_REGNUM,
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| 80 | SIM_SH_R6_BANK0_REGNUM,
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| 81 | SIM_SH_R7_BANK0_REGNUM,
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| 82 | SIM_SH_R0_BANK1_REGNUM,
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| 83 | SIM_SH_R1_BANK1_REGNUM,
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| 84 | SIM_SH_R2_BANK1_REGNUM,
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| 85 | SIM_SH_R3_BANK1_REGNUM,
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| 86 | SIM_SH_R4_BANK1_REGNUM,
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| 87 | SIM_SH_R5_BANK1_REGNUM,
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| 88 | SIM_SH_R6_BANK1_REGNUM,
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| 89 | SIM_SH_R7_BANK1_REGNUM,
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| 90 | SIM_SH_XF0_REGNUM,
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| 91 | SIM_SH_XF1_REGNUM,
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| 92 | SIM_SH_XF2_REGNUM,
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| 93 | SIM_SH_XF3_REGNUM,
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| 94 | SIM_SH_XF4_REGNUM,
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| 95 | SIM_SH_XF5_REGNUM,
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| 96 | SIM_SH_XF6_REGNUM,
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| 97 | SIM_SH_XF7_REGNUM,
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| 98 | SIM_SH_XF8_REGNUM,
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| 99 | SIM_SH_XF9_REGNUM,
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| 100 | SIM_SH_XF10_REGNUM,
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| 101 | SIM_SH_XF11_REGNUM,
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| 102 | SIM_SH_XF12_REGNUM,
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| 103 | SIM_SH_XF13_REGNUM,
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| 104 | SIM_SH_XF14_REGNUM,
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| 105 | SIM_SH_XF15_REGNUM,
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| 106 | SIM_SH_SGR_REGNUM,
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| 107 | SIM_SH_DBR_REGNUM,
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| 108 | SIM_SH4_NUM_REGS, /* 77 */
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| 109 |
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| 110 | /* sh[3]-dsp */
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| 111 | SIM_SH_DSR_REGNUM,
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| 112 | SIM_SH_A0G_REGNUM,
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| 113 | SIM_SH_A0_REGNUM,
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| 114 | SIM_SH_A1G_REGNUM,
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| 115 | SIM_SH_A1_REGNUM,
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| 116 | SIM_SH_M0_REGNUM,
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| 117 | SIM_SH_M1_REGNUM,
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| 118 | SIM_SH_X0_REGNUM,
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| 119 | SIM_SH_X1_REGNUM,
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| 120 | SIM_SH_Y0_REGNUM,
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| 121 | SIM_SH_Y1_REGNUM,
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| 122 | SIM_SH_MOD_REGNUM,
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| 123 | SIM_SH_RS_REGNUM,
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| 124 | SIM_SH_RE_REGNUM,
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| 125 | SIM_SH_R0_BANK_REGNUM,
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| 126 | SIM_SH_R1_BANK_REGNUM,
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| 127 | SIM_SH_R2_BANK_REGNUM,
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| 128 | SIM_SH_R3_BANK_REGNUM,
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| 129 | SIM_SH_R4_BANK_REGNUM,
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| 130 | SIM_SH_R5_BANK_REGNUM,
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| 131 | SIM_SH_R6_BANK_REGNUM,
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| 132 | SIM_SH_R7_BANK_REGNUM
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| 133 | /* 100..127: room for expansion. */
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| 134 | };
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| 135 |
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| 136 | enum
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| 137 | {
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| 138 | SIM_SH64_R0_REGNUM = 0,
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| 139 | SIM_SH64_SP_REGNUM = 15,
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| 140 | SIM_SH64_PC_REGNUM = 64,
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| 141 | SIM_SH64_SR_REGNUM = 65,
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| 142 | SIM_SH64_SSR_REGNUM = 66,
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| 143 | SIM_SH64_SPC_REGNUM = 67,
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| 144 | SIM_SH64_TR0_REGNUM = 68,
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| 145 | SIM_SH64_FPCSR_REGNUM = 76,
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| 146 | SIM_SH64_FR0_REGNUM = 77
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| 147 | };
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| 148 |
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| 149 | enum
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| 150 | {
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| 151 | SIM_SH64_NR_REGS = 141, /* total number of architectural registers */
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| 152 | SIM_SH64_NR_R_REGS = 64, /* number of general registers */
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| 153 | SIM_SH64_NR_TR_REGS = 8, /* number of target registers */
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| 154 | SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */
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| 155 | };
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| 156 |
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| 157 | #ifdef __cplusplus
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| 158 | }
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| 159 | #endif
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| 160 |
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| 161 | #endif
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