| 1 | @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001
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| 2 | @c Free Software Foundation, Inc.
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| 3 | @c This is part of the GAS manual.
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| 4 | @c For copying conditions, see the file as.texinfo.
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| 5 | @page
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| 6 | @node SH-Dependent
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| 7 | @chapter Renesas / SuperH SH Dependent Features
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| 8 |
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| 9 | @cindex SH support
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| 10 | @menu
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| 11 | * SH Options:: Options
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| 12 | * SH Syntax:: Syntax
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| 13 | * SH Floating Point:: Floating Point
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| 14 | * SH Directives:: SH Machine Directives
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| 15 | * SH Opcodes:: Opcodes
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| 16 | @end menu
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| 17 |
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| 18 | @node SH Options
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| 19 | @section Options
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| 20 |
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| 21 | @cindex SH options
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| 22 | @cindex options, SH
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| 23 | @code{@value{AS}} has following command-line options for the Renesas
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| 24 | (formerly Hitachi) / SuperH SH family.
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| 25 |
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| 26 | @table @code
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| 27 | @kindex -little
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| 28 | @kindex -big
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| 29 | @kindex -relax
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| 30 | @kindex -small
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| 31 | @kindex -dsp
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| 32 |
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| 33 | @item -little
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| 34 | Generate little endian code.
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| 35 |
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| 36 | @item -big
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| 37 | Generate big endian code.
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| 38 |
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| 39 | @item -relax
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| 40 | Alter jump instructions for long displacements.
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| 41 |
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| 42 | @item -small
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| 43 | Align sections to 4 byte boundaries, not 16.
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| 44 |
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| 45 | @item -dsp
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| 46 | Enable sh-dsp insns, and disable sh3e / sh4 insns.
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| 47 |
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| 48 | @end table
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| 49 |
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| 50 | @node SH Syntax
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| 51 | @section Syntax
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| 52 |
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| 53 | @menu
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| 54 | * SH-Chars:: Special Characters
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| 55 | * SH-Regs:: Register Names
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| 56 | * SH-Addressing:: Addressing Modes
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| 57 | @end menu
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| 58 |
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| 59 | @node SH-Chars
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| 60 | @subsection Special Characters
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| 61 |
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| 62 | @cindex line comment character, SH
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| 63 | @cindex SH line comment character
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| 64 | @samp{!} is the line comment character.
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| 65 |
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| 66 | @cindex line separator, SH
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| 67 | @cindex statement separator, SH
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| 68 | @cindex SH line separator
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| 69 | You can use @samp{;} instead of a newline to separate statements.
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| 70 |
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| 71 | @cindex symbol names, @samp{$} in
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| 72 | @cindex @code{$} in symbol names
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| 73 | Since @samp{$} has no special meaning, you may use it in symbol names.
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| 74 |
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| 75 | @node SH-Regs
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| 76 | @subsection Register Names
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| 77 |
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| 78 | @cindex SH registers
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| 79 | @cindex registers, SH
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| 80 | You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
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| 81 | @samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
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| 82 | @samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
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| 83 | and @samp{r15} to refer to the SH registers.
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| 84 |
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| 85 | The SH also has these control registers:
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| 86 |
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| 87 | @table @code
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| 88 | @item pr
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| 89 | procedure register (holds return address)
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| 90 |
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| 91 | @item pc
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| 92 | program counter
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| 93 |
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| 94 | @item mach
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| 95 | @itemx macl
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| 96 | high and low multiply accumulator registers
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| 97 |
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| 98 | @item sr
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| 99 | status register
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| 100 |
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| 101 | @item gbr
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| 102 | global base register
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| 103 |
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| 104 | @item vbr
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| 105 | vector base register (for interrupt vectors)
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| 106 | @end table
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| 107 |
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| 108 | @node SH-Addressing
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| 109 | @subsection Addressing Modes
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| 110 |
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| 111 | @cindex addressing modes, SH
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| 112 | @cindex SH addressing modes
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| 113 | @code{@value{AS}} understands the following addressing modes for the SH.
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| 114 | @code{R@var{n}} in the following refers to any of the numbered
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| 115 | registers, but @emph{not} the control registers.
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| 116 |
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| 117 | @table @code
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| 118 | @item R@var{n}
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| 119 | Register direct
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| 120 |
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| 121 | @item @@R@var{n}
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| 122 | Register indirect
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| 123 |
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| 124 | @item @@-R@var{n}
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| 125 | Register indirect with pre-decrement
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| 126 |
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| 127 | @item @@R@var{n}+
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| 128 | Register indirect with post-increment
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| 129 |
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| 130 | @item @@(@var{disp}, R@var{n})
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| 131 | Register indirect with displacement
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| 132 |
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| 133 | @item @@(R0, R@var{n})
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| 134 | Register indexed
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| 135 |
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| 136 | @item @@(@var{disp}, GBR)
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| 137 | @code{GBR} offset
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| 138 |
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| 139 | @item @@(R0, GBR)
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| 140 | GBR indexed
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| 141 |
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| 142 | @item @var{addr}
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| 143 | @itemx @@(@var{disp}, PC)
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| 144 | PC relative address (for branch or for addressing memory). The
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| 145 | @code{@value{AS}} implementation allows you to use the simpler form
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| 146 | @var{addr} anywhere a PC relative address is called for; the alternate
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| 147 | form is supported for compatibility with other assemblers.
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| 148 |
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| 149 | @item #@var{imm}
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| 150 | Immediate data
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| 151 | @end table
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| 152 |
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| 153 | @node SH Floating Point
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| 154 | @section Floating Point
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| 155 |
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| 156 | @cindex floating point, SH (@sc{ieee})
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| 157 | @cindex SH floating point (@sc{ieee})
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| 158 | The SH family has no hardware floating point, but the @code{.float}
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| 159 | directive generates @sc{ieee} floating-point numbers for compatibility
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| 160 | with other development tools.
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| 161 |
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| 162 | @node SH Directives
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| 163 | @section SH Machine Directives
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| 164 |
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| 165 | @cindex SH machine directives
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| 166 | @cindex machine directives, SH
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| 167 | @cindex @code{uaword} directive, SH
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| 168 | @cindex @code{ualong} directive, SH
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| 169 |
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| 170 | @table @code
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| 171 | @item uaword
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| 172 | @itemx ualong
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| 173 | @code{@value{AS}} will issue a warning when a misaligned @code{.word} or
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| 174 | @code{.long} directive is used. You may use @code{.uaword} or
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| 175 | @code{.ualong} to indicate that the value is intentionally misaligned.
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| 176 | @end table
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| 177 |
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| 178 | @node SH Opcodes
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| 179 | @section Opcodes
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| 180 |
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| 181 | @cindex SH opcode summary
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| 182 | @cindex opcode summary, SH
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| 183 | @cindex mnemonics, SH
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| 184 | @cindex instruction summary, SH
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| 185 | For detailed information on the SH machine instruction set, see
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| 186 | @cite{SH-Microcomputer User's Manual} (Renesas) or
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| 187 | @cite{SH-4 32-bit CPU Core Architecture} (SuperH) and
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| 188 | @cite{SuperH (SH) 64-Bit RISC Series} (SuperH).
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| 189 |
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| 190 | @code{@value{AS}} implements all the standard SH opcodes. No additional
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| 191 | pseudo-instructions are needed on this family. Note, however, that
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| 192 | because @code{@value{AS}} supports a simpler form of PC-relative
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| 193 | addressing, you may simply write (for example)
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| 194 |
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| 195 | @example
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| 196 | mov.l bar,r0
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| 197 | @end example
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| 198 |
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| 199 | @noindent
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| 200 | where other assemblers might require an explicit displacement to
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| 201 | @code{bar} from the program counter:
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| 202 |
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| 203 | @example
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| 204 | mov.l @@(@var{disp}, PC)
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| 205 | @end example
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| 206 |
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| 207 | @ifset SMALL
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| 208 | @c this table, due to the multi-col faking and hardcoded order, looks silly
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| 209 | @c except in smallbook. See comments below "@set SMALL" near top of this file.
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| 210 |
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| 211 | Here is a summary of SH opcodes:
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| 212 |
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| 213 | @page
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| 214 | @smallexample
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| 215 | @i{Legend:}
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| 216 | Rn @r{a numbered register}
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| 217 | Rm @r{another numbered register}
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| 218 | #imm @r{immediate data}
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| 219 | disp @r{displacement}
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| 220 | disp8 @r{8-bit displacement}
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| 221 | disp12 @r{12-bit displacement}
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| 222 |
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| 223 | add #imm,Rn lds.l @@Rn+,PR
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| 224 | add Rm,Rn mac.w @@Rm+,@@Rn+
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| 225 | addc Rm,Rn mov #imm,Rn
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| 226 | addv Rm,Rn mov Rm,Rn
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| 227 | and #imm,R0 mov.b Rm,@@(R0,Rn)
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| 228 | and Rm,Rn mov.b Rm,@@-Rn
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| 229 | and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
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| 230 | bf disp8 mov.b @@(disp,Rm),R0
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| 231 | bra disp12 mov.b @@(disp,GBR),R0
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| 232 | bsr disp12 mov.b @@(R0,Rm),Rn
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| 233 | bt disp8 mov.b @@Rm+,Rn
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| 234 | clrmac mov.b @@Rm,Rn
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| 235 | clrt mov.b R0,@@(disp,Rm)
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| 236 | cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
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| 237 | cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
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| 238 | cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
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| 239 | cmp/gt Rm,Rn mov.l Rm,@@-Rn
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| 240 | cmp/hi Rm,Rn mov.l Rm,@@Rn
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| 241 | cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
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| 242 | cmp/pl Rn mov.l @@(disp,GBR),R0
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| 243 | cmp/pz Rn mov.l @@(disp,PC),Rn
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| 244 | cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
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| 245 | div0s Rm,Rn mov.l @@Rm+,Rn
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| 246 | div0u mov.l @@Rm,Rn
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| 247 | div1 Rm,Rn mov.l R0,@@(disp,GBR)
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| 248 | exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
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| 249 | exts.w Rm,Rn mov.w Rm,@@-Rn
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| 250 | extu.b Rm,Rn mov.w Rm,@@Rn
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| 251 | extu.w Rm,Rn mov.w @@(disp,Rm),R0
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| 252 | jmp @@Rn mov.w @@(disp,GBR),R0
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| 253 | jsr @@Rn mov.w @@(disp,PC),Rn
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| 254 | ldc Rn,GBR mov.w @@(R0,Rm),Rn
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| 255 | ldc Rn,SR mov.w @@Rm+,Rn
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| 256 | ldc Rn,VBR mov.w @@Rm,Rn
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| 257 | ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
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| 258 | ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
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| 259 | ldc.l @@Rn+,VBR mova @@(disp,PC),R0
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| 260 | lds Rn,MACH movt Rn
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| 261 | lds Rn,MACL muls Rm,Rn
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| 262 | lds Rn,PR mulu Rm,Rn
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| 263 | lds.l @@Rn+,MACH neg Rm,Rn
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| 264 | lds.l @@Rn+,MACL negc Rm,Rn
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| 265 | @page
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| 266 | nop stc VBR,Rn
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| 267 | not Rm,Rn stc.l GBR,@@-Rn
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| 268 | or #imm,R0 stc.l SR,@@-Rn
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| 269 | or Rm,Rn stc.l VBR,@@-Rn
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| 270 | or.b #imm,@@(R0,GBR) sts MACH,Rn
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| 271 | rotcl Rn sts MACL,Rn
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| 272 | rotcr Rn sts PR,Rn
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| 273 | rotl Rn sts.l MACH,@@-Rn
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| 274 | rotr Rn sts.l MACL,@@-Rn
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| 275 | rte sts.l PR,@@-Rn
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| 276 | rts sub Rm,Rn
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| 277 | sett subc Rm,Rn
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| 278 | shal Rn subv Rm,Rn
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| 279 | shar Rn swap.b Rm,Rn
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| 280 | shll Rn swap.w Rm,Rn
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| 281 | shll16 Rn tas.b @@Rn
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| 282 | shll2 Rn trapa #imm
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| 283 | shll8 Rn tst #imm,R0
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| 284 | shlr Rn tst Rm,Rn
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| 285 | shlr16 Rn tst.b #imm,@@(R0,GBR)
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| 286 | shlr2 Rn xor #imm,R0
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| 287 | shlr8 Rn xor Rm,Rn
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| 288 | sleep xor.b #imm,@@(R0,GBR)
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| 289 | stc GBR,Rn xtrct Rm,Rn
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| 290 | stc SR,Rn
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| 291 | @end smallexample
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| 292 | @end ifset
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| 293 |
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| 294 | @ifset Renesas-all
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| 295 | @ifclear GENERIC
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| 296 | @raisesections
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| 297 | @end ifclear
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| 298 | @end ifset
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| 299 |
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