source: trunk/binutils/gas/doc/as.info-8@ 2772

This is as.info, produced by makeinfo version 4.3 from as.texinfo.

START-INFO-DIR-ENTRY
* As: (as).                     The GNU assembler.
* Gas: (as).                    The GNU assembler.
END-INFO-DIR-ENTRY

   This file documents the GNU Assembler "as".

   Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002
Free Software Foundation, Inc.

   Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.1 or
any later version published by the Free Software Foundation; with no
Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
Texts.  A copy of the license is included in the section entitled "GNU
Free Documentation License".


File: as.info,  Node: MIPS ISA,  Next: MIPS autoextend,  Prev: MIPS Stabs,  Up: MIPS-Dependent

Directives to override the ISA level
------------------------------------

   GNU `as' supports an additional directive to change the MIPS
Instruction Set Architecture level on the fly: `.set mipsN'.  N should
be a number from 0 to 5, or 32, 32r2, or 64.  The values other than 0
make the assembler accept instructions for the corresponding ISA level,
from that point on in the assembly.  `.set mipsN' affects not only
which instructions are permitted, but also how certain macros are
expanded.  `.set mips0' restores the ISA level to its original level:
either the level you selected with command line options, or the default
for your configuration.  You can use this feature to permit specific
R4000 instructions while assembling in 32 bit mode.  Use this directive
with care!

   The directive `.set mips16' puts the assembler into MIPS 16 mode, in
which it will assemble instructions for the MIPS 16 processor.  Use
`.set nomips16' to return to normal 32 bit mode.

   Traditional MIPS assemblers do not support this directive.


File: as.info,  Node: MIPS autoextend,  Next: MIPS insn,  Prev: MIPS ISA,  Up: MIPS-Dependent

Directives for extending MIPS 16 bit instructions
-------------------------------------------------

   By default, MIPS 16 instructions are automatically extended to 32
bits when necessary.  The directive `.set noautoextend' will turn this
off.  When `.set noautoextend' is in effect, any 32 bit instruction
must be explicitly extended with the `.e' modifier (e.g., `li.e
$4,1000').  The directive `.set autoextend' may be used to once again
automatically extend instructions when necessary.

   This directive is only meaningful when in MIPS 16 mode.  Traditional
MIPS assemblers do not support this directive.


File: as.info,  Node: MIPS insn,  Next: MIPS option stack,  Prev: MIPS autoextend,  Up: MIPS-Dependent

Directive to mark data as an instruction
----------------------------------------

   The `.insn' directive tells `as' that the following data is actually
instructions.  This makes a difference in MIPS 16 mode: when loading
the address of a label which precedes instructions, `as' automatically
adds 1 to the value, so that jumping to the loaded address will do the
right thing.


File: as.info,  Node: MIPS option stack,  Next: MIPS ASE instruction generation overrides,  Prev: MIPS insn,  Up: MIPS-Dependent

Directives to save and restore options
--------------------------------------

   The directives `.set push' and `.set pop' may be used to save and
restore the current settings for all the options which are controlled
by `.set'.  The `.set push' directive saves the current settings on a
stack.  The `.set pop' directive pops the stack and restores the
settings.

   These directives can be useful inside an macro which must change an
option such as the ISA level or instruction reordering but does not want
to change the state of the code which invoked the macro.

   Traditional MIPS assemblers do not support these directives.


File: as.info,  Node: MIPS ASE instruction generation overrides,  Prev: MIPS option stack,  Up: MIPS-Dependent

Directives to control generation of MIPS ASE instructions
---------------------------------------------------------

   The directive `.set mips3d' makes the assembler accept instructions
from the MIPS-3D Application Specific Extension from that point on in
the assembly.  The `.set nomips3d' directive prevents MIPS-3D
instructions from being accepted.

   The directive `.set mdmx' makes the assembler accept instructions
from the MDMX Application Specific Extension from that point on in the
assembly.  The `.set nomdmx' directive prevents MDMX instructions from
being accepted.

   Traditional MIPS assemblers do not support these directives.


File: as.info,  Node: MMIX-Dependent,  Next: MSP430-Dependent,  Prev: MIPS-Dependent,  Up: Machine Dependencies

MMIX Dependent Features
=======================

* Menu:

* MMIX-Opts::              Command-line Options
* MMIX-Expand::            Instruction expansion
* MMIX-Syntax::            Syntax
* MMIX-mmixal::            Differences to `mmixal' syntax and semantics


File: as.info,  Node: MMIX-Opts,  Next: MMIX-Expand,  Up: MMIX-Dependent

Command-line Options
--------------------

   The MMIX version of `as' has some machine-dependent options.

   When `--fixed-special-register-names' is specified, only the register
names specified in *Note MMIX-Regs:: are recognized in the instructions
`PUT' and `GET'.

   You can use the `--globalize-symbols' to make all symbols global.
This option is useful when splitting up a `mmixal' program into several
files.

   The `--gnu-syntax' turns off most syntax compatibility with
`mmixal'.  Its usability is currently doubtful.

   The `--relax' option is not fully supported, but will eventually make
the object file prepared for linker relaxation.

   If you want to avoid inadvertently calling a predefined symbol and
would rather get an error, for example when using `as' with a compiler
or other machine-generated code, specify `--no-predefined-syms'.  This
turns off built-in predefined definitions of all such symbols,
including rounding-mode symbols, segment symbols, `BIT' symbols, and
`TRAP' symbols used in `mmix' "system calls".  It also turns off
predefined special-register names, except when used in `PUT' and `GET'
instructions.

   By default, some instructions are expanded to fit the size of the
operand or an external symbol (*note MMIX-Expand::).  By passing
`--no-expand', no such expansion will be done, instead causing errors
at link time if the operand does not fit.

   The `mmixal' documentation (*note mmixsite::) specifies that global
registers allocated with the `GREG' directive (*note MMIX-greg::) and
initialized to the same non-zero value, will refer to the same global
register.  This isn't strictly enforceable in `as' since the final
addresses aren't known until link-time, but it will do an effort unless
the `--no-merge-gregs' option is specified.  (Register merging isn't
yet implemented in `ld'.)

   `as' will warn every time it expands an instruction to fit an
operand unless the option `-x' is specified.  It is believed that this
behaviour is more useful than just mimicking `mmixal''s behaviour, in
which instructions are only expanded if the `-x' option is specified,
and assembly fails otherwise, when an instruction needs to be expanded.
It needs to be kept in mind that `mmixal' is both an assembler and
linker, while `as' will expand instructions that at link stage can be
contracted.  (Though linker relaxation isn't yet implemented in `ld'.)
The option `-x' also imples `--linker-allocated-gregs'.

   Usually a two-operand-expression (*note GREG-base::) without a
matching `GREG' directive is treated as an error by `as'.  When the
option `--linker-allocated-gregs' is in effect, they are instead passed
through to the linker, which will allocate as many global registers as
is needed.


File: as.info,  Node: MMIX-Expand,  Next: MMIX-Syntax,  Prev: MMIX-Opts,  Up: MMIX-Dependent

Instruction expansion
---------------------

   When `as' encounters an instruction with an operand that is either
not known or does not fit the operand size of the instruction, `as'
(and `ld') will expand the instruction into a sequence of instructions
semantically equivalent to the operand fitting the instruction.
Expansion will take place for the following instructions:

`GETA'
     Expands to a sequence of four instructions: `SETL', `INCML',
     `INCMH' and `INCH'.  The operand must be a multiple of four.

Conditional branches
     A branch instruction is turned into a branch with the complemented
     condition and prediction bit over five instructions; four
     instructions setting `$255' to the operand value, which like with
     `GETA' must be a multiple of four, and a final `GO $255,$255,0'.

`PUSHJ'
     Similar to expansion for conditional branches; four instructions
     set `$255' to the operand value, followed by a `PUSHGO
     $255,$255,0'.

`JMP'
     Similar to conditional branches and `PUSHJ'.  The final instruction
     is `GO $255,$255,0'.

   The linker `ld' is expected to shrink these expansions for code
assembled with `--relax' (though not currently implemented).


File: as.info,  Node: MMIX-Syntax,  Next: MMIX-mmixal,  Prev: MMIX-Expand,  Up: MMIX-Dependent

Syntax
------

   The assembly syntax is supposed to be upward compatible with that
described in Sections 1.3 and 1.4 of `The Art of Computer Programming,
Volume 1'.  Draft versions of those chapters as well as other MMIX
information is located at
<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>.  Most code
examples from the mmixal package located there should work unmodified
when assembled and linked as single files, with a few noteworthy
exceptions (*note MMIX-mmixal::).

   Before an instruction is emitted, the current location is aligned to
the next four-byte boundary.  If a label is defined at the beginning of
the line, its value will be the aligned value.

   In addition to the traditional hex-prefix `0x', a hexadecimal number
can also be specified by the prefix character `#'.

   After all operands to an MMIX instruction or directive have been
specified, the rest of the line is ignored, treated as a comment.

* Menu:

* MMIX-Chars::                  Special Characters
* MMIX-Symbols::                Symbols
* MMIX-Regs::                   Register Names
* MMIX-Pseudos::                Assembler Directives


File: as.info,  Node: MMIX-Chars,  Next: MMIX-Symbols,  Up: MMIX-Syntax

Special Characters
..................

   The characters `*' and `#' are line comment characters; each start a
comment at the beginning of a line, but only at the beginning of a
line.  A `#' prefixes a hexadecimal number if found elsewhere on a line.

   Two other characters, `%' and `!', each start a comment anywhere on
the line.  Thus you can't use the `modulus' and `not' operators in
expressions normally associated with these two characters.

   A `;' is a line separator, treated as a new-line, so separate
instructions can be specified on a single line.


File: as.info,  Node: MMIX-Symbols,  Next: MMIX-Regs,  Prev: MMIX-Chars,  Up: MMIX-Syntax

Symbols
.......

   The character `:' is permitted in identifiers.  There are two
exceptions to it being treated as any other symbol character: if a
symbol begins with `:', it means that the symbol is in the global
namespace and that the current prefix should not be prepended to that
symbol (*note MMIX-prefix::).  The `:' is then not considered part of
the symbol.  For a symbol in the label position (first on a line), a `:'
at the end of a symbol is silently stripped off.  A label is permitted,
but not required, to be followed by a `:', as with many other assembly
formats.

   The character `@' in an expression, is a synonym for `.', the
current location.

   In addition to the common forward and backward local symbol formats
(*note Symbol Names::), they can be specified with upper-case `B' and
`F', as in `8B' and `9F'.  A local label defined for the current
position is written with a `H' appended to the number:
     3H LDB $0,$1,2
   This and traditional local-label formats cannot be mixed: a label
must be defined and referred to using the same format.

   There's a minor caveat: just as for the ordinary local symbols, the
local symbols are translated into ordinary symbols using control
characters are to hide the ordinal number of the symbol.
Unfortunately, these symbols are not translated back in error messages.
Thus you may see confusing error messages when local symbols are used.
Control characters `\003' (control-C) and `\004' (control-D) are used
for the MMIX-specific local-symbol syntax.

   The symbol `Main' is handled specially; it is always global.

   By defining the symbols `__.MMIX.start..text' and
`__.MMIX.start..data', the address of respectively the `.text' and
`.data' segments of the final program can be defined, though when
linking more than one object file, the code or data in the object file
containing the symbol is not guaranteed to be start at that position;
just the final executable.  *Note MMIX-loc::.


File: as.info,  Node: MMIX-Regs,  Next: MMIX-Pseudos,  Prev: MMIX-Symbols,  Up: MMIX-Syntax

Register names
..............

   Local and global registers are specified as `$0' to `$255'.  The
recognized special register names are `rJ', `rA', `rB', `rC', `rD',
`rE', `rF', `rG', `rH', `rI', `rK', `rL', `rM', `rN', `rO', `rP', `rQ',
`rR', `rS', `rT', `rU', `rV', `rW', `rX', `rY', `rZ', `rBB', `rTT',
`rWW', `rXX', `rYY' and `rZZ'.  A leading `:' is optional for special
register names.

   Local and global symbols can be equated to register names and used in
place of ordinary registers.

   Similarly for special registers, local and global symbols can be
used.  Also, symbols equated from numbers and constant expressions are
allowed in place of a special register, except when either of the
options `--no-predefined-syms' and `--fixed-special-register-names' are
specified.  Then only the special register names above are allowed for
the instructions having a special register operand; `GET' and `PUT'.


File: as.info,  Node: MMIX-Pseudos,  Prev: MMIX-Regs,  Up: MMIX-Syntax

Assembler Directives
....................

`LOC'
     The `LOC' directive sets the current location to the value of the
     operand field, which may include changing sections.  If the
     operand is a constant, the section is set to either `.data' if the
     value is `0x2000000000000000' or larger, else it is set to `.text'.
     Within a section, the current location may only be changed to
     monotonically higher addresses.  A LOC expression must be a
     previously defined symbol or a "pure" constant.

     An example, which sets the label PREV to the current location, and
     updates the current location to eight bytes forward:
          prev LOC @+8

     When a LOC has a constant as its operand, a symbol
     `__.MMIX.start..text' or `__.MMIX.start..data' is defined
     depending on the address as mentioned above.  Each such symbol is
     interpreted as special by the linker, locating the section at that
     address.  Note that if multiple files are linked, the first object
     file with that section will be mapped to that address (not
     necessarily the file with the LOC definition).

`LOCAL'
     Example:
           LOCAL external_symbol
           LOCAL 42
           .local asymbol

     This directive-operation generates a link-time assertion that the
     operand does not correspond to a global register.  The operand is
     an expression that at link-time resolves to a register symbol or a
     number.  A number is treated as the register having that number.
     There is one restriction on the use of this directive: the
     pseudo-directive must be placed in a section with contents, code
     or data.

`IS'
     The `IS' directive:
          asymbol IS an_expression
     sets the symbol `asymbol' to `an_expression'.  A symbol may not be
     set more than once using this directive.  Local labels may be set
     using this directive, for example:
          5H IS @+4

`GREG'
     This directive reserves a global register, gives it an initial
     value and optionally gives it a symbolic name.  Some examples:

          areg GREG
          breg GREG data_value
               GREG data_buffer
               .greg creg, another_data_value

     The symbolic register name can be used in place of a (non-special)
     register.  If a value isn't provided, it defaults to zero.  Unless
     the option `--no-merge-gregs' is specified, non-zero registers
     allocated with this directive may be eliminated by `as'; another
     register with the same value used in its place.  Any of the
     instructions `CSWAP', `GO', `LDA', `LDBU', `LDB', `LDHT', `LDOU',
     `LDO', `LDSF', `LDTU', `LDT', `LDUNC', `LDVTS', `LDWU', `LDW',
     `PREGO', `PRELD', `PREST', `PUSHGO', `STBU', `STB', `STCO', `STHT',
     `STOU', `STSF', `STTU', `STT', `STUNC', `SYNCD', `SYNCID', can
     have a value nearby an initial value in place of its second and
     third operands.  Here, "nearby" is defined as within the range
     0...255 from the initial value of such an allocated register.

          buffer1 BYTE 0,0,0,0,0
          buffer2 BYTE 0,0,0,0,0
           ...
           GREG buffer1
           LDOU $42,buffer2
     In the example above, the `Y' field of the `LDOUI' instruction
     (LDOU with a constant Z) will be replaced with the global register
     allocated for `buffer1', and the `Z' field will have the value 5,
     the offset from `buffer1' to `buffer2'.  The result is equivalent
     to this code:
          buffer1 BYTE 0,0,0,0,0
          buffer2 BYTE 0,0,0,0,0
           ...
          tmpreg GREG buffer1
           LDOU $42,tmpreg,(buffer2-buffer1)

     Global registers allocated with this directive are allocated in
     order higher-to-lower within a file.  Other than that, the exact
     order of register allocation and elimination is undefined.  For
     example, the order is undefined when more than one file with such
     directives are linked together.  With the options `-x' and
     `--linker-allocated-gregs', `GREG' directives for two-operand
     cases like the one mentioned above can be omitted.  Sufficient
     global registers will then be allocated by the linker.

`BYTE'
     The `BYTE' directive takes a series of operands separated by a
     comma.  If an operand is a string (*note Strings::), each
     character of that string is emitted as a byte.  Other operands
     must be constant expressions without forward references, in the
     range 0...255.  If you need operands having expressions with
     forward references, use `.byte' (*note Byte::).  An operand can be
     omitted, defaulting to a zero value.

`WYDE'
`TETRA'
`OCTA'
     The directives `WYDE', `TETRA' and `OCTA' emit constants of two,
     four and eight bytes size respectively.  Before anything else
     happens for the directive, the current location is aligned to the
     respective constant-size bondary.  If a label is defined at the
     beginning of the line, its value will be that after the alignment.
     A single operand can be omitted, defaulting to a zero value
     emitted for the directive.  Operands can be expressed as strings
     (*note Strings::), in which case each character in the string is
     emitted as a separate constant of the size indicated by the
     directive.

`PREFIX'
     The `PREFIX' directive sets a symbol name prefix to be prepended to
     all symbols (except local symbols, *note MMIX-Symbols::), that are
     not prefixed with `:', until the next `PREFIX' directive.  Such
     prefixes accumulate.  For example,
           PREFIX a
           PREFIX b
          c IS 0
     defines a symbol `abc' with the value 0.

`BSPEC'
`ESPEC'
     A pair of `BSPEC' and `ESPEC' directives delimit a section of
     special contents (without specified semantics).  Example:
           BSPEC 42
           TETRA 1,2,3
           ESPEC
     The single operand to `BSPEC' must be number in the range 0...255.
     The `BSPEC' number 80 is used by the GNU binutils implementation.


File: as.info,  Node: MMIX-mmixal,  Prev: MMIX-Syntax,  Up: MMIX-Dependent

Differences to `mmixal'
-----------------------

   The binutils `as' and `ld' combination has a few differences in
function compared to `mmixal' (*note mmixsite::).

   The replacement of a symbol with a GREG-allocated register (*note
GREG-base::) is not handled the exactly same way in `as' as in
`mmixal'.  This is apparent in the `mmixal' example file `inout.mms',
where different registers with different offsets, eventually yielding
the same address, are used in the first instruction.  This type of
difference should however not affect the function of any program unless
it has specific assumptions about the allocated register number.

   Line numbers (in the `mmo' object format) are currently not
supported.

   Expression operator precedence is not that of mmixal: operator
precedence is that of the C programming language.  It's recommended to
use parentheses to explicitly specify wanted operator precedence
whenever more than one type of operators are used.

   The serialize unary operator `&', the fractional division operator
`//', the logical not operator `!' and the modulus operator `%' are not
available.

   Symbols are not global by default, unless the option
`--globalize-symbols' is passed.  Use the `.global' directive to
globalize symbols (*note Global::).

   Operand syntax is a bit stricter with `as' than `mmixal'.  For
example, you can't say `addu 1,2,3', instead you must write `addu
$1,$2,3'.

   You can't LOC to a lower address than those already visited (i.e.
"backwards").

   A LOC directive must come before any emitted code.

   Predefined symbols are visible as file-local symbols after use.  (In
the ELF file, that is--the linked mmo file has no notion of a file-local
symbol.)

   Some mapping of constant expressions to sections in LOC expressions
is attempted, but that functionality is easily confused and should be
avoided unless compatibility with `mmixal' is required.  A LOC
expression to `0x2000000000000000' or higher, maps to the `.data'
section and lower addresses map to the `.text' section (*note
MMIX-loc::).

   The code and data areas are each contiguous.  Sparse programs with
far-away LOC directives will take up the same amount of space as a
contiguous program with zeros filled in the gaps between the LOC
directives.  If you need sparse programs, you might try and get the
wanted effect with a linker script and splitting up the code parts into
sections (*note Section::).  Assembly code for this, to be compatible
with `mmixal', would look something like:
      .if 0
      LOC away_expression
      .else
      .section away,"ax"
      .fi
   `as' will not execute the LOC directive and `mmixal' ignores the
lines with `.'.  This construct can be used generally to help
compatibility.

   Symbols can't be defined twice-not even to the same value.

   Instruction mnemonics are recognized case-insensitive, though the
`IS' and `GREG' pseudo-operations must be specified in upper-case
characters.

   There's no unicode support.

   The following is a list of programs in `mmix.tar.gz', available at
<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>, last
checked with the version dated 2001-08-25 (md5sum
c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal' but do
not assemble with `as':

`silly.mms'
     LOC to a previous address.

`sim.mms'
     Redefines symbol `Done'.

`test.mms'
     Uses the serial operator `&'.


File: as.info,  Node: MSP430-Dependent,  Next: SH-Dependent,  Prev: MMIX-Dependent,  Up: Machine Dependencies

MSP 430 Dependent Features
==========================

* Menu:

* MSP430 Options::              Options
* MSP430 Syntax::               Syntax
* MSP430 Floating Point::       Floating Point
* MSP430 Directives::           MSP 430 Machine Directives
* MSP430 Opcodes::              Opcodes


File: as.info,  Node: MSP430 Options,  Next: MSP430 Syntax,  Up: MSP430-Dependent

Options
-------

   `as' has only -m flag which selects the mpu arch. Currently has no
effect.


File: as.info,  Node: MSP430 Syntax,  Next: MSP430 Floating Point,  Prev: MSP430 Options,  Up: MSP430-Dependent

Syntax
------

* Menu:

* MSP430-Macros::               Macros
* MSP430-Chars::                Special Characters
* MSP430-Regs::                 Register Names
* MSP430-Ext::                  Assembler Extensions


File: as.info,  Node: MSP430-Macros,  Next: MSP430-Chars,  Up: MSP430 Syntax

Macros
......

   The macro syntax used on the MSP 430 is like that described in the
MSP 430 Family Assembler Specification.  Normal `as' macros should
still work.

   Additional built-in macros are:

`llo(exp)'
     Extracts least significant word from 32-bit expression 'exp'.

`lhi(exp)'
     Extracts most significant word from 32-bit expression 'exp'.

`hlo(exp)'
     Extracts 3rd word from 64-bit expression 'exp'.

`hhi(exp)'
     Extracts 4rd word from 64-bit expression 'exp'.

   They normally being used as an immediate source operand.
         mov    #llo(1), r10    ;       == mov  #1, r10
         mov    #lhi(1), r10    ;       == mov  #0, r10


File: as.info,  Node: MSP430-Chars,  Next: MSP430-Regs,  Prev: MSP430-Macros,  Up: MSP430 Syntax

Special Characters
..................

   `;' is the line comment character.

   The character `$' in jump instructions indicates current location and
implemented only for TI syntax compatibility.


File: as.info,  Node: MSP430-Regs,  Next: MSP430-Ext,  Prev: MSP430-Chars,  Up: MSP430 Syntax

Register Names
..............

   General-purpose registers are represented by predefined symbols of
the form `rN' (for global registers), where N represents a number
between `0' and `15'.  The leading letters may be in either upper or
lower case; for example, `r13' and `R7' are both valid register names.

   Register names `PC', `SP' and `SR' cannot be used as register names
and will be treated as variables. Use `r0', `r1', and `r2' instead.


File: as.info,  Node: MSP430-Ext,  Prev: MSP430-Regs,  Up: MSP430 Syntax

Assembler Extensions
....................

`@rN'
     As destination operand being treated as `0(rn)'

`0(rN)'
     As source operand being treated as `@rn'

`jCOND +N'
     Skips next N bytes followed by jump instruction and equivalent to
     `jCOND $+N+2'


File: as.info,  Node: MSP430 Floating Point,  Next: MSP430 Directives,  Prev: MSP430 Syntax,  Up: MSP430-Dependent

Floating Point
--------------

   The MSP 430 family uses IEEE 32-bit floating-point numbers.


File: as.info,  Node: MSP430 Directives,  Next: MSP430 Opcodes,  Prev: MSP430 Floating Point,  Up: MSP430-Dependent

MSP 430 Machine Directives
--------------------------

`.file'
     This directive is ignored; it is accepted for compatibility with
     other MSP 430 assemblers.

          _Warning:_ in other versions of the GNU assembler, `.file' is
          used for the directive called `.app-file' in the MSP 430
          support.

`.line'
     This directive is ignored; it is accepted for compatibility with
     other MSP 430 assemblers.

`.arch'
     Currently this directive is ignored; it is accepted for
     compatibility with other MSP 430 assemblers.


File: as.info,  Node: MSP430 Opcodes,  Prev: MSP430 Directives,  Up: MSP430-Dependent

Opcodes
-------

   `as' implements all the standard MSP 430 opcodes.  No additional
pseudo-instructions are needed on this family.

   For information on the 430 machine instruction set, see `MSP430
User's Manual, document slau049b', Texas Instrument, Inc.


File: as.info,  Node: PDP-11-Dependent,  Next: PJ-Dependent,  Prev: SH64-Dependent,  Up: Machine Dependencies

PDP-11 Dependent Features
=========================

* Menu:

* PDP-11-Options::              Options
* PDP-11-Pseudos::              Assembler Directives
* PDP-11-Syntax::               DEC Syntax versus BSD Syntax
* PDP-11-Mnemonics::            Instruction Naming
* PDP-11-Synthetic::            Synthetic Instructions


File: as.info,  Node: PDP-11-Options,  Next: PDP-11-Pseudos,  Up: PDP-11-Dependent

Options
-------

   The PDP-11 version of `as' has a rich set of machine dependent
options.

Code Generation Options
.......................

`-mpic | -mno-pic'
     Generate position-independent (or position-dependent) code.

     The default is to generate position-independent code.

Instruction Set Extension Options
.................................

   These options enables or disables the use of extensions over the base
line instruction set as introduced by the first PDP-11 CPU: the KA11.
Most options come in two variants: a `-m'EXTENSION that enables
EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION.

   The default is to enable all extensions.

`-mall | -mall-extensions'
     Enable all instruction set extensions.

`-mno-extensions'
     Disable all instruction set extensions.

`-mcis | -mno-cis'
     Enable (or disable) the use of the commercial instruction set,
     which consists of these instructions: `ADDNI', `ADDN', `ADDPI',
     `ADDP', `ASHNI', `ASHN', `ASHPI', `ASHP', `CMPCI', `CMPC',
     `CMPNI', `CMPN', `CMPPI', `CMPP', `CVTLNI', `CVTLN', `CVTLPI',
     `CVTLP', `CVTNLI', `CVTNL', `CVTNPI', `CVTNP', `CVTPLI', `CVTPL',
     `CVTPNI', `CVTPN', `DIVPI', `DIVP', `L2DR', `L3DR', `LOCCI',
     `LOCC', `MATCI', `MATC', `MOVCI', `MOVC', `MOVRCI', `MOVRC',
     `MOVTCI', `MOVTC', `MULPI', `MULP', `SCANCI', `SCANC', `SKPCI',
     `SKPC', `SPANCI', `SPANC', `SUBNI', `SUBN', `SUBPI', and `SUBP'.

`-mcsm | -mno-csm'
     Enable (or disable) the use of the `CSM' instruction.

`-meis | -mno-eis'
     Enable (or disable) the use of the extended instruction set, which
     consists of these instructions: `ASHC', `ASH', `DIV', `MARK',
     `MUL', `RTT', `SOB' `SXT', and `XOR'.

`-mfis | -mkev11'
`-mno-fis | -mno-kev11'
     Enable (or disable) the use of the KEV11 floating-point
     instructions: `FADD', `FDIV', `FMUL', and `FSUB'.

`-mfpp | -mfpu | -mfp-11'
`-mno-fpp | -mno-fpu | -mno-fp-11'
     Enable (or disable) the use of FP-11 floating-point instructions:
     `ABSF', `ADDF', `CFCC', `CLRF', `CMPF', `DIVF', `LDCFF', `LDCIF',
     `LDEXP', `LDF', `LDFPS', `MODF', `MULF', `NEGF', `SETD', `SETF',
     `SETI', `SETL', `STCFF', `STCFI', `STEXP', `STF', `STFPS', `STST',
     `SUBF', and `TSTF'.

`-mlimited-eis | -mno-limited-eis'
     Enable (or disable) the use of the limited extended instruction
     set: `MARK', `RTT', `SOB', `SXT', and `XOR'.

     The -mno-limited-eis options also implies -mno-eis.

`-mmfpt | -mno-mfpt'
     Enable (or disable) the use of the `MFPT' instruction.

`-mmultiproc | -mno-multiproc'
     Enable (or disable) the use of multiprocessor instructions:
     `TSTSET' and `WRTLCK'.

`-mmxps | -mno-mxps'
     Enable (or disable) the use of the `MFPS' and `MTPS' instructions.

`-mspl | -mno-spl'
     Enable (or disable) the use of the `SPL' instruction.

     Enable (or disable) the use of the microcode instructions: `LDUB',
     `MED', and `XFC'.

CPU Model Options
.................

   These options enable the instruction set extensions supported by a
particular CPU, and disables all other extensions.

`-mka11'
     KA11 CPU.  Base line instruction set only.

`-mkb11'
     KB11 CPU.  Enable extended instruction set and `SPL'.

`-mkd11a'
     KD11-A CPU.  Enable limited extended instruction set.

`-mkd11b'
     KD11-B CPU.  Base line instruction set only.

`-mkd11d'
     KD11-D CPU.  Base line instruction set only.

`-mkd11e'
     KD11-E CPU.  Enable extended instruction set, `MFPS', and `MTPS'.

`-mkd11f | -mkd11h | -mkd11q'
     KD11-F, KD11-H, or KD11-Q CPU.  Enable limited extended
     instruction set, `MFPS', and `MTPS'.

`-mkd11k'
     KD11-K CPU.  Enable extended instruction set, `LDUB', `MED',
     `MFPS', `MFPT', `MTPS', and `XFC'.

`-mkd11z'
     KD11-Z CPU.  Enable extended instruction set, `CSM', `MFPS',
     `MFPT', `MTPS', and `SPL'.

`-mf11'
     F11 CPU.  Enable extended instruction set, `MFPS', `MFPT', and
     `MTPS'.

`-mj11'
     J11 CPU.  Enable extended instruction set, `CSM', `MFPS', `MFPT',
     `MTPS', `SPL', `TSTSET', and `WRTLCK'.

`-mt11'
     T11 CPU.  Enable limited extended instruction set, `MFPS', and
     `MTPS'.

Machine Model Options
.....................

   These options enable the instruction set extensions supported by a
particular machine model, and disables all other extensions.

`-m11/03'
     Same as `-mkd11f'.

`-m11/04'
     Same as `-mkd11d'.

`-m11/05 | -m11/10'
     Same as `-mkd11b'.

`-m11/15 | -m11/20'
     Same as `-mka11'.

`-m11/21'
     Same as `-mt11'.

`-m11/23 | -m11/24'
     Same as `-mf11'.

`-m11/34'
     Same as `-mkd11e'.

`-m11/34a'
     Ame as `-mkd11e' `-mfpp'.

`-m11/35 | -m11/40'
     Same as `-mkd11a'.

`-m11/44'
     Same as `-mkd11z'.

`-m11/45 | -m11/50 | -m11/55 | -m11/70'
     Same as `-mkb11'.

`-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94'
     Same as `-mj11'.

`-m11/60'
     Same as `-mkd11k'.


File: as.info,  Node: PDP-11-Pseudos,  Next: PDP-11-Syntax,  Prev: PDP-11-Options,  Up: PDP-11-Dependent

Assembler Directives
--------------------

   The PDP-11 version of `as' has a few machine dependent assembler
directives.

`.bss'
     Switch to the `bss' section.

`.even'
     Align the location counter to an even number.


File: as.info,  Node: PDP-11-Syntax,  Next: PDP-11-Mnemonics,  Prev: PDP-11-Pseudos,  Up: PDP-11-Dependent

PDP-11 Assembly Language Syntax
-------------------------------

   `as' supports both DEC syntax and BSD syntax.  The only difference
is that in DEC syntax, a `#' character is used to denote an immediate
constants, while in BSD syntax the character for this purpose is `$'.

   eneral-purpose registers are named `r0' through `r7'.  Mnemonic
alternatives for `r6' and `r7' are `sp' and `pc', respectively.

   Floating-point registers are named `ac0' through `ac3', or
alternatively `fr0' through `fr3'.

   Comments are started with a `#' or a `/' character, and extend to
the end of the line.  (FIXME: clash with immediates?)


File: as.info,  Node: PDP-11-Mnemonics,  Next: PDP-11-Synthetic,  Prev: PDP-11-Syntax,  Up: PDP-11-Dependent

Instruction Naming
------------------

   Some instructions have alternative names.

`BCC'
     `BHIS'

`BCS'
     `BLO'

`L2DR'
     `L2D'

`L3DR'
     `L3D'

`SYS'
     `TRAP'


File: as.info,  Node: PDP-11-Synthetic,  Prev: PDP-11-Mnemonics,  Up: PDP-11-Dependent

Synthetic Instructions
----------------------

   The `JBR' and `J'CC synthetic instructions are not supported yet.


File: as.info,  Node: PJ-Dependent,  Next: PPC-Dependent,  Prev: PDP-11-Dependent,  Up: Machine Dependencies

picoJava Dependent Features
===========================

* Menu:

* PJ Options::              Options


File: as.info,  Node: PJ Options,  Up: PJ-Dependent

Options
-------

   `as' has two additional command-line options for the picoJava
architecture.
`-ml'
     This option selects little endian data output.

`-mb'
     This option selects big endian data output.


File: as.info,  Node: PPC-Dependent,  Next: Sparc-Dependent,  Prev: PJ-Dependent,  Up: Machine Dependencies

PowerPC Dependent Features
==========================

* Menu:

* PowerPC-Opts::                Options


File: as.info,  Node: PowerPC-Opts,  Up: PPC-Dependent

Options
-------

   The PowerPC chip family includes several successive levels, using
the same core instruction set, but including a few additional
instructions at each level.  There are exceptions to this however.  For
details on what instructions each variant supports, please see the
chip's architecture reference manual.

   The following table lists all available PowerPC options.

`-mpwrx | -mpwr2'
     Generate code for POWER/2 (RIOS2).

`-mpwr'
     Generate code for POWER (RIOS1)

`-m601'
     Generate code for PowerPC 601.

`-mppc, -mppc32, -m603, -m604'
     Generate code for PowerPC 603/604.

`-m403, -m405'
     Generate code for PowerPC 403/405.

`-m7400, -m7410, -m7450, -m7455'
     Generate code for PowerPC 7400/7410/7450/7455.

`-mppc64, -m620'
     Generate code for PowerPC 620/625/630.

`-mppc64bridge'
     Generate code for PowerPC 64, including bridge insns.

`-mbooke64'
     Generate code for 64-bit BookE.

`-mbooke, mbooke32'
     Generate code for 32-bit BookE.

`-maltivec'
     Generate code for processors with AltiVec instructions.

`-mpower4'
     Generate code for Power4 architecture.

`-mcom'
     Generate code Power/PowerPC common instructions.

`-many'
     Generate code for any architecture (PWR/PWRX/PPC).

`-mregnames'
     Allow symbolic names for registers.

`-mno-regnames'
     Do not allow symbolic names for registers.

`-mrelocatable'
     Support for GCC's -mrelocatble option.

`-mrelocatable-lib'
     Support for GCC's -mrelocatble-lib option.

`-memb'
     Set PPC_EMB bit in ELF flags.

`-mlittle, -mlittle-endian'
     Generate code for a little endian machine.

`-mbig, -mbig-endian'
     Generate code for a big endian machine.

`-msolaris'
     Generate code for Solaris.

`-mno-solaris'
     Do not generate code for Solaris.


File: as.info,  Node: SH-Dependent,  Next: SH64-Dependent,  Prev: MSP430-Dependent,  Up: Machine Dependencies

Renesas / SuperH SH Dependent Features
======================================

* Menu:

* SH Options::              Options
* SH Syntax::               Syntax
* SH Floating Point::       Floating Point
* SH Directives::           SH Machine Directives
* SH Opcodes::              Opcodes


File: as.info,  Node: SH Options,  Next: SH Syntax,  Up: SH-Dependent

Options
-------

   `as' has following command-line options for the Renesas (formerly
Hitachi) / SuperH SH family.

`-little'
     Generate little endian code.

`-big'
     Generate big endian code.

`-relax'
     Alter jump instructions for long displacements.

`-small'
     Align sections to 4 byte boundaries, not 16.

`-dsp'
     Enable sh-dsp insns, and disable sh3e / sh4 insns.


File: as.info,  Node: SH Syntax,  Next: SH Floating Point,  Prev: SH Options,  Up: SH-Dependent

Syntax
------

* Menu:

* SH-Chars::                Special Characters
* SH-Regs::                 Register Names
* SH-Addressing::           Addressing Modes


File: as.info,  Node: SH-Chars,  Next: SH-Regs,  Up: SH Syntax

Special Characters
..................

   `!' is the line comment character.

   You can use `;' instead of a newline to separate statements.

   Since `$' has no special meaning, you may use it in symbol names.


File: as.info,  Node: SH-Regs,  Next: SH-Addressing,  Prev: SH-Chars,  Up: SH Syntax

Register Names
..............

   You can use the predefined symbols `r0', `r1', `r2', `r3', `r4',
`r5', `r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and
`r15' to refer to the SH registers.

   The SH also has these control registers:

`pr'
     procedure register (holds return address)

`pc'
     program counter

`mach'
`macl'
     high and low multiply accumulator registers

`sr'
     status register

`gbr'
     global base register

`vbr'
     vector base register (for interrupt vectors)


File: as.info,  Node: SH-Addressing,  Prev: SH-Regs,  Up: SH Syntax

Addressing Modes
................

   `as' understands the following addressing modes for the SH.  `RN' in
the following refers to any of the numbered registers, but _not_ the
control registers.

`RN'
     Register direct

`@RN'
     Register indirect

`@-RN'
     Register indirect with pre-decrement

`@RN+'
     Register indirect with post-increment

`@(DISP, RN)'
     Register indirect with displacement

`@(R0, RN)'
     Register indexed

`@(DISP, GBR)'
     `GBR' offset

`@(R0, GBR)'
     GBR indexed

`ADDR'
`@(DISP, PC)'
     PC relative address (for branch or for addressing memory).  The
     `as' implementation allows you to use the simpler form ADDR
     anywhere a PC relative address is called for; the alternate form
     is supported for compatibility with other assemblers.

`#IMM'
     Immediate data


File: as.info,  Node: SH Floating Point,  Next: SH Directives,  Prev: SH Syntax,  Up: SH-Dependent

Floating Point
--------------

   The SH family has no hardware floating point, but the `.float'
directive generates IEEE floating-point numbers for compatibility with
other development tools.


File: as.info,  Node: SH Directives,  Next: SH Opcodes,  Prev: SH Floating Point,  Up: SH-Dependent

SH Machine Directives
---------------------

`uaword'
`ualong'
     `as' will issue a warning when a misaligned `.word' or `.long'
     directive is used.  You may use `.uaword' or `.ualong' to indicate
     that the value is intentionally misaligned.


File: as.info,  Node: SH Opcodes,  Prev: SH Directives,  Up: SH-Dependent

Opcodes
-------

   For detailed information on the SH machine instruction set, see
`SH-Microcomputer User's Manual' (Renesas) or `SH-4 32-bit CPU Core
Architecture' (SuperH) and `SuperH (SH) 64-Bit RISC Series' (SuperH).

   `as' implements all the standard SH opcodes.  No additional
pseudo-instructions are needed on this family.  Note, however, that
because `as' supports a simpler form of PC-relative addressing, you may
simply write (for example)

     mov.l  bar,r0

where other assemblers might require an explicit displacement to `bar'
from the program counter:

     mov.l  @(DISP, PC)

   Here is a summary of SH opcodes:

     Legend:
     Rn        a numbered register
     Rm        another numbered register
     #imm      immediate data
     disp      displacement
     disp8     8-bit displacement
     disp12    12-bit displacement
     
     add #imm,Rn                    lds.l @Rn+,PR
     add Rm,Rn                      mac.w @Rm+,@Rn+
     addc Rm,Rn                     mov #imm,Rn
     addv Rm,Rn                     mov Rm,Rn
     and #imm,R0                    mov.b Rm,@(R0,Rn)
     and Rm,Rn                      mov.b Rm,@-Rn
     and.b #imm,@(R0,GBR)           mov.b Rm,@Rn
     bf disp8                       mov.b @(disp,Rm),R0
     bra disp12                     mov.b @(disp,GBR),R0
     bsr disp12                     mov.b @(R0,Rm),Rn
     bt disp8                       mov.b @Rm+,Rn
     clrmac                         mov.b @Rm,Rn
     clrt                           mov.b R0,@(disp,Rm)
     cmp/eq #imm,R0                 mov.b R0,@(disp,GBR)
     cmp/eq Rm,Rn                   mov.l Rm,@(disp,Rn)
     cmp/ge Rm,Rn                   mov.l Rm,@(R0,Rn)
     cmp/gt Rm,Rn                   mov.l Rm,@-Rn
     cmp/hi Rm,Rn                   mov.l Rm,@Rn
     cmp/hs Rm,Rn                   mov.l @(disp,Rn),Rm
     cmp/pl Rn                      mov.l @(disp,GBR),R0
     cmp/pz Rn                      mov.l @(disp,PC),Rn
     cmp/str Rm,Rn                  mov.l @(R0,Rm),Rn
     div0s Rm,Rn                    mov.l @Rm+,Rn
     div0u                          mov.l @Rm,Rn
     div1 Rm,Rn                     mov.l R0,@(disp,GBR)
     exts.b Rm,Rn                   mov.w Rm,@(R0,Rn)
     exts.w Rm,Rn                   mov.w Rm,@-Rn
     extu.b Rm,Rn                   mov.w Rm,@Rn
     extu.w Rm,Rn                   mov.w @(disp,Rm),R0
     jmp @Rn                        mov.w @(disp,GBR),R0
     jsr @Rn                        mov.w @(disp,PC),Rn
     ldc Rn,GBR                     mov.w @(R0,Rm),Rn
     ldc Rn,SR                      mov.w @Rm+,Rn
     ldc Rn,VBR                     mov.w @Rm,Rn
     ldc.l @Rn+,GBR                 mov.w R0,@(disp,Rm)
     ldc.l @Rn+,SR                  mov.w R0,@(disp,GBR)
     ldc.l @Rn+,VBR                 mova @(disp,PC),R0
     lds Rn,MACH                    movt Rn
     lds Rn,MACL                    muls Rm,Rn
     lds Rn,PR                      mulu Rm,Rn
     lds.l @Rn+,MACH                neg Rm,Rn
     lds.l @Rn+,MACL                negc Rm,Rn
     
     nop                            stc VBR,Rn
     not Rm,Rn                      stc.l GBR,@-Rn
     or #imm,R0                     stc.l SR,@-Rn
     or Rm,Rn                       stc.l VBR,@-Rn
     or.b #imm,@(R0,GBR)            sts MACH,Rn
     rotcl Rn                       sts MACL,Rn
     rotcr Rn                       sts PR,Rn
     rotl Rn                        sts.l MACH,@-Rn
     rotr Rn                        sts.l MACL,@-Rn
     rte                            sts.l PR,@-Rn
     rts                            sub Rm,Rn
     sett                           subc Rm,Rn
     shal Rn                        subv Rm,Rn
     shar Rn                        swap.b Rm,Rn
     shll Rn                        swap.w Rm,Rn
     shll16 Rn                      tas.b @Rn
     shll2 Rn                       trapa #imm
     shll8 Rn                       tst #imm,R0
     shlr Rn                        tst Rm,Rn
     shlr16 Rn                      tst.b #imm,@(R0,GBR)
     shlr2 Rn                       xor #imm,R0
     shlr8 Rn                       xor Rm,Rn
     sleep                          xor.b #imm,@(R0,GBR)
     stc GBR,Rn                     xtrct Rm,Rn
     stc SR,Rn


File: as.info,  Node: SH64-Dependent,  Next: PDP-11-Dependent,  Prev: SH-Dependent,  Up: Machine Dependencies

SuperH SH64 Dependent Features
==============================

* Menu:

* SH64 Options::              Options
* SH64 Syntax::               Syntax
* SH64 Directives::           SH64 Machine Directives
* SH64 Opcodes::              Opcodes


File: as.info,  Node: SH64 Options,  Next: SH64 Syntax,  Up: SH64-Dependent

Options
-------

`-isa=shmedia | -isa=shcompact'
     Specify the default instruction set.  `SHmedia' specifies the
     32-bit opcodes, and `SHcompact' specifies the 16-bit opcodes
     compatible with previous SH families.  The default depends on the
     ABI selected; the default for the 64-bit ABI is SHmedia, and the
     default for the 32-bit ABI is SHcompact.  If neither the ABI nor
     the ISA is specified, the default is 32-bit SHcompact.

     Note that the `.mode' pseudo-op is not permitted if the ISA is not
     specified on the command line.

`-abi=32 | -abi=64'
     Specify the default ABI.  If the ISA is specified and the ABI is
     not, the default ABI depends on the ISA, with SHmedia defaulting
     to 64-bit and SHcompact defaulting to 32-bit.

     Note that the `.abi' pseudo-op is not permitted if the ABI is not
     specified on the command line.  When the ABI is specified on the
     command line, any `.abi' pseudo-ops in the source must match it.

`-shcompact-const-crange'
     Emit code-range descriptors for constants in SHcompact code
     sections.

`-no-mix'
     Disallow SHmedia code in the same section as constants and
     SHcompact code.

`-no-expand'
     Do not expand MOVI, PT, PTA or PTB instructions.

`-expand-pt32'
     With -abi=64, expand PT, PTA and PTB instructions to 32 bits only.


File: as.info,  Node: SH64 Syntax,  Next: SH64 Directives,  Prev: SH64 Options,  Up: SH64-Dependent

Syntax
------

* Menu:

* SH64-Chars::                Special Characters
* SH64-Regs::                 Register Names
* SH64-Addressing::           Addressing Modes


File: as.info,  Node: SH64-Chars,  Next: SH64-Regs,  Up: SH64 Syntax

Special Characters
..................

   `!' is the line comment character.

   You can use `;' instead of a newline to separate statements.

   Since `$' has no special meaning, you may use it in symbol names.


File: as.info,  Node: SH64-Regs,  Next: SH64-Addressing,  Prev: SH64-Chars,  Up: SH64 Syntax

Register Names
..............

   You can use the predefined symbols `r0' through `r63' to refer to
the SH64 general registers, `cr0' through `cr63' for control registers,
`tr0' through `tr7' for target address registers, `fr0' through `fr63'
for single-precision floating point registers, `dr0' through `dr62'
(even numbered registers only) for double-precision floating point
registers, `fv0' through `fv60' (multiples of four only) for
single-precision floating point vectors, `fp0' through `fp62' (even
numbered registers only) for single-precision floating point pairs,
`mtrx0' through `mtrx48' (multiples of 16 only) for 4x4 matrices of
single-precision floating point registers, `pc' for the program
counter, and `fpscr' for the floating point status and control register.

   You can also refer to the control registers by the mnemonics `sr',
`ssr', `pssr', `intevt', `expevt', `pexpevt', `tra', `spc', `pspc',
`resvec', `vbr', `tea', `dcr', `kcr0', `kcr1', `ctc', and `usr'.


File: as.info,  Node: SH64-Addressing,  Prev: SH64-Regs,  Up: SH64 Syntax

Addressing Modes
................

   SH64 operands consist of either a register or immediate value.  The
immediate value can be a constant or label reference (or portion of a
label reference), as in this example:

        movi    4,r2
        pt      function, tr4
        movi    (function >> 16) & 65535,r0
        shori   function & 65535, r0
        ld.l    r0,4,r0

   Instruction label references can reference labels in either SHmedia
or SHcompact.  To differentiate between the two, labels in SHmedia
sections will always have the least significant bit set (i.e. they will
be odd), which SHcompact labels will have the least significant bit
reset (i.e. they will be even).  If you need to reference the actual
address of a label, you can use the `datalabel' modifier, as in this
example:

        .long   function
        .long   datalabel function

   In that example, the first longword may or may not have the least
significant bit set depending on whether the label is an SHmedia label
or an SHcompact label.  The second longword will be the actual address
of the label, regardless of what type of label it is.


File: as.info,  Node: SH64 Directives,  Next: SH64 Opcodes,  Prev: SH64 Syntax,  Up: SH64-Dependent

SH64 Machine Directives
-----------------------

   In addition to the SH directives, the SH64 provides the following
directives:

`.mode [shmedia|shcompact]'
`.isa [shmedia|shcompact]'
     Specify the ISA for the following instructions (the two directives
     are equivalent).  Note that programs such as `objdump' rely on
     symbolic labels to determine when such mode switches occur (by
     checking the least significant bit of the label's address), so
     such mode/isa changes should always be followed by a label (in
     practice, this is true anyway).  Note that you cannot use these
     directives if you didn't specify an ISA on the command line.

`.abi [32|64]'
     Specify the ABI for the following instructions.  Note that you
     cannot use this directive unless you specified an ABI on the
     command line, and the ABIs specified must match.

`.uaquad'
     Like .uaword and .ualong, this allows you to specify an
     intenionally unaligned quadword (64 bit word).