source: trunk/binutils/gas/config/tc-m68k.c@ 2562

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1/* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002
4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23#include "as.h"
24#include "safe-ctype.h"
25#include "obstack.h"
26#include "subsegs.h"
27#include "dwarf2dbg.h"
28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
36/* This string holds the chars that always start a comment. If the
37 pre-processor is disabled, these aren't very useful. The macro
38 tc_comment_chars points to this. We use this, rather than the
39 usual comment_chars, so that the --bitwise-or option will work. */
40#if defined (TE_SVR4) || defined (TE_DELTA)
41const char *m68k_comment_chars = "|#";
42#else
43const char *m68k_comment_chars = "|";
44#endif
45
46/* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49/* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
51 #NO_APP at the beginning of its output. */
52/* Also note that comments like this one will always work. */
53const char line_comment_chars[] = "#*";
54
55const char line_separator_chars[] = ";";
56
57/* Chars that can be used to separate mant from exp in floating point nums */
58const char EXP_CHARS[] = "eE";
59
60/* Chars that mean this number is a floating point constant, as
61 in "0f12.456" or "0d1.2345e12". */
62
63const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
64
65/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here. */
68
69const int md_reloc_size = 8; /* Size of relocation record */
70
71/* Are we trying to generate PIC code? If so, absolute references
72 ought to be made into linkage table references or pc-relative
73 references. Not implemented. For ELF there are other means
74 to denote pic relocations. */
75int flag_want_pic;
76
77static int flag_short_refs; /* -l option */
78static int flag_long_jumps; /* -S option */
79static int flag_keep_pcrel; /* --pcrel option. */
80
81#ifdef REGISTER_PREFIX_OPTIONAL
82int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
83#else
84int flag_reg_prefix_optional;
85#endif
86
87/* Whether --register-prefix-optional was used on the command line. */
88static int reg_prefix_optional_seen;
89
90/* The floating point coprocessor to use by default. */
91static enum m68k_register m68k_float_copnum = COP1;
92
93/* If this is non-zero, then references to number(%pc) will be taken
94 to refer to number, rather than to %pc + number. */
95static int m68k_abspcadd;
96
97/* If this is non-zero, then the quick forms of the move, add, and sub
98 instructions are used when possible. */
99static int m68k_quick = 1;
100
101/* If this is non-zero, then if the size is not specified for a base
102 or outer displacement, the assembler assumes that the size should
103 be 32 bits. */
104static int m68k_rel32 = 1;
105
106/* This is non-zero if m68k_rel32 was set from the command line. */
107static int m68k_rel32_from_cmdline;
108
109/* The default width to use for an index register when using a base
110 displacement. */
111static enum m68k_size m68k_index_width_default = SIZE_LONG;
112
113/* We want to warn if any text labels are misaligned. In order to get
114 the right line number, we need to record the line number for each
115 label. */
116
117struct label_line
118{
119 struct label_line *next;
120 symbolS *label;
121 char *file;
122 unsigned int line;
123 int text;
124};
125
126/* The list of labels. */
127
128static struct label_line *labels;
129
130/* The current label. */
131
132static struct label_line *current_label;
133
134/* Its an arbitrary name: This means I don't approve of it */
135/* See flames below */
136static struct obstack robyn;
137
138struct m68k_incant
139 {
140 const char *m_operands;
141 unsigned long m_opcode;
142 short m_opnum;
143 short m_codenum;
144 int m_arch;
145 struct m68k_incant *m_next;
146 };
147
148#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
149#define gettwo(x) (((x)->m_opcode)&0xffff)
150
151static const enum m68k_register m68000_control_regs[] = { 0 };
152static const enum m68k_register m68010_control_regs[] = {
153 SFC, DFC, USP, VBR,
154 0
155};
156static const enum m68k_register m68020_control_regs[] = {
157 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
158 0
159};
160static const enum m68k_register m68040_control_regs[] = {
161 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
162 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
163 0
164};
165static const enum m68k_register m68060_control_regs[] = {
166 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
167 USP, VBR, URP, SRP, PCR,
168 0
169};
170static const enum m68k_register mcf_control_regs[] = {
171 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
172 RAMBAR0, RAMBAR1, MBAR,
173 0
174};
175#define cpu32_control_regs m68010_control_regs
176
177static const enum m68k_register *control_regs;
178
179/* internal form of a 68020 instruction */
180struct m68k_it
181{
182 const char *error;
183 const char *args; /* list of opcode info */
184 int numargs;
185
186 int numo; /* Number of shorts in opcode */
187 short opcode[11];
188
189 struct m68k_op operands[6];
190
191 int nexp; /* number of exprs in use */
192 struct m68k_exp exprs[4];
193
194 int nfrag; /* Number of frags we have to produce */
195 struct
196 {
197 int fragoff; /* Where in the current opcode the frag ends */
198 symbolS *fadd;
199 offsetT foff;
200 int fragty;
201 }
202 fragb[4];
203
204 int nrel; /* Num of reloc strucs in use */
205 struct
206 {
207 int n;
208 expressionS exp;
209 char wid;
210 char pcrel;
211 /* In a pc relative address the difference between the address
212 of the offset and the address that the offset is relative
213 to. This depends on the addressing mode. Basically this
214 is the value to put in the offset field to address the
215 first byte of the offset, without regarding the special
216 significance of some values (in the branch instruction, for
217 example). */
218 int pcrel_fix;
219#ifdef OBJ_ELF
220 /* Whether this expression needs special pic relocation, and if
221 so, which. */
222 enum pic_relocation pic_reloc;
223#endif
224 }
225 reloc[5]; /* Five is enough??? */
226};
227
228#define cpu_of_arch(x) ((x) & (m68000up|mcf))
229#define float_of_arch(x) ((x) & mfloat)
230#define mmu_of_arch(x) ((x) & mmmu)
231#define arch_coldfire_p(x) (((x) & mcf) != 0)
232
233/* Macros for determining if cpu supports a specific addressing mode */
234#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
235
236static struct m68k_it the_ins; /* the instruction being assembled */
237
238#define op(ex) ((ex)->exp.X_op)
239#define adds(ex) ((ex)->exp.X_add_symbol)
240#define subs(ex) ((ex)->exp.X_op_symbol)
241#define offs(ex) ((ex)->exp.X_add_number)
242
243/* Macros for adding things to the m68k_it struct */
244
245#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
246
247/* Static functions. */
248
249static void insop PARAMS ((int, const struct m68k_incant *));
250static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
251static void add_frag PARAMS ((symbolS *, offsetT, int));
252
253/* Like addword, but goes BEFORE general operands */
254static void
255insop (w, opcode)
256 int w;
257 const struct m68k_incant *opcode;
258{
259 int z;
260 for (z = the_ins.numo; z > opcode->m_codenum; --z)
261 the_ins.opcode[z] = the_ins.opcode[z - 1];
262 for (z = 0; z < the_ins.nrel; z++)
263 the_ins.reloc[z].n += 2;
264 for (z = 0; z < the_ins.nfrag; z++)
265 the_ins.fragb[z].fragoff++;
266 the_ins.opcode[opcode->m_codenum] = w;
267 the_ins.numo++;
268}
269
270/* The numo+1 kludge is so we can hit the low order byte of the prev word.
271 Blecch. */
272static void
273add_fix (width, exp, pc_rel, pc_fix)
274 int width;
275 struct m68k_exp *exp;
276 int pc_rel;
277 int pc_fix;
278{
279 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
280 ? (the_ins.numo*2-1)
281 : (((width)=='b')
282 ? (the_ins.numo*2+1)
283 : (the_ins.numo*2)));
284 the_ins.reloc[the_ins.nrel].exp = exp->exp;
285 the_ins.reloc[the_ins.nrel].wid = width;
286 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
287#ifdef OBJ_ELF
288 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
289#endif
290 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
291}
292
293/* Cause an extra frag to be generated here, inserting up to 10 bytes
294 (that value is chosen in the frag_var call in md_assemble). TYPE
295 is the subtype of the frag to be generated; its primary type is
296 rs_machine_dependent.
297
298 The TYPE parameter is also used by md_convert_frag_1 and
299 md_estimate_size_before_relax. The appropriate type of fixup will
300 be emitted by md_convert_frag_1.
301
302 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
303static void
304add_frag (add, off, type)
305 symbolS *add;
306 offsetT off;
307 int type;
308{
309 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
310 the_ins.fragb[the_ins.nfrag].fadd = add;
311 the_ins.fragb[the_ins.nfrag].foff = off;
312 the_ins.fragb[the_ins.nfrag++].fragty = type;
313}
314
315#define isvar(ex) \
316 (op (ex) != O_constant && op (ex) != O_big)
317
318static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
319static int get_num PARAMS ((struct m68k_exp *exp, int ok));
320static void m68k_ip PARAMS ((char *));
321static void insert_reg PARAMS ((const char *, int));
322static void select_control_regs PARAMS ((void));
323static void init_regtable PARAMS ((void));
324static int reverse_16_bits PARAMS ((int in));
325static int reverse_8_bits PARAMS ((int in));
326static void install_gen_operand PARAMS ((int mode, int val));
327static void install_operand PARAMS ((int mode, int val));
328static void s_bss PARAMS ((int));
329static void s_data1 PARAMS ((int));
330static void s_data2 PARAMS ((int));
331static void s_even PARAMS ((int));
332static void s_proc PARAMS ((int));
333static void mri_chip PARAMS ((void));
334static void s_chip PARAMS ((int));
335static void s_fopt PARAMS ((int));
336static void s_opt PARAMS ((int));
337static void s_reg PARAMS ((int));
338static void s_restore PARAMS ((int));
339static void s_save PARAMS ((int));
340static void s_mri_if PARAMS ((int));
341static void s_mri_else PARAMS ((int));
342static void s_mri_endi PARAMS ((int));
343static void s_mri_break PARAMS ((int));
344static void s_mri_next PARAMS ((int));
345static void s_mri_for PARAMS ((int));
346static void s_mri_endf PARAMS ((int));
347static void s_mri_repeat PARAMS ((int));
348static void s_mri_until PARAMS ((int));
349static void s_mri_while PARAMS ((int));
350static void s_mri_endw PARAMS ((int));
351static void md_convert_frag_1 PARAMS ((fragS *));
352
353static int current_architecture;
354
355struct m68k_cpu
356 {
357 unsigned long arch;
358 const char *name;
359 int alias;
360 };
361
362static const struct m68k_cpu archs[] =
363 {
364 { m68000, "68000", 0 },
365 { m68010, "68010", 0 },
366 { m68020, "68020", 0 },
367 { m68030, "68030", 0 },
368 { m68040, "68040", 0 },
369 { m68060, "68060", 0 },
370 { cpu32, "cpu32", 0 },
371 { m68881, "68881", 0 },
372 { m68851, "68851", 0 },
373 { mcf5200, "5200", 0 },
374 { mcf5206e, "5206e", 0 },
375 { mcf5307, "5307", 0},
376 { mcf5407, "5407", 0},
377 /* Aliases (effectively, so far as gas is concerned) for the above
378 cpus. */
379 { m68020, "68k", 1 },
380 { m68000, "68008", 1 },
381 { m68000, "68302", 1 },
382 { m68000, "68306", 1 },
383 { m68000, "68307", 1 },
384 { m68000, "68322", 1 },
385 { m68000, "68356", 1 },
386 { m68000, "68ec000", 1 },
387 { m68000, "68hc000", 1 },
388 { m68000, "68hc001", 1 },
389 { m68020, "68ec020", 1 },
390 { m68030, "68ec030", 1 },
391 { m68040, "68ec040", 1 },
392 { m68060, "68ec060", 1 },
393 { cpu32, "68330", 1 },
394 { cpu32, "68331", 1 },
395 { cpu32, "68332", 1 },
396 { cpu32, "68333", 1 },
397 { cpu32, "68334", 1 },
398 { cpu32, "68336", 1 },
399 { cpu32, "68340", 1 },
400 { cpu32, "68341", 1 },
401 { cpu32, "68349", 1 },
402 { cpu32, "68360", 1 },
403 { m68881, "68882", 1 },
404 { mcf5200, "5202", 1 },
405 { mcf5200, "5204", 1 },
406 { mcf5200, "5206", 1 },
407 };
408
409static const int n_archs = sizeof (archs) / sizeof (archs[0]);
410
411/* This is the assembler relaxation table for m68k. m68k is a rich CISC
412 architecture and we have a lot of relaxation modes. */
413
414/* Macros used in the relaxation code. */
415#define TAB(x,y) (((x) << 2) + (y))
416#define TABTYPE(x) ((x) >> 2)
417
418/* Relaxation states. */
419#define BYTE 0
420#define SHORT 1
421#define LONG 2
422#define SZ_UNDEF 3
423
424/* Here are all the relaxation modes we support. First we can relax ordinary
425 branches. On 68020 and higher and on CPU32 all branch instructions take
426 three forms, so on these CPUs all branches always remain as such. When we
427 have to expand to the LONG form on a 68000, though, we substitute an
428 absolute jump instead. This is a direct replacement for unconditional
429 branches and a branch over a jump for conditional branches. However, if the
430 user requires PIC and disables this with --pcrel, we can only relax between
431 BYTE and SHORT forms, punting if that isn't enough. This gives us four
432 different relaxation modes for branches: */
433
434#define BRANCHBWL 0 /* branch byte, word, or long */
435#define BRABSJUNC 1 /* absolute jump for LONG, unconditional */
436#define BRABSJCOND 2 /* absolute jump for LONG, conditional */
437#define BRANCHBW 3 /* branch byte or word */
438
439/* We also relax coprocessor branches and DBcc's. All CPUs that support
440 coprocessor branches support them in word and long forms, so we have only
441 one relaxation mode for them. DBcc's are word only on all CPUs. We can
442 relax them to the LONG form with a branch-around sequence. This sequence
443 can use a long branch (if available) or an absolute jump (if acceptable).
444 This gives us two relaxation modes. If long branches are not available and
445 absolute jumps are not acceptable, we don't relax DBcc's. */
446
447#define FBRANCH 4 /* coprocessor branch */
448#define DBCCLBR 5 /* DBcc relaxable with a long branch */
449#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump */
450
451/* That's all for instruction relaxation. However, we also relax PC-relative
452 operands. Specifically, we have three operand relaxation modes. On the
453 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
454 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
455 two. Also PC+displacement+index operands in their simple form (with a non-
456 suppressed index without memory indirection) are supported on all CPUs, but
457 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
458 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
459 form of the PC+displacement+index operand. Finally, some absolute operands
460 can be relaxed down to 16-bit PC-relative. */
461
462#define PCREL1632 7 /* 16-bit or 32-bit PC-relative */
463#define PCINDEX 8 /* PC+displacement+index */
464#define ABSTOPCREL 9 /* absolute relax down to 16-bit PC-relative */
465
466/* Note that calls to frag_var need to specify the maximum expansion
467 needed; this is currently 10 bytes for DBCC. */
468
469/* The fields are:
470 How far Forward this mode will reach:
471 How far Backward this mode will reach:
472 How many bytes this mode will add to the size of the frag
473 Which mode to go to if the offset won't fit in this one
474
475 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
476relax_typeS md_relax_table[] =
477{
478 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
479 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
480 { 0, 0, 4, 0 },
481 { 1, 1, 0, 0 },
482
483 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
484 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
485 { 0, 0, 4, 0 },
486 { 1, 1, 0, 0 },
487
488 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
489 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
490 { 0, 0, 6, 0 },
491 { 1, 1, 0, 0 },
492
493 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
494 { 0, 0, 2, 0 },
495 { 1, 1, 0, 0 },
496 { 1, 1, 0, 0 },
497
498 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
499 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
500 { 0, 0, 4, 0 },
501 { 1, 1, 0, 0 },
502
503 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
504 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
505 { 0, 0, 10, 0 },
506 { 1, 1, 0, 0 },
507
508 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
509 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
510 { 0, 0, 10, 0 },
511 { 1, 1, 0, 0 },
512
513 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE */
514 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
515 { 0, 0, 6, 0 },
516 { 1, 1, 0, 0 },
517
518 { 125, -130, 0, TAB (PCINDEX, SHORT) },
519 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
520 { 0, 0, 4, 0 },
521 { 1, 1, 0, 0 },
522
523 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE */
524 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
525 { 0, 0, 4, 0 },
526 { 1, 1, 0, 0 },
527};
528
529/* These are the machine dependent pseudo-ops. These are included so
530 the assembler can work on the output from the SUN C compiler, which
531 generates these.
532 */
533
534/* This table describes all the machine specific pseudo-ops the assembler
535 has to support. The fields are:
536 pseudo-op name without dot
537 function to call to execute this pseudo-op
538 Integer arg to pass to the function
539 */
540const pseudo_typeS md_pseudo_table[] =
541{
542 {"data1", s_data1, 0},
543 {"data2", s_data2, 0},
544 {"bss", s_bss, 0},
545 {"even", s_even, 0},
546 {"skip", s_space, 0},
547 {"proc", s_proc, 0},
548#if defined (TE_SUN3) || defined (OBJ_ELF)
549 {"align", s_align_bytes, 0},
550#endif
551#ifdef OBJ_ELF
552 {"swbeg", s_ignore, 0},
553#endif
554 {"extend", float_cons, 'x'},
555 {"ldouble", float_cons, 'x'},
556
557#ifdef OBJ_ELF
558 /* Dwarf2 support for Gcc. */
559 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
560 {"loc", dwarf2_directive_loc, 0},
561#endif
562
563 /* The following pseudo-ops are supported for MRI compatibility. */
564 {"chip", s_chip, 0},
565 {"comline", s_space, 1},
566 {"fopt", s_fopt, 0},
567 {"mask2", s_ignore, 0},
568 {"opt", s_opt, 0},
569 {"reg", s_reg, 0},
570 {"restore", s_restore, 0},
571 {"save", s_save, 0},
572
573 {"if", s_mri_if, 0},
574 {"if.b", s_mri_if, 'b'},
575 {"if.w", s_mri_if, 'w'},
576 {"if.l", s_mri_if, 'l'},
577 {"else", s_mri_else, 0},
578 {"else.s", s_mri_else, 's'},
579 {"else.l", s_mri_else, 'l'},
580 {"endi", s_mri_endi, 0},
581 {"break", s_mri_break, 0},
582 {"break.s", s_mri_break, 's'},
583 {"break.l", s_mri_break, 'l'},
584 {"next", s_mri_next, 0},
585 {"next.s", s_mri_next, 's'},
586 {"next.l", s_mri_next, 'l'},
587 {"for", s_mri_for, 0},
588 {"for.b", s_mri_for, 'b'},
589 {"for.w", s_mri_for, 'w'},
590 {"for.l", s_mri_for, 'l'},
591 {"endf", s_mri_endf, 0},
592 {"repeat", s_mri_repeat, 0},
593 {"until", s_mri_until, 0},
594 {"until.b", s_mri_until, 'b'},
595 {"until.w", s_mri_until, 'w'},
596 {"until.l", s_mri_until, 'l'},
597 {"while", s_mri_while, 0},
598 {"while.b", s_mri_while, 'b'},
599 {"while.w", s_mri_while, 'w'},
600 {"while.l", s_mri_while, 'l'},
601 {"endw", s_mri_endw, 0},
602
603 {0, 0, 0}
604};
605
606/* The mote pseudo ops are put into the opcode table, since they
607 don't start with a . they look like opcodes to gas.
608 */
609
610#ifdef M68KCOFF
611extern void obj_coff_section PARAMS ((int));
612#endif
613
614const pseudo_typeS mote_pseudo_table[] =
615{
616
617 {"dcl", cons, 4},
618 {"dc", cons, 2},
619 {"dcw", cons, 2},
620 {"dcb", cons, 1},
621
622 {"dsl", s_space, 4},
623 {"ds", s_space, 2},
624 {"dsw", s_space, 2},
625 {"dsb", s_space, 1},
626
627 {"xdef", s_globl, 0},
628#ifdef OBJ_ELF
629 {"align", s_align_bytes, 0},
630#else
631 {"align", s_align_ptwo, 0},
632#endif
633#ifdef M68KCOFF
634 {"sect", obj_coff_section, 0},
635 {"section", obj_coff_section, 0},
636#endif
637 {0, 0, 0}
638};
639
640#define issbyte(x) ((x)>=-128 && (x)<=127)
641#define isubyte(x) ((x)>=0 && (x)<=255)
642#define issword(x) ((x)>=-32768 && (x)<=32767)
643#define isuword(x) ((x)>=0 && (x)<=65535)
644
645#define isbyte(x) ((x)>= -255 && (x)<=255)
646#define isword(x) ((x)>=-65536 && (x)<=65535)
647#define islong(x) (1)
648
649extern char *input_line_pointer;
650
651static char notend_table[256];
652static char alt_notend_table[256];
653#define notend(s) \
654 (! (notend_table[(unsigned char) *s] \
655 || (*s == ':' \
656 && alt_notend_table[(unsigned char) s[1]])))
657
658#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
659
660#ifdef NO_PCREL_RELOCS
661
662int
663make_pcrel_absolute(fixP, add_number)
664 fixS *fixP;
665 long *add_number;
666{
667 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
668
669 /* rewrite the PC relative instructions to absolute address ones.
670 * these are rumoured to be faster, and the apollo linker refuses
671 * to deal with the PC relative relocations.
672 */
673 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
674 {
675 opcode[0] = 0x4e;
676 opcode[1] = 0xf9;
677 }
678 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
679 {
680 opcode[0] = 0x4e;
681 opcode[1] = 0xb9;
682 }
683 else
684 as_fatal (_("Unknown PC relative instruction"));
685 *add_number -= 4;
686 return 0;
687}
688
689#endif /* NO_PCREL_RELOCS */
690
691short
692tc_coff_fix2rtype (fixP)
693 fixS *fixP;
694{
695 if (fixP->fx_tcbit && fixP->fx_size == 4)
696 return R_RELLONG_NEG;
697#ifdef NO_PCREL_RELOCS
698 know (fixP->fx_pcrel == 0);
699 return (fixP->fx_size == 1 ? R_RELBYTE
700 : fixP->fx_size == 2 ? R_DIR16
701 : R_DIR32);
702#else
703 return (fixP->fx_pcrel ?
704 (fixP->fx_size == 1 ? R_PCRBYTE :
705 fixP->fx_size == 2 ? R_PCRWORD :
706 R_PCRLONG) :
707 (fixP->fx_size == 1 ? R_RELBYTE :
708 fixP->fx_size == 2 ? R_RELWORD :
709 R_RELLONG));
710#endif
711}
712
713#endif
714
715#ifdef OBJ_ELF
716
717/* Return zero if the reference to SYMBOL from within the same segment may
718 be relaxed. */
719
720/* On an ELF system, we can't relax an externally visible symbol,
721 because it may be overridden by a shared library. However, if
722 TARGET_OS is "elf", then we presume that we are assembling for an
723 embedded system, in which case we don't have to worry about shared
724 libraries, and we can relax any external sym. */
725
726#define relaxable_symbol(symbol) \
727 (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \
728 || S_IS_WEAK (symbol)))
729
730/* Compute the relocation code for a fixup of SIZE bytes, using pc
731 relative relocation if PCREL is non-zero. PIC says whether a special
732 pic relocation was requested. */
733
734static bfd_reloc_code_real_type get_reloc_code
735 PARAMS ((int, int, enum pic_relocation));
736
737static bfd_reloc_code_real_type
738get_reloc_code (size, pcrel, pic)
739 int size;
740 int pcrel;
741 enum pic_relocation pic;
742{
743 switch (pic)
744 {
745 case pic_got_pcrel:
746 switch (size)
747 {
748 case 1:
749 return BFD_RELOC_8_GOT_PCREL;
750 case 2:
751 return BFD_RELOC_16_GOT_PCREL;
752 case 4:
753 return BFD_RELOC_32_GOT_PCREL;
754 }
755 break;
756
757 case pic_got_off:
758 switch (size)
759 {
760 case 1:
761 return BFD_RELOC_8_GOTOFF;
762 case 2:
763 return BFD_RELOC_16_GOTOFF;
764 case 4:
765 return BFD_RELOC_32_GOTOFF;
766 }
767 break;
768
769 case pic_plt_pcrel:
770 switch (size)
771 {
772 case 1:
773 return BFD_RELOC_8_PLT_PCREL;
774 case 2:
775 return BFD_RELOC_16_PLT_PCREL;
776 case 4:
777 return BFD_RELOC_32_PLT_PCREL;
778 }
779 break;
780
781 case pic_plt_off:
782 switch (size)
783 {
784 case 1:
785 return BFD_RELOC_8_PLTOFF;
786 case 2:
787 return BFD_RELOC_16_PLTOFF;
788 case 4:
789 return BFD_RELOC_32_PLTOFF;
790 }
791 break;
792
793 case pic_none:
794 if (pcrel)
795 {
796 switch (size)
797 {
798 case 1:
799 return BFD_RELOC_8_PCREL;
800 case 2:
801 return BFD_RELOC_16_PCREL;
802 case 4:
803 return BFD_RELOC_32_PCREL;
804 }
805 }
806 else
807 {
808 switch (size)
809 {
810 case 1:
811 return BFD_RELOC_8;
812 case 2:
813 return BFD_RELOC_16;
814 case 4:
815 return BFD_RELOC_32;
816 }
817 }
818 }
819
820 if (pcrel)
821 {
822 if (pic == pic_none)
823 as_bad (_("Can not do %d byte pc-relative relocation"), size);
824 else
825 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
826 }
827 else
828 {
829 if (pic == pic_none)
830 as_bad (_("Can not do %d byte relocation"), size);
831 else
832 as_bad (_("Can not do %d byte pic relocation"), size);
833 }
834
835 return BFD_RELOC_NONE;
836}
837
838/* Here we decide which fixups can be adjusted to make them relative
839 to the beginning of the section instead of the symbol. Basically
840 we need to make sure that the dynamic relocations are done
841 correctly, so in some cases we force the original symbol to be
842 used. */
843int
844tc_m68k_fix_adjustable (fixP)
845 fixS *fixP;
846{
847 /* adjust_reloc_syms doesn't know about the GOT */
848 switch (fixP->fx_r_type)
849 {
850 case BFD_RELOC_8_GOT_PCREL:
851 case BFD_RELOC_16_GOT_PCREL:
852 case BFD_RELOC_32_GOT_PCREL:
853 case BFD_RELOC_8_GOTOFF:
854 case BFD_RELOC_16_GOTOFF:
855 case BFD_RELOC_32_GOTOFF:
856 case BFD_RELOC_8_PLT_PCREL:
857 case BFD_RELOC_16_PLT_PCREL:
858 case BFD_RELOC_32_PLT_PCREL:
859 case BFD_RELOC_8_PLTOFF:
860 case BFD_RELOC_16_PLTOFF:
861 case BFD_RELOC_32_PLTOFF:
862 return 0;
863
864 case BFD_RELOC_VTABLE_INHERIT:
865 case BFD_RELOC_VTABLE_ENTRY:
866 return 0;
867
868 default:
869 return 1;
870 }
871}
872
873#else /* !OBJ_ELF */
874
875#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
876
877#define relaxable_symbol(symbol) 1
878
879#endif /* OBJ_ELF */
880
881#ifdef BFD_ASSEMBLER
882
883arelent *
884tc_gen_reloc (section, fixp)
885 asection *section ATTRIBUTE_UNUSED;
886 fixS *fixp;
887{
888 arelent *reloc;
889 bfd_reloc_code_real_type code;
890
891 /* If the tcbit is set, then this was a fixup of a negative value
892 that was never resolved. We do not have a reloc to handle this,
893 so just return. We assume that other code will have detected this
894 situation and produced a helpful error message, so we just tell the
895 user that the reloc cannot be produced. */
896 if (fixp->fx_tcbit)
897 {
898 if (fixp->fx_addsy)
899 as_bad_where (fixp->fx_file, fixp->fx_line,
900 _("Unable to produce reloc against symbol '%s'"),
901 S_GET_NAME (fixp->fx_addsy));
902 return NULL;
903 }
904
905 if (fixp->fx_r_type != BFD_RELOC_NONE)
906 {
907 code = fixp->fx_r_type;
908
909 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
910 that fixup_segment converted a non-PC relative reloc into a
911 PC relative reloc. In such a case, we need to convert the
912 reloc code. */
913 if (fixp->fx_pcrel)
914 {
915 switch (code)
916 {
917 case BFD_RELOC_8:
918 code = BFD_RELOC_8_PCREL;
919 break;
920 case BFD_RELOC_16:
921 code = BFD_RELOC_16_PCREL;
922 break;
923 case BFD_RELOC_32:
924 code = BFD_RELOC_32_PCREL;
925 break;
926 case BFD_RELOC_8_PCREL:
927 case BFD_RELOC_16_PCREL:
928 case BFD_RELOC_32_PCREL:
929 case BFD_RELOC_8_GOT_PCREL:
930 case BFD_RELOC_16_GOT_PCREL:
931 case BFD_RELOC_32_GOT_PCREL:
932 case BFD_RELOC_8_GOTOFF:
933 case BFD_RELOC_16_GOTOFF:
934 case BFD_RELOC_32_GOTOFF:
935 case BFD_RELOC_8_PLT_PCREL:
936 case BFD_RELOC_16_PLT_PCREL:
937 case BFD_RELOC_32_PLT_PCREL:
938 case BFD_RELOC_8_PLTOFF:
939 case BFD_RELOC_16_PLTOFF:
940 case BFD_RELOC_32_PLTOFF:
941 break;
942 default:
943 as_bad_where (fixp->fx_file, fixp->fx_line,
944 _("Cannot make %s relocation PC relative"),
945 bfd_get_reloc_code_name (code));
946 }
947 }
948 }
949 else
950 {
951#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
952 switch (F (fixp->fx_size, fixp->fx_pcrel))
953 {
954#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
955 MAP (1, 0, BFD_RELOC_8);
956 MAP (2, 0, BFD_RELOC_16);
957 MAP (4, 0, BFD_RELOC_32);
958 MAP (1, 1, BFD_RELOC_8_PCREL);
959 MAP (2, 1, BFD_RELOC_16_PCREL);
960 MAP (4, 1, BFD_RELOC_32_PCREL);
961 default:
962 abort ();
963 }
964 }
965#undef F
966#undef MAP
967
968 reloc = (arelent *) xmalloc (sizeof (arelent));
969 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
970 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
971 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
972#ifndef OBJ_ELF
973 if (fixp->fx_pcrel)
974 reloc->addend = fixp->fx_addnumber;
975 else
976 reloc->addend = 0;
977#else
978 if (!fixp->fx_pcrel)
979 reloc->addend = fixp->fx_addnumber;
980 else
981 reloc->addend = (section->vma
982 /* Explicit sign extension in case char is
983 unsigned. */
984 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
985 + fixp->fx_addnumber
986 + md_pcrel_from (fixp));
987#endif
988
989 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
990 assert (reloc->howto != 0);
991
992 return reloc;
993}
994
995#endif /* BFD_ASSEMBLER */
996
997/* Handle of the OPCODE hash table. NULL means any use before
998 m68k_ip_begin() will crash. */
999static struct hash_control *op_hash;
1000
1001
1002/* Assemble an m68k instruction. */
1003
1004static void
1005m68k_ip (instring)
1006 char *instring;
1007{
1008 register char *p;
1009 register struct m68k_op *opP;
1010 register const struct m68k_incant *opcode;
1011 register const char *s;
1012 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1013 char *pdot, *pdotmove;
1014 enum m68k_size siz1, siz2;
1015 char c;
1016 int losing;
1017 int opsfound;
1018 LITTLENUM_TYPE words[6];
1019 LITTLENUM_TYPE *wordp;
1020 unsigned long ok_arch = 0;
1021
1022 if (*instring == ' ')
1023 instring++; /* skip leading whitespace */
1024
1025 /* Scan up to end of operation-code, which MUST end in end-of-string
1026 or exactly 1 space. */
1027 pdot = 0;
1028 for (p = instring; *p != '\0'; p++)
1029 {
1030 if (*p == ' ')
1031 break;
1032 if (*p == '.')
1033 pdot = p;
1034 }
1035
1036 if (p == instring)
1037 {
1038 the_ins.error = _("No operator");
1039 return;
1040 }
1041
1042 /* p now points to the end of the opcode name, probably whitespace.
1043 Make sure the name is null terminated by clobbering the
1044 whitespace, look it up in the hash table, then fix it back.
1045 Remove a dot, first, since the opcode tables have none. */
1046 if (pdot != NULL)
1047 {
1048 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1049 *pdotmove = pdotmove[1];
1050 p--;
1051 }
1052
1053 c = *p;
1054 *p = '\0';
1055 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1056 *p = c;
1057
1058 if (pdot != NULL)
1059 {
1060 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1061 *pdotmove = pdotmove[-1];
1062 *pdot = '.';
1063 ++p;
1064 }
1065
1066 if (opcode == NULL)
1067 {
1068 the_ins.error = _("Unknown operator");
1069 return;
1070 }
1071
1072 /* found a legitimate opcode, start matching operands */
1073 while (*p == ' ')
1074 ++p;
1075
1076 if (opcode->m_operands == 0)
1077 {
1078 char *old = input_line_pointer;
1079 *old = '\n';
1080 input_line_pointer = p;
1081 /* Ahh - it's a motorola style psuedo op */
1082 mote_pseudo_table[opcode->m_opnum].poc_handler
1083 (mote_pseudo_table[opcode->m_opnum].poc_val);
1084 input_line_pointer = old;
1085 *old = 0;
1086
1087 return;
1088 }
1089
1090 if (flag_mri && opcode->m_opnum == 0)
1091 {
1092 /* In MRI mode, random garbage is allowed after an instruction
1093 which accepts no operands. */
1094 the_ins.args = opcode->m_operands;
1095 the_ins.numargs = opcode->m_opnum;
1096 the_ins.numo = opcode->m_codenum;
1097 the_ins.opcode[0] = getone (opcode);
1098 the_ins.opcode[1] = gettwo (opcode);
1099 return;
1100 }
1101
1102 for (opP = &the_ins.operands[0]; *p; opP++)
1103 {
1104 p = crack_operand (p, opP);
1105
1106 if (opP->error)
1107 {
1108 the_ins.error = opP->error;
1109 return;
1110 }
1111 }
1112
1113 opsfound = opP - &the_ins.operands[0];
1114
1115 /* This ugly hack is to support the floating pt opcodes in their
1116 standard form. Essentially, we fake a first enty of type COP#1 */
1117 if (opcode->m_operands[0] == 'I')
1118 {
1119 int n;
1120
1121 for (n = opsfound; n > 0; --n)
1122 the_ins.operands[n] = the_ins.operands[n - 1];
1123
1124 memset ((char *) (&the_ins.operands[0]), '\0',
1125 sizeof (the_ins.operands[0]));
1126 the_ins.operands[0].mode = CONTROL;
1127 the_ins.operands[0].reg = m68k_float_copnum;
1128 opsfound++;
1129 }
1130
1131 /* We've got the operands. Find an opcode that'll accept them */
1132 for (losing = 0;;)
1133 {
1134 /* If we didn't get the right number of ops, or we have no
1135 common model with this pattern then reject this pattern. */
1136
1137 ok_arch |= opcode->m_arch;
1138 if (opsfound != opcode->m_opnum
1139 || ((opcode->m_arch & current_architecture) == 0))
1140 ++losing;
1141 else
1142 {
1143 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1144 *s && !losing;
1145 s += 2, opP++)
1146 {
1147 /* Warning: this switch is huge! */
1148 /* I've tried to organize the cases into this order:
1149 non-alpha first, then alpha by letter. Lower-case
1150 goes directly before uppercase counterpart. */
1151 /* Code with multiple case ...: gets sorted by the lowest
1152 case ... it belongs to. I hope this makes sense. */
1153 switch (*s)
1154 {
1155 case '!':
1156 switch (opP->mode)
1157 {
1158 case IMMED:
1159 case DREG:
1160 case AREG:
1161 case FPREG:
1162 case CONTROL:
1163 case AINC:
1164 case ADEC:
1165 case REGLST:
1166 losing++;
1167 break;
1168 default:
1169 break;
1170 }
1171 break;
1172
1173 case '<':
1174 switch (opP->mode)
1175 {
1176 case DREG:
1177 case AREG:
1178 case FPREG:
1179 case CONTROL:
1180 case IMMED:
1181 case ADEC:
1182 case REGLST:
1183 losing++;
1184 break;
1185 default:
1186 break;
1187 }
1188 break;
1189
1190 case '>':
1191 switch (opP->mode)
1192 {
1193 case DREG:
1194 case AREG:
1195 case FPREG:
1196 case CONTROL:
1197 case IMMED:
1198 case AINC:
1199 case REGLST:
1200 losing++;
1201 break;
1202 case ABSL:
1203 break;
1204 default:
1205 if (opP->reg == PC
1206 || opP->reg == ZPC)
1207 losing++;
1208 break;
1209 }
1210 break;
1211
1212 case 'm':
1213 switch (opP->mode)
1214 {
1215 case DREG:
1216 case AREG:
1217 case AINDR:
1218 case AINC:
1219 case ADEC:
1220 break;
1221 default:
1222 losing++;
1223 }
1224 break;
1225
1226 case 'n':
1227 switch (opP->mode)
1228 {
1229 case DISP:
1230 break;
1231 default:
1232 losing++;
1233 }
1234 break;
1235
1236 case 'o':
1237 switch (opP->mode)
1238 {
1239 case BASE:
1240 case ABSL:
1241 case IMMED:
1242 break;
1243 default:
1244 losing++;
1245 }
1246 break;
1247
1248 case 'p':
1249 switch (opP->mode)
1250 {
1251 case DREG:
1252 case AREG:
1253 case AINDR:
1254 case AINC:
1255 case ADEC:
1256 break;
1257 case DISP:
1258 if (opP->reg == PC || opP->reg == ZPC)
1259 losing++;
1260 break;
1261 default:
1262 losing++;
1263 }
1264 break;
1265
1266 case 'q':
1267 switch (opP->mode)
1268 {
1269 case DREG:
1270 case AINDR:
1271 case AINC:
1272 case ADEC:
1273 break;
1274 case DISP:
1275 if (opP->reg == PC || opP->reg == ZPC)
1276 losing++;
1277 break;
1278 default:
1279 losing++;
1280 break;
1281 }
1282 break;
1283
1284 case 'v':
1285 switch (opP->mode)
1286 {
1287 case DREG:
1288 case AINDR:
1289 case AINC:
1290 case ADEC:
1291 case ABSL:
1292 break;
1293 case DISP:
1294 if (opP->reg == PC || opP->reg == ZPC)
1295 losing++;
1296 break;
1297 default:
1298 losing++;
1299 break;
1300 }
1301 break;
1302
1303 case '#':
1304 if (opP->mode != IMMED)
1305 losing++;
1306 else if (s[1] == 'b'
1307 && ! isvar (&opP->disp)
1308 && (opP->disp.exp.X_op != O_constant
1309 || ! isbyte (opP->disp.exp.X_add_number)))
1310 losing++;
1311 else if (s[1] == 'B'
1312 && ! isvar (&opP->disp)
1313 && (opP->disp.exp.X_op != O_constant
1314 || ! issbyte (opP->disp.exp.X_add_number)))
1315 losing++;
1316 else if (s[1] == 'w'
1317 && ! isvar (&opP->disp)
1318 && (opP->disp.exp.X_op != O_constant
1319 || ! isword (opP->disp.exp.X_add_number)))
1320 losing++;
1321 else if (s[1] == 'W'
1322 && ! isvar (&opP->disp)
1323 && (opP->disp.exp.X_op != O_constant
1324 || ! issword (opP->disp.exp.X_add_number)))
1325 losing++;
1326 break;
1327
1328 case '^':
1329 case 'T':
1330 if (opP->mode != IMMED)
1331 losing++;
1332 break;
1333
1334 case '$':
1335 if (opP->mode == AREG
1336 || opP->mode == CONTROL
1337 || opP->mode == FPREG
1338 || opP->mode == IMMED
1339 || opP->mode == REGLST
1340 || (opP->mode != ABSL
1341 && (opP->reg == PC
1342 || opP->reg == ZPC)))
1343 losing++;
1344 break;
1345
1346 case '%':
1347 if (opP->mode == CONTROL
1348 || opP->mode == FPREG
1349 || opP->mode == REGLST
1350 || opP->mode == IMMED
1351 || (opP->mode != ABSL
1352 && (opP->reg == PC
1353 || opP->reg == ZPC)))
1354 losing++;
1355 break;
1356
1357 case '&':
1358 switch (opP->mode)
1359 {
1360 case DREG:
1361 case AREG:
1362 case FPREG:
1363 case CONTROL:
1364 case IMMED:
1365 case AINC:
1366 case ADEC:
1367 case REGLST:
1368 losing++;
1369 break;
1370 case ABSL:
1371 break;
1372 default:
1373 if (opP->reg == PC
1374 || opP->reg == ZPC)
1375 losing++;
1376 break;
1377 }
1378 break;
1379
1380 case '*':
1381 if (opP->mode == CONTROL
1382 || opP->mode == FPREG
1383 || opP->mode == REGLST)
1384 losing++;
1385 break;
1386
1387 case '+':
1388 if (opP->mode != AINC)
1389 losing++;
1390 break;
1391
1392 case '-':
1393 if (opP->mode != ADEC)
1394 losing++;
1395 break;
1396
1397 case '/':
1398 switch (opP->mode)
1399 {
1400 case AREG:
1401 case CONTROL:
1402 case FPREG:
1403 case AINC:
1404 case ADEC:
1405 case IMMED:
1406 case REGLST:
1407 losing++;
1408 break;
1409 default:
1410 break;
1411 }
1412 break;
1413
1414 case ';':
1415 switch (opP->mode)
1416 {
1417 case AREG:
1418 case CONTROL:
1419 case FPREG:
1420 case REGLST:
1421 losing++;
1422 break;
1423 default:
1424 break;
1425 }
1426 break;
1427
1428 case '?':
1429 switch (opP->mode)
1430 {
1431 case AREG:
1432 case CONTROL:
1433 case FPREG:
1434 case AINC:
1435 case ADEC:
1436 case IMMED:
1437 case REGLST:
1438 losing++;
1439 break;
1440 case ABSL:
1441 break;
1442 default:
1443 if (opP->reg == PC || opP->reg == ZPC)
1444 losing++;
1445 break;
1446 }
1447 break;
1448
1449 case '@':
1450 switch (opP->mode)
1451 {
1452 case AREG:
1453 case CONTROL:
1454 case FPREG:
1455 case IMMED:
1456 case REGLST:
1457 losing++;
1458 break;
1459 default:
1460 break;
1461 }
1462 break;
1463
1464 case '~': /* For now! (JF FOO is this right?) */
1465 switch (opP->mode)
1466 {
1467 case DREG:
1468 case AREG:
1469 case CONTROL:
1470 case FPREG:
1471 case IMMED:
1472 case REGLST:
1473 losing++;
1474 break;
1475 case ABSL:
1476 break;
1477 default:
1478 if (opP->reg == PC
1479 || opP->reg == ZPC)
1480 losing++;
1481 break;
1482 }
1483 break;
1484
1485 case '3':
1486 if (opP->mode != CONTROL
1487 || (opP->reg != TT0 && opP->reg != TT1))
1488 losing++;
1489 break;
1490
1491 case 'A':
1492 if (opP->mode != AREG)
1493 losing++;
1494 break;
1495
1496 case 'a':
1497 if (opP->mode != AINDR)
1498 ++losing;
1499 break;
1500
1501 case 'B': /* FOO */
1502 if (opP->mode != ABSL
1503 || (flag_long_jumps
1504 && strncmp (instring, "jbsr", 4) == 0))
1505 losing++;
1506 break;
1507
1508 case 'C':
1509 if (opP->mode != CONTROL || opP->reg != CCR)
1510 losing++;
1511 break;
1512
1513 case 'd':
1514 if (opP->mode != DISP
1515 || opP->reg < ADDR0
1516 || opP->reg > ADDR7)
1517 losing++;
1518 break;
1519
1520 case 'D':
1521 if (opP->mode != DREG)
1522 losing++;
1523 break;
1524
1525 case 'E':
1526 if (opP->reg != ACC)
1527 losing++;
1528 break;
1529
1530 case 'F':
1531 if (opP->mode != FPREG)
1532 losing++;
1533 break;
1534
1535 case 'G':
1536 if (opP->reg != MACSR)
1537 losing++;
1538 break;
1539
1540 case 'H':
1541 if (opP->reg != MASK)
1542 losing++;
1543 break;
1544
1545 case 'I':
1546 if (opP->mode != CONTROL
1547 || opP->reg < COP0
1548 || opP->reg > COP7)
1549 losing++;
1550 break;
1551
1552 case 'J':
1553 if (opP->mode != CONTROL
1554 || opP->reg < USP
1555 || opP->reg > last_movec_reg)
1556 losing++;
1557 else
1558 {
1559 const enum m68k_register *rp;
1560 for (rp = control_regs; *rp; rp++)
1561 if (*rp == opP->reg)
1562 break;
1563 if (*rp == 0)
1564 losing++;
1565 }
1566 break;
1567
1568 case 'k':
1569 if (opP->mode != IMMED)
1570 losing++;
1571 break;
1572
1573 case 'l':
1574 case 'L':
1575 if (opP->mode == DREG
1576 || opP->mode == AREG
1577 || opP->mode == FPREG)
1578 {
1579 if (s[1] == '8')
1580 losing++;
1581 else
1582 {
1583 switch (opP->mode)
1584 {
1585 case DREG:
1586 opP->mask = 1 << (opP->reg - DATA0);
1587 break;
1588 case AREG:
1589 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1590 break;
1591 case FPREG:
1592 opP->mask = 1 << (opP->reg - FP0 + 16);
1593 break;
1594 default:
1595 abort ();
1596 }
1597 opP->mode = REGLST;
1598 }
1599 }
1600 else if (opP->mode == CONTROL)
1601 {
1602 if (s[1] != '8')
1603 losing++;
1604 else
1605 {
1606 switch (opP->reg)
1607 {
1608 case FPI:
1609 opP->mask = 1 << 24;
1610 break;
1611 case FPS:
1612 opP->mask = 1 << 25;
1613 break;
1614 case FPC:
1615 opP->mask = 1 << 26;
1616 break;
1617 default:
1618 losing++;
1619 break;
1620 }
1621 opP->mode = REGLST;
1622 }
1623 }
1624 else if (opP->mode != REGLST)
1625 losing++;
1626 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1627 losing++;
1628 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1629 losing++;
1630 break;
1631
1632 case 'M':
1633 if (opP->mode != IMMED)
1634 losing++;
1635 else if (opP->disp.exp.X_op != O_constant
1636 || ! issbyte (opP->disp.exp.X_add_number))
1637 losing++;
1638 else if (! m68k_quick
1639 && instring[3] != 'q'
1640 && instring[4] != 'q')
1641 losing++;
1642 break;
1643
1644 case 'O':
1645 if (opP->mode != DREG
1646 && opP->mode != IMMED
1647 && opP->mode != ABSL)
1648 losing++;
1649 break;
1650
1651 case 'Q':
1652 if (opP->mode != IMMED)
1653 losing++;
1654 else if (opP->disp.exp.X_op != O_constant
1655 || opP->disp.exp.X_add_number < 1
1656 || opP->disp.exp.X_add_number > 8)
1657 losing++;
1658 else if (! m68k_quick
1659 && (strncmp (instring, "add", 3) == 0
1660 || strncmp (instring, "sub", 3) == 0)
1661 && instring[3] != 'q')
1662 losing++;
1663 break;
1664
1665 case 'R':
1666 if (opP->mode != DREG && opP->mode != AREG)
1667 losing++;
1668 break;
1669
1670 case 'r':
1671 if (opP->mode != AINDR
1672 && (opP->mode != BASE
1673 || (opP->reg != 0
1674 && opP->reg != ZADDR0)
1675 || opP->disp.exp.X_op != O_absent
1676 || ((opP->index.reg < DATA0
1677 || opP->index.reg > DATA7)
1678 && (opP->index.reg < ADDR0
1679 || opP->index.reg > ADDR7))
1680 || opP->index.size != SIZE_UNSPEC
1681 || opP->index.scale != 1))
1682 losing++;
1683 break;
1684
1685 case 's':
1686 if (opP->mode != CONTROL
1687 || ! (opP->reg == FPI
1688 || opP->reg == FPS
1689 || opP->reg == FPC))
1690 losing++;
1691 break;
1692
1693 case 'S':
1694 if (opP->mode != CONTROL || opP->reg != SR)
1695 losing++;
1696 break;
1697
1698 case 't':
1699 if (opP->mode != IMMED)
1700 losing++;
1701 else if (opP->disp.exp.X_op != O_constant
1702 || opP->disp.exp.X_add_number < 0
1703 || opP->disp.exp.X_add_number > 7)
1704 losing++;
1705 break;
1706
1707 case 'U':
1708 if (opP->mode != CONTROL || opP->reg != USP)
1709 losing++;
1710 break;
1711
1712 /* JF these are out of order. We could put them
1713 in order if we were willing to put up with
1714 bunches of #ifdef m68851s in the code.
1715
1716 Don't forget that you need these operands
1717 to use 68030 MMU instructions. */
1718#ifndef NO_68851
1719 /* Memory addressing mode used by pflushr */
1720 case '|':
1721 if (opP->mode == CONTROL
1722 || opP->mode == FPREG
1723 || opP->mode == DREG
1724 || opP->mode == AREG
1725 || opP->mode == REGLST)
1726 losing++;
1727 /* We should accept immediate operands, but they
1728 supposedly have to be quad word, and we don't
1729 handle that. I would like to see what a Motorola
1730 assembler does before doing something here. */
1731 if (opP->mode == IMMED)
1732 losing++;
1733 break;
1734
1735 case 'f':
1736 if (opP->mode != CONTROL
1737 || (opP->reg != SFC && opP->reg != DFC))
1738 losing++;
1739 break;
1740
1741 case '0':
1742 if (opP->mode != CONTROL || opP->reg != TC)
1743 losing++;
1744 break;
1745
1746 case '1':
1747 if (opP->mode != CONTROL || opP->reg != AC)
1748 losing++;
1749 break;
1750
1751 case '2':
1752 if (opP->mode != CONTROL
1753 || (opP->reg != CAL
1754 && opP->reg != VAL
1755 && opP->reg != SCC))
1756 losing++;
1757 break;
1758
1759 case 'V':
1760 if (opP->mode != CONTROL
1761 || opP->reg != VAL)
1762 losing++;
1763 break;
1764
1765 case 'W':
1766 if (opP->mode != CONTROL
1767 || (opP->reg != DRP
1768 && opP->reg != SRP
1769 && opP->reg != CRP))
1770 losing++;
1771 break;
1772
1773 case 'X':
1774 if (opP->mode != CONTROL
1775 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1776 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1777 losing++;
1778 break;
1779
1780 case 'Y':
1781 if (opP->mode != CONTROL || opP->reg != PSR)
1782 losing++;
1783 break;
1784
1785 case 'Z':
1786 if (opP->mode != CONTROL || opP->reg != PCSR)
1787 losing++;
1788 break;
1789#endif
1790 case 'c':
1791 if (opP->mode != CONTROL
1792 || (opP->reg != NC
1793 && opP->reg != IC
1794 && opP->reg != DC
1795 && opP->reg != BC))
1796 {
1797 losing++;
1798 } /* not a cache specifier. */
1799 break;
1800
1801 case '_':
1802 if (opP->mode != ABSL)
1803 ++losing;
1804 break;
1805
1806 case 'u':
1807 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1808 losing++;
1809 /* FIXME: kludge instead of fixing parser:
1810 upper/lower registers are *not* CONTROL
1811 registers, but ordinary ones. */
1812 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1813 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1814 opP->mode = DREG;
1815 else
1816 opP->mode = AREG;
1817 break;
1818
1819 default:
1820 abort ();
1821 } /* switch on type of operand */
1822
1823 if (losing)
1824 break;
1825 } /* for each operand */
1826 } /* if immediately wrong */
1827
1828 if (!losing)
1829 {
1830 break;
1831 } /* got it. */
1832
1833 opcode = opcode->m_next;
1834
1835 if (!opcode)
1836 {
1837 if (ok_arch
1838 && !(ok_arch & current_architecture))
1839 {
1840 char buf[200], *cp;
1841
1842 strcpy (buf,
1843 _("invalid instruction for this architecture; needs "));
1844 cp = buf + strlen (buf);
1845 switch (ok_arch)
1846 {
1847 case mfloat:
1848 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1849 break;
1850 case mmmu:
1851 strcpy (cp, _("mmu (68030 or 68851)"));
1852 break;
1853 case m68020up:
1854 strcpy (cp, _("68020 or higher"));
1855 break;
1856 case m68000up:
1857 strcpy (cp, _("68000 or higher"));
1858 break;
1859 case m68010up:
1860 strcpy (cp, _("68010 or higher"));
1861 break;
1862 default:
1863 {
1864 int got_one = 0, idx;
1865 for (idx = 0;
1866 idx < (int) (sizeof (archs) / sizeof (archs[0]));
1867 idx++)
1868 {
1869 if ((archs[idx].arch & ok_arch)
1870 && ! archs[idx].alias)
1871 {
1872 if (got_one)
1873 {
1874 strcpy (cp, " or ");
1875 cp += strlen (cp);
1876 }
1877 got_one = 1;
1878 strcpy (cp, archs[idx].name);
1879 cp += strlen (cp);
1880 }
1881 }
1882 }
1883 }
1884 cp = xmalloc (strlen (buf) + 1);
1885 strcpy (cp, buf);
1886 the_ins.error = cp;
1887 }
1888 else
1889 the_ins.error = _("operands mismatch");
1890 return;
1891 } /* Fell off the end */
1892
1893 losing = 0;
1894 }
1895
1896 /* now assemble it */
1897
1898 the_ins.args = opcode->m_operands;
1899 the_ins.numargs = opcode->m_opnum;
1900 the_ins.numo = opcode->m_codenum;
1901 the_ins.opcode[0] = getone (opcode);
1902 the_ins.opcode[1] = gettwo (opcode);
1903
1904 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1905 {
1906 /* This switch is a doozy.
1907 Watch the first step; its a big one! */
1908 switch (s[0])
1909 {
1910
1911 case '*':
1912 case '~':
1913 case '%':
1914 case ';':
1915 case '@':
1916 case '!':
1917 case '&':
1918 case '$':
1919 case '?':
1920 case '/':
1921 case '<':
1922 case '>':
1923 case 'm':
1924 case 'n':
1925 case 'o':
1926 case 'p':
1927 case 'q':
1928 case 'v':
1929#ifndef NO_68851
1930 case '|':
1931#endif
1932 switch (opP->mode)
1933 {
1934 case IMMED:
1935 tmpreg = 0x3c; /* 7.4 */
1936 if (strchr ("bwl", s[1]))
1937 nextword = get_num (&opP->disp, 80);
1938 else
1939 nextword = get_num (&opP->disp, 0);
1940 if (isvar (&opP->disp))
1941 add_fix (s[1], &opP->disp, 0, 0);
1942 switch (s[1])
1943 {
1944 case 'b':
1945 if (!isbyte (nextword))
1946 opP->error = _("operand out of range");
1947 addword (nextword);
1948 baseo = 0;
1949 break;
1950 case 'w':
1951 if (!isword (nextword))
1952 opP->error = _("operand out of range");
1953 addword (nextword);
1954 baseo = 0;
1955 break;
1956 case 'W':
1957 if (!issword (nextword))
1958 opP->error = _("operand out of range");
1959 addword (nextword);
1960 baseo = 0;
1961 break;
1962 case 'l':
1963 addword (nextword >> 16);
1964 addword (nextword);
1965 baseo = 0;
1966 break;
1967
1968 case 'f':
1969 baseo = 2;
1970 outro = 8;
1971 break;
1972 case 'F':
1973 baseo = 4;
1974 outro = 11;
1975 break;
1976 case 'x':
1977 baseo = 6;
1978 outro = 15;
1979 break;
1980 case 'p':
1981 baseo = 6;
1982 outro = -1;
1983 break;
1984 default:
1985 abort ();
1986 }
1987 if (!baseo)
1988 break;
1989
1990 /* We gotta put out some float */
1991 if (op (&opP->disp) != O_big)
1992 {
1993 valueT val;
1994 int gencnt;
1995
1996 /* Can other cases happen here? */
1997 if (op (&opP->disp) != O_constant)
1998 abort ();
1999
2000 val = (valueT) offs (&opP->disp);
2001 gencnt = 0;
2002 do
2003 {
2004 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2005 val >>= LITTLENUM_NUMBER_OF_BITS;
2006 ++gencnt;
2007 }
2008 while (val != 0);
2009 offs (&opP->disp) = gencnt;
2010 }
2011 if (offs (&opP->disp) > 0)
2012 {
2013 if (offs (&opP->disp) > baseo)
2014 {
2015 as_warn (_("Bignum too big for %c format; truncated"),
2016 s[1]);
2017 offs (&opP->disp) = baseo;
2018 }
2019 baseo -= offs (&opP->disp);
2020 while (baseo--)
2021 addword (0);
2022 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2023 offs (&opP->disp)--;
2024 --wordp)
2025 addword (*wordp);
2026 break;
2027 }
2028 gen_to_words (words, baseo, (long) outro);
2029 for (wordp = words; baseo--; wordp++)
2030 addword (*wordp);
2031 break;
2032 case DREG:
2033 tmpreg = opP->reg - DATA; /* 0.dreg */
2034 break;
2035 case AREG:
2036 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2037 break;
2038 case AINDR:
2039 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2040 break;
2041 case ADEC:
2042 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2043 break;
2044 case AINC:
2045 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2046 break;
2047 case DISP:
2048
2049 nextword = get_num (&opP->disp, 80);
2050
2051 if (opP->reg == PC
2052 && ! isvar (&opP->disp)
2053 && m68k_abspcadd)
2054 {
2055 opP->disp.exp.X_op = O_symbol;
2056#ifndef BFD_ASSEMBLER
2057 opP->disp.exp.X_add_symbol = &abs_symbol;
2058#else
2059 opP->disp.exp.X_add_symbol =
2060 section_symbol (absolute_section);
2061#endif
2062 }
2063
2064 /* Force into index mode. Hope this works */
2065
2066 /* We do the first bit for 32-bit displacements, and the
2067 second bit for 16 bit ones. It is possible that we
2068 should make the default be WORD instead of LONG, but
2069 I think that'd break GCC, so we put up with a little
2070 inefficiency for the sake of working output. */
2071
2072 if (!issword (nextword)
2073 || (isvar (&opP->disp)
2074 && ((opP->disp.size == SIZE_UNSPEC
2075 && flag_short_refs == 0
2076 && cpu_of_arch (current_architecture) >= m68020
2077 && ! arch_coldfire_p (current_architecture))
2078 || opP->disp.size == SIZE_LONG)))
2079 {
2080 if (cpu_of_arch (current_architecture) < m68020
2081 || arch_coldfire_p (current_architecture))
2082 opP->error =
2083 _("displacement too large for this architecture; needs 68020 or higher");
2084 if (opP->reg == PC)
2085 tmpreg = 0x3B; /* 7.3 */
2086 else
2087 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2088 if (isvar (&opP->disp))
2089 {
2090 if (opP->reg == PC)
2091 {
2092 if (opP->disp.size == SIZE_LONG
2093#ifdef OBJ_ELF
2094 /* If the displacement needs pic
2095 relocation it cannot be relaxed. */
2096 || opP->disp.pic_reloc != pic_none
2097#endif
2098 )
2099 {
2100 addword (0x0170);
2101 add_fix ('l', &opP->disp, 1, 2);
2102 }
2103 else
2104 {
2105 add_frag (adds (&opP->disp),
2106 offs (&opP->disp),
2107 TAB (PCREL1632, SZ_UNDEF));
2108 break;
2109 }
2110 }
2111 else
2112 {
2113 addword (0x0170);
2114 add_fix ('l', &opP->disp, 0, 0);
2115 }
2116 }
2117 else
2118 addword (0x0170);
2119 addword (nextword >> 16);
2120 }
2121 else
2122 {
2123 if (opP->reg == PC)
2124 tmpreg = 0x3A; /* 7.2 */
2125 else
2126 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2127
2128 if (isvar (&opP->disp))
2129 {
2130 if (opP->reg == PC)
2131 {
2132 add_fix ('w', &opP->disp, 1, 0);
2133 }
2134 else
2135 add_fix ('w', &opP->disp, 0, 0);
2136 }
2137 }
2138 addword (nextword);
2139 break;
2140
2141 case POST:
2142 case PRE:
2143 case BASE:
2144 nextword = 0;
2145 baseo = get_num (&opP->disp, 80);
2146 if (opP->mode == POST || opP->mode == PRE)
2147 outro = get_num (&opP->odisp, 80);
2148 /* Figure out the `addressing mode'.
2149 Also turn on the BASE_DISABLE bit, if needed. */
2150 if (opP->reg == PC || opP->reg == ZPC)
2151 {
2152 tmpreg = 0x3b; /* 7.3 */
2153 if (opP->reg == ZPC)
2154 nextword |= 0x80;
2155 }
2156 else if (opP->reg == 0)
2157 {
2158 nextword |= 0x80;
2159 tmpreg = 0x30; /* 6.garbage */
2160 }
2161 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2162 {
2163 nextword |= 0x80;
2164 tmpreg = 0x30 + opP->reg - ZADDR0;
2165 }
2166 else
2167 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2168
2169 siz1 = opP->disp.size;
2170 if (opP->mode == POST || opP->mode == PRE)
2171 siz2 = opP->odisp.size;
2172 else
2173 siz2 = SIZE_UNSPEC;
2174
2175 /* Index register stuff */
2176 if (opP->index.reg != 0
2177 && opP->index.reg >= DATA
2178 && opP->index.reg <= ADDR7)
2179 {
2180 nextword |= (opP->index.reg - DATA) << 12;
2181
2182 if (opP->index.size == SIZE_LONG
2183 || (opP->index.size == SIZE_UNSPEC
2184 && m68k_index_width_default == SIZE_LONG))
2185 nextword |= 0x800;
2186
2187 if ((opP->index.scale != 1
2188 && cpu_of_arch (current_architecture) < m68020)
2189 || (opP->index.scale == 8
2190 && arch_coldfire_p (current_architecture)))
2191 {
2192 opP->error =
2193 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2194 }
2195
2196 if (arch_coldfire_p (current_architecture)
2197 && opP->index.size == SIZE_WORD)
2198 opP->error = _("invalid index size for coldfire");
2199
2200 switch (opP->index.scale)
2201 {
2202 case 1:
2203 break;
2204 case 2:
2205 nextword |= 0x200;
2206 break;
2207 case 4:
2208 nextword |= 0x400;
2209 break;
2210 case 8:
2211 nextword |= 0x600;
2212 break;
2213 default:
2214 abort ();
2215 }
2216 /* IF its simple,
2217 GET US OUT OF HERE! */
2218
2219 /* Must be INDEX, with an index register. Address
2220 register cannot be ZERO-PC, and either :b was
2221 forced, or we know it will fit. For a 68000 or
2222 68010, force this mode anyways, because the
2223 larger modes aren't supported. */
2224 if (opP->mode == BASE
2225 && ((opP->reg >= ADDR0
2226 && opP->reg <= ADDR7)
2227 || opP->reg == PC))
2228 {
2229 if (siz1 == SIZE_BYTE
2230 || cpu_of_arch (current_architecture) < m68020
2231 || arch_coldfire_p (current_architecture)
2232 || (siz1 == SIZE_UNSPEC
2233 && ! isvar (&opP->disp)
2234 && issbyte (baseo)))
2235 {
2236 nextword += baseo & 0xff;
2237 addword (nextword);
2238 if (isvar (&opP->disp))
2239 {
2240 /* Do a byte relocation. If it doesn't
2241 fit (possible on m68000) let the
2242 fixup processing complain later. */
2243 if (opP->reg == PC)
2244 add_fix ('B', &opP->disp, 1, 1);
2245 else
2246 add_fix ('B', &opP->disp, 0, 0);
2247 }
2248 else if (siz1 != SIZE_BYTE)
2249 {
2250 if (siz1 != SIZE_UNSPEC)
2251 as_warn (_("Forcing byte displacement"));
2252 if (! issbyte (baseo))
2253 opP->error = _("byte displacement out of range");
2254 }
2255
2256 break;
2257 }
2258 else if (siz1 == SIZE_UNSPEC
2259 && opP->reg == PC
2260 && isvar (&opP->disp)
2261 && subs (&opP->disp) == NULL
2262#ifdef OBJ_ELF
2263 /* If the displacement needs pic
2264 relocation it cannot be relaxed. */
2265 && opP->disp.pic_reloc == pic_none
2266#endif
2267 )
2268 {
2269 /* The code in md_convert_frag_1 needs to be
2270 able to adjust nextword. Call frag_grow
2271 to ensure that we have enough space in
2272 the frag obstack to make all the bytes
2273 contiguous. */
2274 frag_grow (14);
2275 nextword += baseo & 0xff;
2276 addword (nextword);
2277 add_frag (adds (&opP->disp), offs (&opP->disp),
2278 TAB (PCINDEX, SZ_UNDEF));
2279
2280 break;
2281 }
2282 }
2283 }
2284 else
2285 {
2286 nextword |= 0x40; /* No index reg */
2287 if (opP->index.reg >= ZDATA0
2288 && opP->index.reg <= ZDATA7)
2289 nextword |= (opP->index.reg - ZDATA0) << 12;
2290 else if (opP->index.reg >= ZADDR0
2291 || opP->index.reg <= ZADDR7)
2292 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2293 }
2294
2295 /* It isn't simple. */
2296
2297 if (cpu_of_arch (current_architecture) < m68020
2298 || arch_coldfire_p (current_architecture))
2299 opP->error =
2300 _("invalid operand mode for this architecture; needs 68020 or higher");
2301
2302 nextword |= 0x100;
2303 /* If the guy specified a width, we assume that it is
2304 wide enough. Maybe it isn't. If so, we lose. */
2305 switch (siz1)
2306 {
2307 case SIZE_UNSPEC:
2308 if (isvar (&opP->disp)
2309 ? m68k_rel32
2310 : ! issword (baseo))
2311 {
2312 siz1 = SIZE_LONG;
2313 nextword |= 0x30;
2314 }
2315 else if (! isvar (&opP->disp) && baseo == 0)
2316 nextword |= 0x10;
2317 else
2318 {
2319 nextword |= 0x20;
2320 siz1 = SIZE_WORD;
2321 }
2322 break;
2323 case SIZE_BYTE:
2324 as_warn (_(":b not permitted; defaulting to :w"));
2325 /* Fall through. */
2326 case SIZE_WORD:
2327 nextword |= 0x20;
2328 break;
2329 case SIZE_LONG:
2330 nextword |= 0x30;
2331 break;
2332 }
2333
2334 /* Figure out innner displacement stuff */
2335 if (opP->mode == POST || opP->mode == PRE)
2336 {
2337 if (cpu_of_arch (current_architecture) & cpu32)
2338 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2339 switch (siz2)
2340 {
2341 case SIZE_UNSPEC:
2342 if (isvar (&opP->odisp)
2343 ? m68k_rel32
2344 : ! issword (outro))
2345 {
2346 siz2 = SIZE_LONG;
2347 nextword |= 0x3;
2348 }
2349 else if (! isvar (&opP->odisp) && outro == 0)
2350 nextword |= 0x1;
2351 else
2352 {
2353 nextword |= 0x2;
2354 siz2 = SIZE_WORD;
2355 }
2356 break;
2357 case 1:
2358 as_warn (_(":b not permitted; defaulting to :w"));
2359 /* Fall through. */
2360 case 2:
2361 nextword |= 0x2;
2362 break;
2363 case 3:
2364 nextword |= 0x3;
2365 break;
2366 }
2367 if (opP->mode == POST
2368 && (nextword & 0x40) == 0)
2369 nextword |= 0x04;
2370 }
2371 addword (nextword);
2372
2373 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2374 {
2375 if (opP->reg == PC || opP->reg == ZPC)
2376 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2377 else
2378 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2379 }
2380 if (siz1 == SIZE_LONG)
2381 addword (baseo >> 16);
2382 if (siz1 != SIZE_UNSPEC)
2383 addword (baseo);
2384
2385 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2386 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2387 if (siz2 == SIZE_LONG)
2388 addword (outro >> 16);
2389 if (siz2 != SIZE_UNSPEC)
2390 addword (outro);
2391
2392 break;
2393
2394 case ABSL:
2395 nextword = get_num (&opP->disp, 80);
2396 switch (opP->disp.size)
2397 {
2398 default:
2399 abort ();
2400 case SIZE_UNSPEC:
2401 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2402 {
2403 tmpreg = 0x38; /* 7.0 */
2404 addword (nextword);
2405 break;
2406 }
2407 if (isvar (&opP->disp)
2408 && !subs (&opP->disp)
2409 && adds (&opP->disp)
2410#ifdef OBJ_ELF
2411 /* If the displacement needs pic relocation it
2412 cannot be relaxed. */
2413 && opP->disp.pic_reloc == pic_none
2414#endif
2415 && !flag_long_jumps
2416 && !strchr ("~%&$?", s[0]))
2417 {
2418 tmpreg = 0x3A; /* 7.2 */
2419 add_frag (adds (&opP->disp),
2420 offs (&opP->disp),
2421 TAB (ABSTOPCREL, SZ_UNDEF));
2422 break;
2423 }
2424 /* Fall through into long */
2425 case SIZE_LONG:
2426 if (isvar (&opP->disp))
2427 add_fix ('l', &opP->disp, 0, 0);
2428
2429 tmpreg = 0x39;/* 7.1 mode */
2430 addword (nextword >> 16);
2431 addword (nextword);
2432 break;
2433
2434 case SIZE_BYTE:
2435 as_bad (_("unsupported byte value; use a different suffix"));
2436 /* Fall through. */
2437 case SIZE_WORD: /* Word */
2438 if (isvar (&opP->disp))
2439 add_fix ('w', &opP->disp, 0, 0);
2440
2441 tmpreg = 0x38;/* 7.0 mode */
2442 addword (nextword);
2443 break;
2444 }
2445 break;
2446 case CONTROL:
2447 case FPREG:
2448 default:
2449 as_bad (_("unknown/incorrect operand"));
2450 /* abort (); */
2451 }
2452 install_gen_operand (s[1], tmpreg);
2453 break;
2454
2455 case '#':
2456 case '^':
2457 switch (s[1])
2458 { /* JF: I hate floating point! */
2459 case 'j':
2460 tmpreg = 70;
2461 break;
2462 case '8':
2463 tmpreg = 20;
2464 break;
2465 case 'C':
2466 tmpreg = 50;
2467 break;
2468 case '3':
2469 default:
2470 tmpreg = 80;
2471 break;
2472 }
2473 tmpreg = get_num (&opP->disp, tmpreg);
2474 if (isvar (&opP->disp))
2475 add_fix (s[1], &opP->disp, 0, 0);
2476 switch (s[1])
2477 {
2478 case 'b': /* Danger: These do no check for
2479 certain types of overflow.
2480 user beware! */
2481 if (!isbyte (tmpreg))
2482 opP->error = _("out of range");
2483 insop (tmpreg, opcode);
2484 if (isvar (&opP->disp))
2485 the_ins.reloc[the_ins.nrel - 1].n =
2486 (opcode->m_codenum) * 2 + 1;
2487 break;
2488 case 'B':
2489 if (!issbyte (tmpreg))
2490 opP->error = _("out of range");
2491 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2492 if (isvar (&opP->disp))
2493 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2494 break;
2495 case 'w':
2496 if (!isword (tmpreg))
2497 opP->error = _("out of range");
2498 insop (tmpreg, opcode);
2499 if (isvar (&opP->disp))
2500 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2501 break;
2502 case 'W':
2503 if (!issword (tmpreg))
2504 opP->error = _("out of range");
2505 insop (tmpreg, opcode);
2506 if (isvar (&opP->disp))
2507 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2508 break;
2509 case 'l':
2510 /* Because of the way insop works, we put these two out
2511 backwards. */
2512 insop (tmpreg, opcode);
2513 insop (tmpreg >> 16, opcode);
2514 if (isvar (&opP->disp))
2515 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2516 break;
2517 case '3':
2518 tmpreg &= 0xFF;
2519 case '8':
2520 case 'C':
2521 case 'j':
2522 install_operand (s[1], tmpreg);
2523 break;
2524 default:
2525 abort ();
2526 }
2527 break;
2528
2529 case '+':
2530 case '-':
2531 case 'A':
2532 case 'a':
2533 install_operand (s[1], opP->reg - ADDR);
2534 break;
2535
2536 case 'B':
2537 tmpreg = get_num (&opP->disp, 80);
2538 switch (s[1])
2539 {
2540 case 'B':
2541 add_fix ('B', &opP->disp, 1, -1);
2542 break;
2543 case 'W':
2544 add_fix ('w', &opP->disp, 1, 0);
2545 addword (0);
2546 break;
2547 case 'L':
2548 long_branch:
2549 if (! HAVE_LONG_BRANCH (current_architecture))
2550 as_warn (_("Can't use long branches on 68000/68010/5200"));
2551 the_ins.opcode[0] |= 0xff;
2552 add_fix ('l', &opP->disp, 1, 0);
2553 addword (0);
2554 addword (0);
2555 break;
2556 case 'g':
2557 if (subs (&opP->disp)) /* We can't relax it */
2558 goto long_branch;
2559
2560#ifdef OBJ_ELF
2561 /* If the displacement needs pic relocation it cannot be
2562 relaxed. */
2563 if (opP->disp.pic_reloc != pic_none)
2564 goto long_branch;
2565#endif
2566 /* This could either be a symbol, or an absolute
2567 address. If it's an absolute address, turn it into
2568 an absolute jump right here and keep it out of the
2569 relaxer. */
2570 if (adds (&opP->disp) == 0)
2571 {
2572 if (the_ins.opcode[0] == 0x6000) /* jbra */
2573 the_ins.opcode[0] = 0x4EF9;
2574 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2575 the_ins.opcode[0] = 0x4EB9;
2576 else /* jCC */
2577 {
2578 the_ins.opcode[0] ^= 0x0100;
2579 the_ins.opcode[0] |= 0x0006;
2580 addword (0x4EF9);
2581 }
2582 add_fix ('l', &opP->disp, 0, 0);
2583 addword (0);
2584 addword (0);
2585 break;
2586 }
2587
2588 /* Now we know it's going into the relaxer. Now figure
2589 out which mode. We try in this order of preference:
2590 long branch, absolute jump, byte/word branches only. */
2591 if (HAVE_LONG_BRANCH (current_architecture))
2592 add_frag (adds (&opP->disp), offs (&opP->disp),
2593 TAB (BRANCHBWL, SZ_UNDEF));
2594 else if (! flag_keep_pcrel)
2595 {
2596 if ((the_ins.opcode[0] == 0x6000)
2597 || (the_ins.opcode[0] == 0x6100))
2598 add_frag (adds (&opP->disp), offs (&opP->disp),
2599 TAB (BRABSJUNC, SZ_UNDEF));
2600 else
2601 add_frag (adds (&opP->disp), offs (&opP->disp),
2602 TAB (BRABSJCOND, SZ_UNDEF));
2603 }
2604 else
2605 add_frag (adds (&opP->disp), offs (&opP->disp),
2606 TAB (BRANCHBW, SZ_UNDEF));
2607 break;
2608 case 'w':
2609 if (isvar (&opP->disp))
2610 {
2611 /* Check for DBcc instructions. We can relax them,
2612 but only if we have long branches and/or absolute
2613 jumps. */
2614 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2615 && (HAVE_LONG_BRANCH (current_architecture)
2616 || (! flag_keep_pcrel)))
2617 {
2618 if (HAVE_LONG_BRANCH (current_architecture))
2619 add_frag (adds (&opP->disp), offs (&opP->disp),
2620 TAB (DBCCLBR, SZ_UNDEF));
2621 else
2622 add_frag (adds (&opP->disp), offs (&opP->disp),
2623 TAB (DBCCABSJ, SZ_UNDEF));
2624 break;
2625 }
2626 add_fix ('w', &opP->disp, 1, 0);
2627 }
2628 addword (0);
2629 break;
2630 case 'C': /* Fixed size LONG coproc branches */
2631 add_fix ('l', &opP->disp, 1, 0);
2632 addword (0);
2633 addword (0);
2634 break;
2635 case 'c': /* Var size Coprocesssor branches */
2636 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2637 {
2638 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2639 add_fix ('l', &opP->disp, 1, 0);
2640 addword (0);
2641 addword (0);
2642 }
2643 else
2644 add_frag (adds (&opP->disp), offs (&opP->disp),
2645 TAB (FBRANCH, SZ_UNDEF));
2646 break;
2647 default:
2648 abort ();
2649 }
2650 break;
2651
2652 case 'C': /* Ignore it */
2653 break;
2654
2655 case 'd': /* JF this is a kludge */
2656 install_operand ('s', opP->reg - ADDR);
2657 tmpreg = get_num (&opP->disp, 80);
2658 if (!issword (tmpreg))
2659 {
2660 as_warn (_("Expression out of range, using 0"));
2661 tmpreg = 0;
2662 }
2663 addword (tmpreg);
2664 break;
2665
2666 case 'D':
2667 install_operand (s[1], opP->reg - DATA);
2668 break;
2669
2670 case 'E': /* Ignore it */
2671 break;
2672
2673 case 'F':
2674 install_operand (s[1], opP->reg - FP0);
2675 break;
2676
2677 case 'G': /* Ignore it */
2678 case 'H':
2679 break;
2680
2681 case 'I':
2682 tmpreg = opP->reg - COP0;
2683 install_operand (s[1], tmpreg);
2684 break;
2685
2686 case 'J': /* JF foo */
2687 switch (opP->reg)
2688 {
2689 case SFC:
2690 tmpreg = 0x000;
2691 break;
2692 case DFC:
2693 tmpreg = 0x001;
2694 break;
2695 case CACR:
2696 tmpreg = 0x002;
2697 break;
2698 case TC:
2699 tmpreg = 0x003;
2700 break;
2701 case ITT0:
2702 tmpreg = 0x004;
2703 break;
2704 case ITT1:
2705 tmpreg = 0x005;
2706 break;
2707 case DTT0:
2708 tmpreg = 0x006;
2709 break;
2710 case DTT1:
2711 tmpreg = 0x007;
2712 break;
2713 case BUSCR:
2714 tmpreg = 0x008;
2715 break;
2716
2717 case USP:
2718 tmpreg = 0x800;
2719 break;
2720 case VBR:
2721 tmpreg = 0x801;
2722 break;
2723 case CAAR:
2724 tmpreg = 0x802;
2725 break;
2726 case MSP:
2727 tmpreg = 0x803;
2728 break;
2729 case ISP:
2730 tmpreg = 0x804;
2731 break;
2732 case MMUSR:
2733 tmpreg = 0x805;
2734 break;
2735 case URP:
2736 tmpreg = 0x806;
2737 break;
2738 case SRP:
2739 tmpreg = 0x807;
2740 break;
2741 case PCR:
2742 tmpreg = 0x808;
2743 break;
2744 case ROMBAR:
2745 tmpreg = 0xC00;
2746 break;
2747 case RAMBAR0:
2748 tmpreg = 0xC04;
2749 break;
2750 case RAMBAR1:
2751 tmpreg = 0xC05;
2752 break;
2753 case MBAR:
2754 tmpreg = 0xC0F;
2755 break;
2756 default:
2757 abort ();
2758 }
2759 install_operand (s[1], tmpreg);
2760 break;
2761
2762 case 'k':
2763 tmpreg = get_num (&opP->disp, 55);
2764 install_operand (s[1], tmpreg & 0x7f);
2765 break;
2766
2767 case 'l':
2768 tmpreg = opP->mask;
2769 if (s[1] == 'w')
2770 {
2771 if (tmpreg & 0x7FF0000)
2772 as_bad (_("Floating point register in register list"));
2773 insop (reverse_16_bits (tmpreg), opcode);
2774 }
2775 else
2776 {
2777 if (tmpreg & 0x700FFFF)
2778 as_bad (_("Wrong register in floating-point reglist"));
2779 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2780 }
2781 break;
2782
2783 case 'L':
2784 tmpreg = opP->mask;
2785 if (s[1] == 'w')
2786 {
2787 if (tmpreg & 0x7FF0000)
2788 as_bad (_("Floating point register in register list"));
2789 insop (tmpreg, opcode);
2790 }
2791 else if (s[1] == '8')
2792 {
2793 if (tmpreg & 0x0FFFFFF)
2794 as_bad (_("incorrect register in reglist"));
2795 install_operand (s[1], tmpreg >> 24);
2796 }
2797 else
2798 {
2799 if (tmpreg & 0x700FFFF)
2800 as_bad (_("wrong register in floating-point reglist"));
2801 else
2802 install_operand (s[1], tmpreg >> 16);
2803 }
2804 break;
2805
2806 case 'M':
2807 install_operand (s[1], get_num (&opP->disp, 60));
2808 break;
2809
2810 case 'O':
2811 tmpreg = ((opP->mode == DREG)
2812 ? 0x20 + (int) (opP->reg - DATA)
2813 : (get_num (&opP->disp, 40) & 0x1F));
2814 install_operand (s[1], tmpreg);
2815 break;
2816
2817 case 'Q':
2818 tmpreg = get_num (&opP->disp, 10);
2819 if (tmpreg == 8)
2820 tmpreg = 0;
2821 install_operand (s[1], tmpreg);
2822 break;
2823
2824 case 'R':
2825 /* This depends on the fact that ADDR registers are eight
2826 more than their corresponding DATA regs, so the result
2827 will have the ADDR_REG bit set */
2828 install_operand (s[1], opP->reg - DATA);
2829 break;
2830
2831 case 'r':
2832 if (opP->mode == AINDR)
2833 install_operand (s[1], opP->reg - DATA);
2834 else
2835 install_operand (s[1], opP->index.reg - DATA);
2836 break;
2837
2838 case 's':
2839 if (opP->reg == FPI)
2840 tmpreg = 0x1;
2841 else if (opP->reg == FPS)
2842 tmpreg = 0x2;
2843 else if (opP->reg == FPC)
2844 tmpreg = 0x4;
2845 else
2846 abort ();
2847 install_operand (s[1], tmpreg);
2848 break;
2849
2850 case 'S': /* Ignore it */
2851 break;
2852
2853 case 'T':
2854 install_operand (s[1], get_num (&opP->disp, 30));
2855 break;
2856
2857 case 'U': /* Ignore it */
2858 break;
2859
2860 case 'c':
2861 switch (opP->reg)
2862 {
2863 case NC:
2864 tmpreg = 0;
2865 break;
2866 case DC:
2867 tmpreg = 1;
2868 break;
2869 case IC:
2870 tmpreg = 2;
2871 break;
2872 case BC:
2873 tmpreg = 3;
2874 break;
2875 default:
2876 as_fatal (_("failed sanity check"));
2877 } /* switch on cache token */
2878 install_operand (s[1], tmpreg);
2879 break;
2880#ifndef NO_68851
2881 /* JF: These are out of order, I fear. */
2882 case 'f':
2883 switch (opP->reg)
2884 {
2885 case SFC:
2886 tmpreg = 0;
2887 break;
2888 case DFC:
2889 tmpreg = 1;
2890 break;
2891 default:
2892 abort ();
2893 }
2894 install_operand (s[1], tmpreg);
2895 break;
2896
2897 case '0':
2898 case '1':
2899 case '2':
2900 switch (opP->reg)
2901 {
2902 case TC:
2903 tmpreg = 0;
2904 break;
2905 case CAL:
2906 tmpreg = 4;
2907 break;
2908 case VAL:
2909 tmpreg = 5;
2910 break;
2911 case SCC:
2912 tmpreg = 6;
2913 break;
2914 case AC:
2915 tmpreg = 7;
2916 break;
2917 default:
2918 abort ();
2919 }
2920 install_operand (s[1], tmpreg);
2921 break;
2922
2923 case 'V':
2924 if (opP->reg == VAL)
2925 break;
2926 abort ();
2927
2928 case 'W':
2929 switch (opP->reg)
2930 {
2931 case DRP:
2932 tmpreg = 1;
2933 break;
2934 case SRP:
2935 tmpreg = 2;
2936 break;
2937 case CRP:
2938 tmpreg = 3;
2939 break;
2940 default:
2941 abort ();
2942 }
2943 install_operand (s[1], tmpreg);
2944 break;
2945
2946 case 'X':
2947 switch (opP->reg)
2948 {
2949 case BAD:
2950 case BAD + 1:
2951 case BAD + 2:
2952 case BAD + 3:
2953 case BAD + 4:
2954 case BAD + 5:
2955 case BAD + 6:
2956 case BAD + 7:
2957 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2958 break;
2959
2960 case BAC:
2961 case BAC + 1:
2962 case BAC + 2:
2963 case BAC + 3:
2964 case BAC + 4:
2965 case BAC + 5:
2966 case BAC + 6:
2967 case BAC + 7:
2968 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2969 break;
2970
2971 default:
2972 abort ();
2973 }
2974 install_operand (s[1], tmpreg);
2975 break;
2976 case 'Y':
2977 know (opP->reg == PSR);
2978 break;
2979 case 'Z':
2980 know (opP->reg == PCSR);
2981 break;
2982#endif /* m68851 */
2983 case '3':
2984 switch (opP->reg)
2985 {
2986 case TT0:
2987 tmpreg = 2;
2988 break;
2989 case TT1:
2990 tmpreg = 3;
2991 break;
2992 default:
2993 abort ();
2994 }
2995 install_operand (s[1], tmpreg);
2996 break;
2997 case 't':
2998 tmpreg = get_num (&opP->disp, 20);
2999 install_operand (s[1], tmpreg);
3000 break;
3001 case '_': /* used only for move16 absolute 32-bit address */
3002 if (isvar (&opP->disp))
3003 add_fix ('l', &opP->disp, 0, 0);
3004 tmpreg = get_num (&opP->disp, 80);
3005 addword (tmpreg >> 16);
3006 addword (tmpreg & 0xFFFF);
3007 break;
3008 case 'u':
3009 install_operand (s[1], opP->reg - DATA0L);
3010 opP->reg -= (DATA0L);
3011 opP->reg &= 0x0F; /* remove upper/lower bit */
3012 break;
3013 default:
3014 abort ();
3015 }
3016 }
3017
3018 /* By the time whe get here (FINALLY) the_ins contains the complete
3019 instruction, ready to be emitted. . . */
3020}
3021
3022static int
3023reverse_16_bits (in)
3024 int in;
3025{
3026 int out = 0;
3027 int n;
3028
3029 static int mask[16] =
3030 {
3031 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3032 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3033 };
3034 for (n = 0; n < 16; n++)
3035 {
3036 if (in & mask[n])
3037 out |= mask[15 - n];
3038 }
3039 return out;
3040} /* reverse_16_bits() */
3041
3042static int
3043reverse_8_bits (in)
3044 int in;
3045{
3046 int out = 0;
3047 int n;
3048
3049 static int mask[8] =
3050 {
3051 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3052 };
3053
3054 for (n = 0; n < 8; n++)
3055 {
3056 if (in & mask[n])
3057 out |= mask[7 - n];
3058 }
3059 return out;
3060} /* reverse_8_bits() */
3061
3062/* Cause an extra frag to be generated here, inserting up to 10 bytes
3063 (that value is chosen in the frag_var call in md_assemble). TYPE
3064 is the subtype of the frag to be generated; its primary type is
3065 rs_machine_dependent.
3066
3067 The TYPE parameter is also used by md_convert_frag_1 and
3068 md_estimate_size_before_relax. The appropriate type of fixup will
3069 be emitted by md_convert_frag_1.
3070
3071 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3072static void
3073install_operand (mode, val)
3074 int mode;
3075 int val;
3076{
3077 switch (mode)
3078 {
3079 case 's':
3080 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3081 break;
3082 case 'd':
3083 the_ins.opcode[0] |= val << 9;
3084 break;
3085 case '1':
3086 the_ins.opcode[1] |= val << 12;
3087 break;
3088 case '2':
3089 the_ins.opcode[1] |= val << 6;
3090 break;
3091 case '3':
3092 the_ins.opcode[1] |= val;
3093 break;
3094 case '4':
3095 the_ins.opcode[2] |= val << 12;
3096 break;
3097 case '5':
3098 the_ins.opcode[2] |= val << 6;
3099 break;
3100 case '6':
3101 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3102 three words long! */
3103 the_ins.numo++;
3104 the_ins.opcode[2] |= val;
3105 break;
3106 case '7':
3107 the_ins.opcode[1] |= val << 7;
3108 break;
3109 case '8':
3110 the_ins.opcode[1] |= val << 10;
3111 break;
3112#ifndef NO_68851
3113 case '9':
3114 the_ins.opcode[1] |= val << 5;
3115 break;
3116#endif
3117
3118 case 't':
3119 the_ins.opcode[1] |= (val << 10) | (val << 7);
3120 break;
3121 case 'D':
3122 the_ins.opcode[1] |= (val << 12) | val;
3123 break;
3124 case 'g':
3125 the_ins.opcode[0] |= val = 0xff;
3126 break;
3127 case 'i':
3128 the_ins.opcode[0] |= val << 9;
3129 break;
3130 case 'C':
3131 the_ins.opcode[1] |= val;
3132 break;
3133 case 'j':
3134 the_ins.opcode[1] |= val;
3135 the_ins.numo++; /* What a hack */
3136 break;
3137 case 'k':
3138 the_ins.opcode[1] |= val << 4;
3139 break;
3140 case 'b':
3141 case 'w':
3142 case 'W':
3143 case 'l':
3144 break;
3145 case 'e':
3146 the_ins.opcode[0] |= (val << 6);
3147 break;
3148 case 'L':
3149 the_ins.opcode[1] = (val >> 16);
3150 the_ins.opcode[2] = val & 0xffff;
3151 break;
3152 case 'm':
3153 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3154 the_ins.opcode[0] |= ((val & 0x7) << 9);
3155 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3156 break;
3157 case 'n':
3158 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3159 the_ins.opcode[0] |= ((val & 0x7) << 9);
3160 break;
3161 case 'o':
3162 the_ins.opcode[1] |= val << 12;
3163 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3164 break;
3165 case 'M':
3166 the_ins.opcode[0] |= (val & 0xF);
3167 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3168 break;
3169 case 'N':
3170 the_ins.opcode[1] |= (val & 0xF);
3171 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3172 break;
3173 case 'h':
3174 the_ins.opcode[1] |= ((val != 1) << 10);
3175 break;
3176 case 'c':
3177 default:
3178 as_fatal (_("failed sanity check."));
3179 }
3180} /* install_operand() */
3181
3182static void
3183install_gen_operand (mode, val)
3184 int mode;
3185 int val;
3186{
3187 switch (mode)
3188 {
3189 case 's':
3190 the_ins.opcode[0] |= val;
3191 break;
3192 case 'd':
3193 /* This is a kludge!!! */
3194 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3195 break;
3196 case 'b':
3197 case 'w':
3198 case 'l':
3199 case 'f':
3200 case 'F':
3201 case 'x':
3202 case 'p':
3203 the_ins.opcode[0] |= val;
3204 break;
3205 /* more stuff goes here */
3206 default:
3207 as_fatal (_("failed sanity check."));
3208 }
3209} /* install_gen_operand() */
3210
3211/*
3212 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3213 * then deal with the bitfield hack.
3214 */
3215
3216static char *
3217crack_operand (str, opP)
3218 register char *str;
3219 register struct m68k_op *opP;
3220{
3221 register int parens;
3222 register int c;
3223 register char *beg_str;
3224 int inquote = 0;
3225
3226 if (!str)
3227 {
3228 return str;
3229 }
3230 beg_str = str;
3231 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3232 {
3233 if (! inquote)
3234 {
3235 if (*str == '(')
3236 parens++;
3237 else if (*str == ')')
3238 {
3239 if (!parens)
3240 { /* ERROR */
3241 opP->error = _("Extra )");
3242 return str;
3243 }
3244 --parens;
3245 }
3246 }
3247 if (flag_mri && *str == '\'')
3248 inquote = ! inquote;
3249 }
3250 if (!*str && parens)
3251 { /* ERROR */
3252 opP->error = _("Missing )");
3253 return str;
3254 }
3255 c = *str;
3256 *str = '\0';
3257 if (m68k_ip_op (beg_str, opP) != 0)
3258 {
3259 *str = c;
3260 return str;
3261 }
3262 *str = c;
3263 if (c == '}')
3264 c = *++str; /* JF bitfield hack */
3265 if (c)
3266 {
3267 c = *++str;
3268 if (!c)
3269 as_bad (_("Missing operand"));
3270 }
3271
3272 /* Detect MRI REG symbols and convert them to REGLSTs. */
3273 if (opP->mode == CONTROL && (int)opP->reg < 0)
3274 {
3275 opP->mode = REGLST;
3276 opP->mask = ~(int)opP->reg;
3277 opP->reg = 0;
3278 }
3279
3280 return str;
3281}
3282
3283/* This is the guts of the machine-dependent assembler. STR points to a
3284 machine dependent instruction. This function is supposed to emit
3285 the frags/bytes it assembles to.
3286 */
3287
3288static void
3289insert_reg (regname, regnum)
3290 const char *regname;
3291 int regnum;
3292{
3293 char buf[100];
3294 int i;
3295
3296#ifdef REGISTER_PREFIX
3297 if (!flag_reg_prefix_optional)
3298 {
3299 buf[0] = REGISTER_PREFIX;
3300 strcpy (buf + 1, regname);
3301 regname = buf;
3302 }
3303#endif
3304
3305 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3306 &zero_address_frag));
3307
3308 for (i = 0; regname[i]; i++)
3309 buf[i] = TOUPPER (regname[i]);
3310 buf[i] = '\0';
3311
3312 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3313 &zero_address_frag));
3314}
3315
3316struct init_entry
3317 {
3318 const char *name;
3319 int number;
3320 };
3321
3322static const struct init_entry init_table[] =
3323{
3324 { "d0", DATA0 },
3325 { "d1", DATA1 },
3326 { "d2", DATA2 },
3327 { "d3", DATA3 },
3328 { "d4", DATA4 },
3329 { "d5", DATA5 },
3330 { "d6", DATA6 },
3331 { "d7", DATA7 },
3332 { "a0", ADDR0 },
3333 { "a1", ADDR1 },
3334 { "a2", ADDR2 },
3335 { "a3", ADDR3 },
3336 { "a4", ADDR4 },
3337 { "a5", ADDR5 },
3338 { "a6", ADDR6 },
3339 { "fp", ADDR6 },
3340 { "a7", ADDR7 },
3341 { "sp", ADDR7 },
3342 { "ssp", ADDR7 },
3343 { "fp0", FP0 },
3344 { "fp1", FP1 },
3345 { "fp2", FP2 },
3346 { "fp3", FP3 },
3347 { "fp4", FP4 },
3348 { "fp5", FP5 },
3349 { "fp6", FP6 },
3350 { "fp7", FP7 },
3351 { "fpi", FPI },
3352 { "fpiar", FPI },
3353 { "fpc", FPI },
3354 { "fps", FPS },
3355 { "fpsr", FPS },
3356 { "fpc", FPC },
3357 { "fpcr", FPC },
3358 { "control", FPC },
3359 { "status", FPS },
3360 { "iaddr", FPI },
3361
3362 { "cop0", COP0 },
3363 { "cop1", COP1 },
3364 { "cop2", COP2 },
3365 { "cop3", COP3 },
3366 { "cop4", COP4 },
3367 { "cop5", COP5 },
3368 { "cop6", COP6 },
3369 { "cop7", COP7 },
3370 { "pc", PC },
3371 { "zpc", ZPC },
3372 { "sr", SR },
3373
3374 { "ccr", CCR },
3375 { "cc", CCR },
3376
3377 { "acc", ACC },
3378 { "macsr", MACSR },
3379 { "mask", MASK },
3380
3381 /* control registers */
3382 { "sfc", SFC }, /* Source Function Code */
3383 { "sfcr", SFC },
3384 { "dfc", DFC }, /* Destination Function Code */
3385 { "dfcr", DFC },
3386 { "cacr", CACR }, /* Cache Control Register */
3387 { "caar", CAAR }, /* Cache Address Register */
3388
3389 { "usp", USP }, /* User Stack Pointer */
3390 { "vbr", VBR }, /* Vector Base Register */
3391 { "msp", MSP }, /* Master Stack Pointer */
3392 { "isp", ISP }, /* Interrupt Stack Pointer */
3393
3394 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3395 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3396 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3397 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3398
3399 /* 68ec040 versions of same */
3400 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3401 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3402 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3403 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3404
3405 /* mcf5200 versions of same. The ColdFire programmer's reference
3406 manual indicated that the order is 2,3,0,1, but Ken Rose
3407 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3408 { "acr0", ITT0 }, /* Access Control Unit 0 */
3409 { "acr1", ITT1 }, /* Access Control Unit 1 */
3410 { "acr2", DTT0 }, /* Access Control Unit 2 */
3411 { "acr3", DTT1 }, /* Access Control Unit 3 */
3412
3413 { "tc", TC }, /* MMU Translation Control Register */
3414 { "tcr", TC },
3415
3416 { "mmusr", MMUSR }, /* MMU Status Register */
3417 { "srp", SRP }, /* User Root Pointer */
3418 { "urp", URP }, /* Supervisor Root Pointer */
3419
3420 { "buscr", BUSCR },
3421 { "pcr", PCR },
3422
3423 { "rombar", ROMBAR }, /* ROM Base Address Register */
3424 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3425 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3426 { "mbar", MBAR }, /* Module Base Address Register */
3427 /* end of control registers */
3428
3429 { "ac", AC },
3430 { "bc", BC },
3431 { "cal", CAL },
3432 { "crp", CRP },
3433 { "drp", DRP },
3434 { "pcsr", PCSR },
3435 { "psr", PSR },
3436 { "scc", SCC },
3437 { "val", VAL },
3438 { "bad0", BAD0 },
3439 { "bad1", BAD1 },
3440 { "bad2", BAD2 },
3441 { "bad3", BAD3 },
3442 { "bad4", BAD4 },
3443 { "bad5", BAD5 },
3444 { "bad6", BAD6 },
3445 { "bad7", BAD7 },
3446 { "bac0", BAC0 },
3447 { "bac1", BAC1 },
3448 { "bac2", BAC2 },
3449 { "bac3", BAC3 },
3450 { "bac4", BAC4 },
3451 { "bac5", BAC5 },
3452 { "bac6", BAC6 },
3453 { "bac7", BAC7 },
3454
3455 { "ic", IC },
3456 { "dc", DC },
3457 { "nc", NC },
3458
3459 { "tt0", TT0 },
3460 { "tt1", TT1 },
3461 /* 68ec030 versions of same */
3462 { "ac0", TT0 },
3463 { "ac1", TT1 },
3464 /* 68ec030 access control unit, identical to 030 MMU status reg */
3465 { "acusr", PSR },
3466
3467 /* Suppressed data and address registers. */
3468 { "zd0", ZDATA0 },
3469 { "zd1", ZDATA1 },
3470 { "zd2", ZDATA2 },
3471 { "zd3", ZDATA3 },
3472 { "zd4", ZDATA4 },
3473 { "zd5", ZDATA5 },
3474 { "zd6", ZDATA6 },
3475 { "zd7", ZDATA7 },
3476 { "za0", ZADDR0 },
3477 { "za1", ZADDR1 },
3478 { "za2", ZADDR2 },
3479 { "za3", ZADDR3 },
3480 { "za4", ZADDR4 },
3481 { "za5", ZADDR5 },
3482 { "za6", ZADDR6 },
3483 { "za7", ZADDR7 },
3484
3485 /* Upper and lower data and address registers, used by macw and msacw. */
3486 { "d0l", DATA0L },
3487 { "d1l", DATA1L },
3488 { "d2l", DATA2L },
3489 { "d3l", DATA3L },
3490 { "d4l", DATA4L },
3491 { "d5l", DATA5L },
3492 { "d6l", DATA6L },
3493 { "d7l", DATA7L },
3494
3495 { "a0l", ADDR0L },
3496 { "a1l", ADDR1L },
3497 { "a2l", ADDR2L },
3498 { "a3l", ADDR3L },
3499 { "a4l", ADDR4L },
3500 { "a5l", ADDR5L },
3501 { "a6l", ADDR6L },
3502 { "a7l", ADDR7L },
3503
3504 { "d0u", DATA0U },
3505 { "d1u", DATA1U },
3506 { "d2u", DATA2U },
3507 { "d3u", DATA3U },
3508 { "d4u", DATA4U },
3509 { "d5u", DATA5U },
3510 { "d6u", DATA6U },
3511 { "d7u", DATA7U },
3512
3513 { "a0u", ADDR0U },
3514 { "a1u", ADDR1U },
3515 { "a2u", ADDR2U },
3516 { "a3u", ADDR3U },
3517 { "a4u", ADDR4U },
3518 { "a5u", ADDR5U },
3519 { "a6u", ADDR6U },
3520 { "a7u", ADDR7U },
3521
3522 { 0, 0 }
3523};
3524
3525static void
3526init_regtable ()
3527{
3528 int i;
3529 for (i = 0; init_table[i].name; i++)
3530 insert_reg (init_table[i].name, init_table[i].number);
3531}
3532
3533static int no_68851, no_68881;
3534
3535#ifdef OBJ_AOUT
3536/* a.out machine type. Default to 68020. */
3537int m68k_aout_machtype = 2;
3538#endif
3539
3540void
3541md_assemble (str)
3542 char *str;
3543{
3544 const char *er;
3545 short *fromP;
3546 char *toP = NULL;
3547 int m, n = 0;
3548 char *to_beg_P;
3549 int shorts_this_frag;
3550 fixS *fixP;
3551
3552 /* In MRI mode, the instruction and operands are separated by a
3553 space. Anything following the operands is a comment. The label
3554 has already been removed. */
3555 if (flag_mri)
3556 {
3557 char *s;
3558 int fields = 0;
3559 int infield = 0;
3560 int inquote = 0;
3561
3562 for (s = str; *s != '\0'; s++)
3563 {
3564 if ((*s == ' ' || *s == '\t') && ! inquote)
3565 {
3566 if (infield)
3567 {
3568 ++fields;
3569 if (fields >= 2)
3570 {
3571 *s = '\0';
3572 break;
3573 }
3574 infield = 0;
3575 }
3576 }
3577 else
3578 {
3579 if (! infield)
3580 infield = 1;
3581 if (*s == '\'')
3582 inquote = ! inquote;
3583 }
3584 }
3585 }
3586
3587 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3588 m68k_ip (str);
3589 er = the_ins.error;
3590 if (!er)
3591 {
3592 for (n = 0; n < the_ins.numargs; n++)
3593 if (the_ins.operands[n].error)
3594 {
3595 er = the_ins.operands[n].error;
3596 break;
3597 }
3598 }
3599 if (er)
3600 {
3601 as_bad (_("%s -- statement `%s' ignored"), er, str);
3602 return;
3603 }
3604
3605 /* If there is a current label, record that it marks an instruction. */
3606 if (current_label != NULL)
3607 {
3608 current_label->text = 1;
3609 current_label = NULL;
3610 }
3611
3612#ifdef OBJ_ELF
3613 /* Tie dwarf2 debug info to the address at the start of the insn. */
3614 dwarf2_emit_insn (0);
3615#endif
3616
3617 if (the_ins.nfrag == 0)
3618 {
3619 /* No frag hacking involved; just put it out */
3620 toP = frag_more (2 * the_ins.numo);
3621 fromP = &the_ins.opcode[0];
3622 for (m = the_ins.numo; m; --m)
3623 {
3624 md_number_to_chars (toP, (long) (*fromP), 2);
3625 toP += 2;
3626 fromP++;
3627 }
3628 /* put out symbol-dependent info */
3629 for (m = 0; m < the_ins.nrel; m++)
3630 {
3631 switch (the_ins.reloc[m].wid)
3632 {
3633 case 'B':
3634 n = 1;
3635 break;
3636 case 'b':
3637 n = 1;
3638 break;
3639 case '3':
3640 n = 1;
3641 break;
3642 case 'w':
3643 case 'W':
3644 n = 2;
3645 break;
3646 case 'l':
3647 n = 4;
3648 break;
3649 default:
3650 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3651 the_ins.reloc[m].wid);
3652 }
3653
3654 fixP = fix_new_exp (frag_now,
3655 ((toP - frag_now->fr_literal)
3656 - the_ins.numo * 2 + the_ins.reloc[m].n),
3657 n,
3658 &the_ins.reloc[m].exp,
3659 the_ins.reloc[m].pcrel,
3660 get_reloc_code (n, the_ins.reloc[m].pcrel,
3661 the_ins.reloc[m].pic_reloc));
3662 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3663 if (the_ins.reloc[m].wid == 'B')
3664 fixP->fx_signed = 1;
3665 }
3666 return;
3667 }
3668
3669 /* There's some frag hacking */
3670 {
3671 /* Calculate the max frag size. */
3672 int wid;
3673
3674 wid = 2 * the_ins.fragb[0].fragoff;
3675 for (n = 1; n < the_ins.nfrag; n++)
3676 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3677 /* frag_var part. */
3678 wid += 10;
3679 /* Make sure the whole insn fits in one chunk, in particular that
3680 the var part is attached, as we access one byte before the
3681 variable frag for byte branches. */
3682 frag_grow (wid);
3683 }
3684
3685 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3686 {
3687 int wid;
3688
3689 if (n == 0)
3690 wid = 2 * the_ins.fragb[n].fragoff;
3691 else
3692 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3693 toP = frag_more (wid);
3694 to_beg_P = toP;
3695 shorts_this_frag = 0;
3696 for (m = wid / 2; m; --m)
3697 {
3698 md_number_to_chars (toP, (long) (*fromP), 2);
3699 toP += 2;
3700 fromP++;
3701 shorts_this_frag++;
3702 }
3703 for (m = 0; m < the_ins.nrel; m++)
3704 {
3705 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3706 {
3707 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3708 break;
3709 }
3710 wid = the_ins.reloc[m].wid;
3711 if (wid == 0)
3712 continue;
3713 the_ins.reloc[m].wid = 0;
3714 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3715
3716 fixP = fix_new_exp (frag_now,
3717 ((toP - frag_now->fr_literal)
3718 - the_ins.numo * 2 + the_ins.reloc[m].n),
3719 wid,
3720 &the_ins.reloc[m].exp,
3721 the_ins.reloc[m].pcrel,
3722 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3723 the_ins.reloc[m].pic_reloc));
3724 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3725 }
3726 (void) frag_var (rs_machine_dependent, 10, 0,
3727 (relax_substateT) (the_ins.fragb[n].fragty),
3728 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3729 }
3730 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3731 shorts_this_frag = 0;
3732 if (n)
3733 {
3734 toP = frag_more (n * sizeof (short));
3735 while (n--)
3736 {
3737 md_number_to_chars (toP, (long) (*fromP), 2);
3738 toP += 2;
3739 fromP++;
3740 shorts_this_frag++;
3741 }
3742 }
3743 for (m = 0; m < the_ins.nrel; m++)
3744 {
3745 int wid;
3746
3747 wid = the_ins.reloc[m].wid;
3748 if (wid == 0)
3749 continue;
3750 the_ins.reloc[m].wid = 0;
3751 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3752
3753 fixP = fix_new_exp (frag_now,
3754 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3755 - shorts_this_frag * 2),
3756 wid,
3757 &the_ins.reloc[m].exp,
3758 the_ins.reloc[m].pcrel,
3759 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3760 the_ins.reloc[m].pic_reloc));
3761 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3762 }
3763}
3764
3765void
3766md_begin ()
3767{
3768 /*
3769 * md_begin -- set up hash tables with 68000 instructions.
3770 * similar to what the vax assembler does. ---phr
3771 */
3772 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3773 a copy of it at runtime, adding in the information we want but isn't
3774 there. I think it'd be better to have an awk script hack the table
3775 at compile time. Or even just xstr the table and use it as-is. But
3776 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3777 names. */
3778
3779 const struct m68k_opcode *ins;
3780 struct m68k_incant *hack, *slak;
3781 const char *retval = 0; /* empty string, or error msg text */
3782 int i;
3783
3784 if (flag_mri)
3785 {
3786 flag_reg_prefix_optional = 1;
3787 m68k_abspcadd = 1;
3788 if (! m68k_rel32_from_cmdline)
3789 m68k_rel32 = 0;
3790 }
3791
3792 op_hash = hash_new ();
3793
3794 obstack_begin (&robyn, 4000);
3795 for (i = 0; i < m68k_numopcodes; i++)
3796 {
3797 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3798 do
3799 {
3800 ins = &m68k_opcodes[i];
3801 /* We *could* ignore insns that don't match our arch here
3802 but just leaving them out of the hash. */
3803 slak->m_operands = ins->args;
3804 slak->m_opnum = strlen (slak->m_operands) / 2;
3805 slak->m_arch = ins->arch;
3806 slak->m_opcode = ins->opcode;
3807 /* This is kludgey */
3808 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3809 if (i + 1 != m68k_numopcodes
3810 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3811 {
3812 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3813 i++;
3814 }
3815 else
3816 slak->m_next = 0;
3817 slak = slak->m_next;
3818 }
3819 while (slak);
3820
3821 retval = hash_insert (op_hash, ins->name, (char *) hack);
3822 if (retval)
3823 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3824 }
3825
3826 for (i = 0; i < m68k_numaliases; i++)
3827 {
3828 const char *name = m68k_opcode_aliases[i].primary;
3829 const char *alias = m68k_opcode_aliases[i].alias;
3830 PTR val = hash_find (op_hash, name);
3831 if (!val)
3832 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3833 retval = hash_insert (op_hash, alias, val);
3834 if (retval)
3835 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3836 }
3837
3838 /* In MRI mode, all unsized branches are variable sized. Normally,
3839 they are word sized. */
3840 if (flag_mri)
3841 {
3842 static struct m68k_opcode_alias mri_aliases[] =
3843 {
3844 { "bhi", "jhi", },
3845 { "bls", "jls", },
3846 { "bcc", "jcc", },
3847 { "bcs", "jcs", },
3848 { "bne", "jne", },
3849 { "beq", "jeq", },
3850 { "bvc", "jvc", },
3851 { "bvs", "jvs", },
3852 { "bpl", "jpl", },
3853 { "bmi", "jmi", },
3854 { "bge", "jge", },
3855 { "blt", "jlt", },
3856 { "bgt", "jgt", },
3857 { "ble", "jle", },
3858 { "bra", "jra", },
3859 { "bsr", "jbsr", },
3860 };
3861
3862 for (i = 0;
3863 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3864 i++)
3865 {
3866 const char *name = mri_aliases[i].primary;
3867 const char *alias = mri_aliases[i].alias;
3868 PTR val = hash_find (op_hash, name);
3869 if (!val)
3870 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3871 retval = hash_jam (op_hash, alias, val);
3872 if (retval)
3873 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3874 }
3875 }
3876
3877 for (i = 0; i < (int) sizeof (notend_table); i++)
3878 {
3879 notend_table[i] = 0;
3880 alt_notend_table[i] = 0;
3881 }
3882 notend_table[','] = 1;
3883 notend_table['{'] = 1;
3884 notend_table['}'] = 1;
3885 alt_notend_table['a'] = 1;
3886 alt_notend_table['A'] = 1;
3887 alt_notend_table['d'] = 1;
3888 alt_notend_table['D'] = 1;
3889 alt_notend_table['#'] = 1;
3890 alt_notend_table['&'] = 1;
3891 alt_notend_table['f'] = 1;
3892 alt_notend_table['F'] = 1;
3893#ifdef REGISTER_PREFIX
3894 alt_notend_table[REGISTER_PREFIX] = 1;
3895#endif
3896
3897 /* We need to put '(' in alt_notend_table to handle
3898 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3899 */
3900 alt_notend_table['('] = 1;
3901
3902 /* We need to put '@' in alt_notend_table to handle
3903 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3904 */
3905 alt_notend_table['@'] = 1;
3906
3907 /* We need to put digits in alt_notend_table to handle
3908 bfextu %d0{24:1},%d0
3909 */
3910 alt_notend_table['0'] = 1;
3911 alt_notend_table['1'] = 1;
3912 alt_notend_table['2'] = 1;
3913 alt_notend_table['3'] = 1;
3914 alt_notend_table['4'] = 1;
3915 alt_notend_table['5'] = 1;
3916 alt_notend_table['6'] = 1;
3917 alt_notend_table['7'] = 1;
3918 alt_notend_table['8'] = 1;
3919 alt_notend_table['9'] = 1;
3920
3921#ifndef MIT_SYNTAX_ONLY
3922 /* Insert pseudo ops, these have to go into the opcode table since
3923 gas expects pseudo ops to start with a dot */
3924 {
3925 int n = 0;
3926 while (mote_pseudo_table[n].poc_name)
3927 {
3928 hack = (struct m68k_incant *)
3929 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3930 hash_insert (op_hash,
3931 mote_pseudo_table[n].poc_name, (char *) hack);
3932 hack->m_operands = 0;
3933 hack->m_opnum = n;
3934 n++;
3935 }
3936 }
3937#endif
3938
3939 init_regtable ();
3940
3941#ifdef OBJ_ELF
3942 record_alignment (text_section, 2);
3943 record_alignment (data_section, 2);
3944 record_alignment (bss_section, 2);
3945#endif
3946}
3947
3948static void
3949select_control_regs ()
3950{
3951 /* Note which set of "movec" control registers is available. */
3952 switch (cpu_of_arch (current_architecture))
3953 {
3954 case 0:
3955 as_warn (_("architecture not yet selected: defaulting to 68020"));
3956 control_regs = m68020_control_regs;
3957 break;
3958
3959 case m68000:
3960 control_regs = m68000_control_regs;
3961 break;
3962 case m68010:
3963 control_regs = m68010_control_regs;
3964 break;
3965 case m68020:
3966 case m68030:
3967 control_regs = m68020_control_regs;
3968 break;
3969 case m68040:
3970 control_regs = m68040_control_regs;
3971 break;
3972 case m68060:
3973 control_regs = m68060_control_regs;
3974 break;
3975 case cpu32:
3976 control_regs = cpu32_control_regs;
3977 break;
3978 case mcf5200:
3979 case mcf5206e:
3980 case mcf5307:
3981 case mcf5407:
3982 control_regs = mcf_control_regs;
3983 break;
3984 default:
3985 abort ();
3986 }
3987}
3988
3989void
3990m68k_init_after_args ()
3991{
3992 if (cpu_of_arch (current_architecture) == 0)
3993 {
3994 int i;
3995 const char *default_cpu = TARGET_CPU;
3996
3997 if (*default_cpu == 'm')
3998 default_cpu++;
3999 for (i = 0; i < n_archs; i++)
4000 if (strcasecmp (default_cpu, archs[i].name) == 0)
4001 break;
4002 if (i == n_archs)
4003 {
4004 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4005 current_architecture |= m68020;
4006 }
4007 else
4008 current_architecture |= archs[i].arch;
4009 }
4010 /* Permit m68881 specification with all cpus; those that can't work
4011 with a coprocessor could be doing emulation. */
4012 if (current_architecture & m68851)
4013 {
4014 if (current_architecture & m68040)
4015 {
4016 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4017 }
4018 }
4019 /* What other incompatibilities could we check for? */
4020
4021 /* Toss in some default assumptions about coprocessors. */
4022 if (!no_68881
4023 && (cpu_of_arch (current_architecture)
4024 /* Can CPU32 have a 68881 coprocessor?? */
4025 & (m68020 | m68030 | cpu32)))
4026 {
4027 current_architecture |= m68881;
4028 }
4029 if (!no_68851
4030 && (cpu_of_arch (current_architecture) & m68020up) != 0
4031 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4032 {
4033 current_architecture |= m68851;
4034 }
4035 if (no_68881 && (current_architecture & m68881))
4036 as_bad (_("options for 68881 and no-68881 both given"));
4037 if (no_68851 && (current_architecture & m68851))
4038 as_bad (_("options for 68851 and no-68851 both given"));
4039
4040#ifdef OBJ_AOUT
4041 /* Work out the magic number. This isn't very general. */
4042 if (current_architecture & m68000)
4043 m68k_aout_machtype = 0;
4044 else if (current_architecture & m68010)
4045 m68k_aout_machtype = 1;
4046 else if (current_architecture & m68020)
4047 m68k_aout_machtype = 2;
4048 else
4049 m68k_aout_machtype = 2;
4050#endif
4051
4052 /* Note which set of "movec" control registers is available. */
4053 select_control_regs ();
4054
4055 if (cpu_of_arch (current_architecture) < m68020
4056 || arch_coldfire_p (current_architecture))
4057 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4058}
4059
4060
4061/* This is called when a label is defined. */
4062
4063void
4064m68k_frob_label (sym)
4065 symbolS *sym;
4066{
4067 struct label_line *n;
4068
4069 n = (struct label_line *) xmalloc (sizeof *n);
4070 n->next = labels;
4071 n->label = sym;
4072 as_where (&n->file, &n->line);
4073 n->text = 0;
4074 labels = n;
4075 current_label = n;
4076}
4077
4078/* This is called when a value that is not an instruction is emitted. */
4079
4080void
4081m68k_flush_pending_output ()
4082{
4083 current_label = NULL;
4084}
4085
4086/* This is called at the end of the assembly, when the final value of
4087 the label is known. We warn if this is a text symbol aligned at an
4088 odd location. */
4089
4090void
4091m68k_frob_symbol (sym)
4092 symbolS *sym;
4093{
4094 if (S_GET_SEGMENT (sym) == reg_section
4095 && (int) S_GET_VALUE (sym) < 0)
4096 {
4097 S_SET_SEGMENT (sym, absolute_section);
4098 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4099 }
4100 else if ((S_GET_VALUE (sym) & 1) != 0)
4101 {
4102 struct label_line *l;
4103
4104 for (l = labels; l != NULL; l = l->next)
4105 {
4106 if (l->label == sym)
4107 {
4108 if (l->text)
4109 as_warn_where (l->file, l->line,
4110 _("text label `%s' aligned to odd boundary"),
4111 S_GET_NAME (sym));
4112 break;
4113 }
4114 }
4115 }
4116}
4117
4118
4119/* This is called if we go in or out of MRI mode because of the .mri
4120 pseudo-op. */
4121
4122void
4123m68k_mri_mode_change (on)
4124 int on;
4125{
4126 if (on)
4127 {
4128 if (! flag_reg_prefix_optional)
4129 {
4130 flag_reg_prefix_optional = 1;
4131#ifdef REGISTER_PREFIX
4132 init_regtable ();
4133#endif
4134 }
4135 m68k_abspcadd = 1;
4136 if (! m68k_rel32_from_cmdline)
4137 m68k_rel32 = 0;
4138 }
4139 else
4140 {
4141 if (! reg_prefix_optional_seen)
4142 {
4143#ifdef REGISTER_PREFIX_OPTIONAL
4144 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4145#else
4146 flag_reg_prefix_optional = 0;
4147#endif
4148#ifdef REGISTER_PREFIX
4149 init_regtable ();
4150#endif
4151 }
4152 m68k_abspcadd = 0;
4153 if (! m68k_rel32_from_cmdline)
4154 m68k_rel32 = 1;
4155 }
4156}
4157
4158/* Equal to MAX_PRECISION in atof-ieee.c */
4159#define MAX_LITTLENUMS 6
4160
4161/* Turn a string in input_line_pointer into a floating point constant
4162 of type TYPE, and store the appropriate bytes in *LITP. The number
4163 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4164 returned, or NULL on OK. */
4165
4166char *
4167md_atof (type, litP, sizeP)
4168 char type;
4169 char *litP;
4170 int *sizeP;
4171{
4172 int prec;
4173 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4174 LITTLENUM_TYPE *wordP;
4175 char *t;
4176
4177 switch (type)
4178 {
4179 case 'f':
4180 case 'F':
4181 case 's':
4182 case 'S':
4183 prec = 2;
4184 break;
4185
4186 case 'd':
4187 case 'D':
4188 case 'r':
4189 case 'R':
4190 prec = 4;
4191 break;
4192
4193 case 'x':
4194 case 'X':
4195 prec = 6;
4196 break;
4197
4198 case 'p':
4199 case 'P':
4200 prec = 6;
4201 break;
4202
4203 default:
4204 *sizeP = 0;
4205 return _("Bad call to MD_ATOF()");
4206 }
4207 t = atof_ieee (input_line_pointer, type, words);
4208 if (t)
4209 input_line_pointer = t;
4210
4211 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4212 for (wordP = words; prec--;)
4213 {
4214 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4215 litP += sizeof (LITTLENUM_TYPE);
4216 }
4217 return 0;
4218}
4219
4220void
4221md_number_to_chars (buf, val, n)
4222 char *buf;
4223 valueT val;
4224 int n;
4225{
4226 number_to_chars_bigendian (buf, val, n);
4227}
4228
4229void
4230md_apply_fix3 (fixP, valP, seg)
4231 fixS *fixP;
4232 valueT *valP;
4233 segT seg ATTRIBUTE_UNUSED;
4234{
4235 offsetT val = *valP;
4236 addressT upper_limit;
4237 offsetT lower_limit;
4238
4239 /* This is unnecessary but it convinces the native rs6000 compiler
4240 to generate the code we want. */
4241 char *buf = fixP->fx_frag->fr_literal;
4242 buf += fixP->fx_where;
4243 /* end ibm compiler workaround */
4244
4245 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
4246
4247 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4248 fixP->fx_done = 1;
4249
4250#ifdef OBJ_ELF
4251 if (fixP->fx_addsy)
4252 {
4253 memset (buf, 0, fixP->fx_size);
4254 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4255
4256 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4257 && !S_IS_DEFINED (fixP->fx_addsy)
4258 && !S_IS_WEAK (fixP->fx_addsy))
4259 S_SET_WEAK (fixP->fx_addsy);
4260 return;
4261 }
4262#endif
4263
4264#ifdef BFD_ASSEMBLER
4265 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4266 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4267 return;
4268#endif
4269
4270 switch (fixP->fx_size)
4271 {
4272 /* The cast to offsetT below are necessary to make code
4273 correct for machines where ints are smaller than offsetT. */
4274 case 1:
4275 *buf++ = val;
4276 upper_limit = 0x7f;
4277 lower_limit = - (offsetT) 0x80;
4278 break;
4279 case 2:
4280 *buf++ = (val >> 8);
4281 *buf++ = val;
4282 upper_limit = 0x7fff;
4283 lower_limit = - (offsetT) 0x8000;
4284 break;
4285 case 4:
4286 *buf++ = (val >> 24);
4287 *buf++ = (val >> 16);
4288 *buf++ = (val >> 8);
4289 *buf++ = val;
4290 upper_limit = 0x7fffffff;
4291 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4292 break;
4293 default:
4294 BAD_CASE (fixP->fx_size);
4295 }
4296
4297 /* Fix up a negative reloc. */
4298 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4299 {
4300 fixP->fx_addsy = fixP->fx_subsy;
4301 fixP->fx_subsy = NULL;
4302 fixP->fx_tcbit = 1;
4303 }
4304
4305 /* For non-pc-relative values, it's conceivable we might get something
4306 like "0xff" for a byte field. So extend the upper part of the range
4307 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4308 so that we can do any range checking at all. */
4309 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4310 upper_limit = upper_limit * 2 + 1;
4311
4312 if ((addressT) val > upper_limit
4313 && (val > 0 || val < lower_limit))
4314 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4315
4316 /* A one byte PC-relative reloc means a short branch. We can't use
4317 a short branch with a value of 0 or -1, because those indicate
4318 different opcodes (branches with longer offsets). fixup_segment
4319 in write.c may have clobbered fx_pcrel, so we need to examine the
4320 reloc type. */
4321 if ((fixP->fx_pcrel
4322#ifdef BFD_ASSEMBLER
4323 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4324#endif
4325 )
4326 && fixP->fx_size == 1
4327 && (fixP->fx_addsy == NULL
4328 || S_IS_DEFINED (fixP->fx_addsy))
4329 && (val == 0 || val == -1))
4330 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4331}
4332
4333/* *fragP has been relaxed to its final size, and now needs to have
4334 the bytes inside it modified to conform to the new size There is UGLY
4335 MAGIC here. ..
4336 */
4337static void
4338md_convert_frag_1 (fragP)
4339 register fragS *fragP;
4340{
4341 long disp;
4342 fixS *fixP;
4343
4344 /* Address in object code of the displacement. */
4345 register int object_address = fragP->fr_fix + fragP->fr_address;
4346
4347 /* Address in gas core of the place to store the displacement. */
4348 /* This convinces the native rs6000 compiler to generate the code we
4349 want. */
4350 register char *buffer_address = fragP->fr_literal;
4351 buffer_address += fragP->fr_fix;
4352 /* end ibm compiler workaround */
4353
4354 /* The displacement of the address, from current location. */
4355 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4356 disp = (disp + fragP->fr_offset) - object_address;
4357
4358 switch (fragP->fr_subtype)
4359 {
4360 case TAB (BRANCHBWL, BYTE):
4361 case TAB (BRABSJUNC, BYTE):
4362 case TAB (BRABSJCOND, BYTE):
4363 case TAB (BRANCHBW, BYTE):
4364 know (issbyte (disp));
4365 if (disp == 0)
4366 as_bad_where (fragP->fr_file, fragP->fr_line,
4367 _("short branch with zero offset: use :w"));
4368 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4369 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4370 fixP->fx_pcrel_adjust = -1;
4371 break;
4372 case TAB (BRANCHBWL, SHORT):
4373 case TAB (BRABSJUNC, SHORT):
4374 case TAB (BRABSJCOND, SHORT):
4375 case TAB (BRANCHBW, SHORT):
4376 fragP->fr_opcode[1] = 0x00;
4377 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4378 1, RELAX_RELOC_PC16);
4379 fragP->fr_fix += 2;
4380 break;
4381 case TAB (BRANCHBWL, LONG):
4382 fragP->fr_opcode[1] = (char) 0xFF;
4383 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4384 1, RELAX_RELOC_PC32);
4385 fragP->fr_fix += 4;
4386 break;
4387 case TAB (BRABSJUNC, LONG):
4388 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4389 {
4390 fragP->fr_opcode[0] = 0x4E;
4391 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4392 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4393 0, RELAX_RELOC_ABS32);
4394 fragP->fr_fix += 4;
4395 }
4396 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4397 {
4398 fragP->fr_opcode[0] = 0x4E;
4399 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4400 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4401 0, RELAX_RELOC_ABS32);
4402 fragP->fr_fix += 4;
4403 }
4404 else
4405 {
4406 /* This cannot happen, because jbsr and jbra are the only two
4407 unconditional branches. */
4408 abort ();
4409 }
4410 break;
4411 case TAB (BRABSJCOND, LONG):
4412 /* Only Bcc 68000 instructions can come here. */
4413 /* Change bcc into b!cc/jmp absl long. */
4414
4415 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4416 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4417
4418 /* JF: these used to be fr_opcode[2,3], but they may be in a
4419 different frag, in which case refering to them is a no-no.
4420 Only fr_opcode[0,1] are guaranteed to work. */
4421 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4422 *buffer_address++ = (char) 0xf9;
4423 fragP->fr_fix += 2; /* account for jmp instruction */
4424 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4425 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4426 fragP->fr_fix += 4;
4427 break;
4428 case TAB (FBRANCH, SHORT):
4429 know ((fragP->fr_opcode[1] & 0x40) == 0);
4430 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4431 1, RELAX_RELOC_PC16);
4432 fragP->fr_fix += 2;
4433 break;
4434 case TAB (FBRANCH, LONG):
4435 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4436 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4437 1, RELAX_RELOC_PC32);
4438 fragP->fr_fix += 4;
4439 break;
4440 case TAB (DBCCLBR, SHORT):
4441 case TAB (DBCCABSJ, SHORT):
4442 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4443 1, RELAX_RELOC_PC16);
4444 fragP->fr_fix += 2;
4445 break;
4446 case TAB (DBCCLBR, LONG):
4447 /* only DBcc instructions can come here */
4448 /* Change dbcc into dbcc/bral. */
4449
4450 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4451 *buffer_address++ = 0x00; /* branch offset = 4 */
4452 *buffer_address++ = 0x04;
4453 *buffer_address++ = 0x60; /* put in bra pc+6 */
4454 *buffer_address++ = 0x06;
4455 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4456 *buffer_address++ = (char) 0xff;
4457
4458 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4459 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4460 RELAX_RELOC_PC32);
4461 fragP->fr_fix += 4;
4462 break;
4463 case TAB (DBCCABSJ, LONG):
4464 /* only DBcc instructions can come here */
4465 /* Change dbcc into dbcc/jmp. */
4466
4467 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4468 *buffer_address++ = 0x00; /* branch offset = 4 */
4469 *buffer_address++ = 0x04;
4470 *buffer_address++ = 0x60; /* put in bra pc+6 */
4471 *buffer_address++ = 0x06;
4472 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4473 *buffer_address++ = (char) 0xf9;
4474
4475 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4476 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4477 RELAX_RELOC_ABS32);
4478 fragP->fr_fix += 4;
4479 break;
4480 case TAB (PCREL1632, SHORT):
4481 fragP->fr_opcode[1] &= ~0x3F;
4482 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4483 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4484 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4485 fragP->fr_fix += 2;
4486 break;
4487 case TAB (PCREL1632, LONG):
4488 /* Already set to mode 7.3; this indicates: PC indirect with
4489 suppressed index, 32-bit displacement. */
4490 *buffer_address++ = 0x01;
4491 *buffer_address++ = 0x70;
4492 fragP->fr_fix += 2;
4493 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4494 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4495 fixP->fx_pcrel_adjust = 2;
4496 fragP->fr_fix += 4;
4497 break;
4498 case TAB (PCINDEX, BYTE):
4499 assert (fragP->fr_fix >= 2);
4500 buffer_address[-2] &= ~1;
4501 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4502 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4503 fixP->fx_pcrel_adjust = 1;
4504 break;
4505 case TAB (PCINDEX, SHORT):
4506 assert (fragP->fr_fix >= 2);
4507 buffer_address[-2] |= 0x1;
4508 buffer_address[-1] = 0x20;
4509 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4510 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4511 fixP->fx_pcrel_adjust = 2;
4512 fragP->fr_fix += 2;
4513 break;
4514 case TAB (PCINDEX, LONG):
4515 assert (fragP->fr_fix >= 2);
4516 buffer_address[-2] |= 0x1;
4517 buffer_address[-1] = 0x30;
4518 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4519 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4520 fixP->fx_pcrel_adjust = 2;
4521 fragP->fr_fix += 4;
4522 break;
4523 case TAB (ABSTOPCREL, SHORT):
4524 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4525 1, RELAX_RELOC_PC16);
4526 fragP->fr_fix += 2;
4527 break;
4528 case TAB (ABSTOPCREL, LONG):
4529 /* The thing to do here is force it to ABSOLUTE LONG, since
4530 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4531 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4532 abort ();
4533 fragP->fr_opcode[1] &= ~0x3F;
4534 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4535 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4536 0, RELAX_RELOC_ABS32);
4537 fragP->fr_fix += 4;
4538 break;
4539 }
4540}
4541
4542#ifndef BFD_ASSEMBLER
4543
4544void
4545md_convert_frag (headers, sec, fragP)
4546 object_headers *headers ATTRIBUTE_UNUSED;
4547 segT sec ATTRIBUTE_UNUSED;
4548 fragS *fragP;
4549{
4550 md_convert_frag_1 (fragP);
4551}
4552
4553#else
4554
4555void
4556md_convert_frag (abfd, sec, fragP)
4557 bfd *abfd ATTRIBUTE_UNUSED;
4558 segT sec ATTRIBUTE_UNUSED;
4559 fragS *fragP;
4560{
4561 md_convert_frag_1 (fragP);
4562}
4563#endif
4564
4565/* Force truly undefined symbols to their maximum size, and generally set up
4566 the frag list to be relaxed
4567 */
4568int
4569md_estimate_size_before_relax (fragP, segment)
4570 register fragS *fragP;
4571 segT segment;
4572{
4573 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4574 switch (fragP->fr_subtype)
4575 {
4576 case TAB (BRANCHBWL, SZ_UNDEF):
4577 case TAB (BRABSJUNC, SZ_UNDEF):
4578 case TAB (BRABSJCOND, SZ_UNDEF):
4579 {
4580 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4581 && relaxable_symbol (fragP->fr_symbol))
4582 {
4583 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4584 }
4585 else if (flag_short_refs)
4586 {
4587 /* Symbol is undefined and we want short ref. */
4588 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4589 }
4590 else
4591 {
4592 /* Symbol is still undefined. Make it LONG. */
4593 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4594 }
4595 break;
4596 }
4597
4598 case TAB (BRANCHBW, SZ_UNDEF):
4599 {
4600 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4601 && relaxable_symbol (fragP->fr_symbol))
4602 {
4603 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4604 }
4605 else
4606 {
4607 /* Symbol is undefined and we don't have long branches. */
4608 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4609 }
4610 break;
4611 }
4612
4613 case TAB (FBRANCH, SZ_UNDEF):
4614 case TAB (DBCCLBR, SZ_UNDEF):
4615 case TAB (DBCCABSJ, SZ_UNDEF):
4616 case TAB (PCREL1632, SZ_UNDEF):
4617 {
4618 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4619 && relaxable_symbol (fragP->fr_symbol))
4620 || flag_short_refs)
4621 {
4622 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4623 }
4624 else
4625 {
4626 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4627 }
4628 break;
4629 }
4630
4631 case TAB (PCINDEX, SZ_UNDEF):
4632 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4633 && relaxable_symbol (fragP->fr_symbol)))
4634 {
4635 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4636 }
4637 else
4638 {
4639 fragP->fr_subtype = TAB (PCINDEX, LONG);
4640 }
4641 break;
4642
4643 case TAB (ABSTOPCREL, SZ_UNDEF):
4644 {
4645 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4646 && relaxable_symbol (fragP->fr_symbol)))
4647 {
4648 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4649 }
4650 else
4651 {
4652 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
4653 }
4654 break;
4655 }
4656
4657 default:
4658 break;
4659 }
4660
4661 /* Now that SZ_UNDEF are taken care of, check others. */
4662 switch (fragP->fr_subtype)
4663 {
4664 case TAB (BRANCHBWL, BYTE):
4665 case TAB (BRABSJUNC, BYTE):
4666 case TAB (BRABSJCOND, BYTE):
4667 case TAB (BRANCHBW, BYTE):
4668 /* We can't do a short jump to the next instruction, so in that
4669 case we force word mode. If the symbol is at the start of a
4670 frag, and it is the next frag with any data in it (usually
4671 this is just the next frag, but assembler listings may
4672 introduce empty frags), we must use word mode. */
4673 if (fragP->fr_symbol)
4674 {
4675 fragS *sym_frag;
4676
4677 sym_frag = symbol_get_frag (fragP->fr_symbol);
4678 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
4679 {
4680 fragS *l;
4681
4682 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
4683 if (l->fr_fix != 0)
4684 break;
4685 if (l == sym_frag)
4686 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4687 }
4688 }
4689 break;
4690 default:
4691 break;
4692 }
4693 return md_relax_table[fragP->fr_subtype].rlx_length;
4694}
4695
4696#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4697/* the bit-field entries in the relocation_info struct plays hell
4698 with the byte-order problems of cross-assembly. So as a hack,
4699 I added this mach. dependent ri twiddler. Ugly, but it gets
4700 you there. -KWK */
4701/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4702 are symbolnum, most sig. byte first. Last byte is broken up with
4703 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4704 nibble as nuthin. (on Sun 3 at least) */
4705/* Translate the internal relocation information into target-specific
4706 format. */
4707#ifdef comment
4708void
4709md_ri_to_chars (the_bytes, ri)
4710 char *the_bytes;
4711 struct reloc_info_generic *ri;
4712{
4713 /* this is easy */
4714 md_number_to_chars (the_bytes, ri->r_address, 4);
4715 /* now the fun stuff */
4716 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4717 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4718 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4719 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4720 ((ri->r_extern << 4) & 0x10));
4721}
4722
4723#endif /* comment */
4724
4725#ifndef BFD_ASSEMBLER
4726void
4727tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4728 char *where;
4729 fixS *fixP;
4730 relax_addressT segment_address_in_file;
4731{
4732 /*
4733 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4734 * Out: GNU LD relocation length code: 0, 1, or 2.
4735 */
4736
4737 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4738 long r_symbolnum;
4739
4740 know (fixP->fx_addsy != NULL);
4741
4742 md_number_to_chars (where,
4743 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4744 4);
4745
4746 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4747 ? S_GET_TYPE (fixP->fx_addsy)
4748 : fixP->fx_addsy->sy_number);
4749
4750 where[4] = (r_symbolnum >> 16) & 0x0ff;
4751 where[5] = (r_symbolnum >> 8) & 0x0ff;
4752 where[6] = r_symbolnum & 0x0ff;
4753 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4754 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4755}
4756#endif
4757
4758#endif /* OBJ_AOUT or OBJ_BOUT */
4759
4760#ifndef WORKING_DOT_WORD
4761const int md_short_jump_size = 4;
4762const int md_long_jump_size = 6;
4763
4764void
4765md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4766 char *ptr;
4767 addressT from_addr, to_addr;
4768 fragS *frag ATTRIBUTE_UNUSED;
4769 symbolS *to_symbol ATTRIBUTE_UNUSED;
4770{
4771 valueT offset;
4772
4773 offset = to_addr - (from_addr + 2);
4774
4775 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4776 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4777}
4778
4779void
4780md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4781 char *ptr;
4782 addressT from_addr, to_addr;
4783 fragS *frag;
4784 symbolS *to_symbol;
4785{
4786 valueT offset;
4787
4788 if (!HAVE_LONG_BRANCH(current_architecture))
4789 {
4790 offset = to_addr - S_GET_VALUE (to_symbol);
4791 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4792 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4793 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4794 0, NO_RELOC);
4795 }
4796 else
4797 {
4798 offset = to_addr - (from_addr + 2);
4799 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4800 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4801 }
4802}
4803
4804#endif
4805
4806/* Different values of OK tell what its OK to return. Things that
4807 aren't OK are an error (what a shock, no?)
4808
4809 0: Everything is OK
4810 10: Absolute 1:8 only
4811 20: Absolute 0:7 only
4812 30: absolute 0:15 only
4813 40: Absolute 0:31 only
4814 50: absolute 0:127 only
4815 55: absolute -64:63 only
4816 60: absolute -128:127 only
4817 70: absolute 0:4095 only
4818 80: No bignums
4819
4820 */
4821
4822static int
4823get_num (exp, ok)
4824 struct m68k_exp *exp;
4825 int ok;
4826{
4827 if (exp->exp.X_op == O_absent)
4828 {
4829 /* Do the same thing the VAX asm does */
4830 op (exp) = O_constant;
4831 adds (exp) = 0;
4832 subs (exp) = 0;
4833 offs (exp) = 0;
4834 if (ok == 10)
4835 {
4836 as_warn (_("expression out of range: defaulting to 1"));
4837 offs (exp) = 1;
4838 }
4839 }
4840 else if (exp->exp.X_op == O_constant)
4841 {
4842 switch (ok)
4843 {
4844 case 10:
4845 if (offs (exp) < 1 || offs (exp) > 8)
4846 {
4847 as_warn (_("expression out of range: defaulting to 1"));
4848 offs (exp) = 1;
4849 }
4850 break;
4851 case 20:
4852 if (offs (exp) < 0 || offs (exp) > 7)
4853 goto outrange;
4854 break;
4855 case 30:
4856 if (offs (exp) < 0 || offs (exp) > 15)
4857 goto outrange;
4858 break;
4859 case 40:
4860 if (offs (exp) < 0 || offs (exp) > 32)
4861 goto outrange;
4862 break;
4863 case 50:
4864 if (offs (exp) < 0 || offs (exp) > 127)
4865 goto outrange;
4866 break;
4867 case 55:
4868 if (offs (exp) < -64 || offs (exp) > 63)
4869 goto outrange;
4870 break;
4871 case 60:
4872 if (offs (exp) < -128 || offs (exp) > 127)
4873 goto outrange;
4874 break;
4875 case 70:
4876 if (offs (exp) < 0 || offs (exp) > 4095)
4877 {
4878 outrange:
4879 as_warn (_("expression out of range: defaulting to 0"));
4880 offs (exp) = 0;
4881 }
4882 break;
4883 default:
4884 break;
4885 }
4886 }
4887 else if (exp->exp.X_op == O_big)
4888 {
4889 if (offs (exp) <= 0 /* flonum */
4890 && (ok == 80 /* no bignums */
4891 || (ok > 10 /* small-int ranges including 0 ok */
4892 /* If we have a flonum zero, a zero integer should
4893 do as well (e.g., in moveq). */
4894 && generic_floating_point_number.exponent == 0
4895 && generic_floating_point_number.low[0] == 0)))
4896 {
4897 /* HACK! Turn it into a long */
4898 LITTLENUM_TYPE words[6];
4899
4900 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4901 op (exp) = O_constant;
4902 adds (exp) = 0;
4903 subs (exp) = 0;
4904 offs (exp) = words[1] | (words[0] << 16);
4905 }
4906 else if (ok != 0)
4907 {
4908 op (exp) = O_constant;
4909 adds (exp) = 0;
4910 subs (exp) = 0;
4911 offs (exp) = (ok == 10) ? 1 : 0;
4912 as_warn (_("Can't deal with expression; defaulting to %ld"),
4913 offs (exp));
4914 }
4915 }
4916 else
4917 {
4918 if (ok >= 10 && ok <= 70)
4919 {
4920 op (exp) = O_constant;
4921 adds (exp) = 0;
4922 subs (exp) = 0;
4923 offs (exp) = (ok == 10) ? 1 : 0;
4924 as_warn (_("Can't deal with expression; defaulting to %ld"),
4925 offs (exp));
4926 }
4927 }
4928
4929 if (exp->size != SIZE_UNSPEC)
4930 {
4931 switch (exp->size)
4932 {
4933 case SIZE_UNSPEC:
4934 case SIZE_LONG:
4935 break;
4936 case SIZE_BYTE:
4937 if (!isbyte (offs (exp)))
4938 as_warn (_("expression doesn't fit in BYTE"));
4939 break;
4940 case SIZE_WORD:
4941 if (!isword (offs (exp)))
4942 as_warn (_("expression doesn't fit in WORD"));
4943 break;
4944 }
4945 }
4946
4947 return offs (exp);
4948}
4949
4950/* These are the back-ends for the various machine dependent pseudo-ops. */
4951
4952static void
4953s_data1 (ignore)
4954 int ignore ATTRIBUTE_UNUSED;
4955{
4956 subseg_set (data_section, 1);
4957 demand_empty_rest_of_line ();
4958}
4959
4960static void
4961s_data2 (ignore)
4962 int ignore ATTRIBUTE_UNUSED;
4963{
4964 subseg_set (data_section, 2);
4965 demand_empty_rest_of_line ();
4966}
4967
4968static void
4969s_bss (ignore)
4970 int ignore ATTRIBUTE_UNUSED;
4971{
4972 /* We don't support putting frags in the BSS segment, we fake it
4973 by marking in_bss, then looking at s_skip for clues. */
4974
4975 subseg_set (bss_section, 0);
4976 demand_empty_rest_of_line ();
4977}
4978
4979static void
4980s_even (ignore)
4981 int ignore ATTRIBUTE_UNUSED;
4982{
4983 register int temp;
4984 register long temp_fill;
4985
4986 temp = 1; /* JF should be 2? */
4987 temp_fill = get_absolute_expression ();
4988 if (!need_pass_2) /* Never make frag if expect extra pass. */
4989 frag_align (temp, (int) temp_fill, 0);
4990 demand_empty_rest_of_line ();
4991 record_alignment (now_seg, temp);
4992}
4993
4994static void
4995s_proc (ignore)
4996 int ignore ATTRIBUTE_UNUSED;
4997{
4998 demand_empty_rest_of_line ();
4999}
5000
5001
5002/* Pseudo-ops handled for MRI compatibility. */
5003
5004/* This function returns non-zero if the argument is a conditional
5005 pseudo-op. This is called when checking whether a pending
5006 alignment is needed. */
5007
5008int
5009m68k_conditional_pseudoop (pop)
5010 pseudo_typeS *pop;
5011{
5012 return (pop->poc_handler == s_mri_if
5013 || pop->poc_handler == s_mri_else);
5014}
5015
5016/* Handle an MRI style chip specification. */
5017
5018static void
5019mri_chip ()
5020{
5021 char *s;
5022 char c;
5023 int i;
5024
5025 s = input_line_pointer;
5026 /* We can't use get_symbol_end since the processor names are not proper
5027 symbols. */
5028 while (is_part_of_name (c = *input_line_pointer++))
5029 ;
5030 *--input_line_pointer = 0;
5031 for (i = 0; i < n_archs; i++)
5032 if (strcasecmp (s, archs[i].name) == 0)
5033 break;
5034 if (i >= n_archs)
5035 {
5036 as_bad (_("%s: unrecognized processor name"), s);
5037 *input_line_pointer = c;
5038 ignore_rest_of_line ();
5039 return;
5040 }
5041 *input_line_pointer = c;
5042
5043 if (*input_line_pointer == '/')
5044 current_architecture = 0;
5045 else
5046 current_architecture &= m68881 | m68851;
5047 current_architecture |= archs[i].arch;
5048
5049 while (*input_line_pointer == '/')
5050 {
5051 ++input_line_pointer;
5052 s = input_line_pointer;
5053 /* We can't use get_symbol_end since the processor names are not
5054 proper symbols. */
5055 while (is_part_of_name (c = *input_line_pointer++))
5056 ;
5057 *--input_line_pointer = 0;
5058 if (strcmp (s, "68881") == 0)
5059 current_architecture |= m68881;
5060 else if (strcmp (s, "68851") == 0)
5061 current_architecture |= m68851;
5062 *input_line_pointer = c;
5063 }
5064
5065 /* Update info about available control registers. */
5066 select_control_regs ();
5067}
5068
5069/* The MRI CHIP pseudo-op. */
5070
5071static void
5072s_chip (ignore)
5073 int ignore ATTRIBUTE_UNUSED;
5074{
5075 char *stop = NULL;
5076 char stopc;
5077
5078 if (flag_mri)
5079 stop = mri_comment_field (&stopc);
5080 mri_chip ();
5081 if (flag_mri)
5082 mri_comment_end (stop, stopc);
5083 demand_empty_rest_of_line ();
5084}
5085
5086/* The MRI FOPT pseudo-op. */
5087
5088static void
5089s_fopt (ignore)
5090 int ignore ATTRIBUTE_UNUSED;
5091{
5092 SKIP_WHITESPACE ();
5093
5094 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5095 {
5096 int temp;
5097
5098 input_line_pointer += 3;
5099 temp = get_absolute_expression ();
5100 if (temp < 0 || temp > 7)
5101 as_bad (_("bad coprocessor id"));
5102 else
5103 m68k_float_copnum = COP0 + temp;
5104 }
5105 else
5106 {
5107 as_bad (_("unrecognized fopt option"));
5108 ignore_rest_of_line ();
5109 return;
5110 }
5111
5112 demand_empty_rest_of_line ();
5113}
5114
5115/* The structure used to handle the MRI OPT pseudo-op. */
5116
5117struct opt_action
5118{
5119 /* The name of the option. */
5120 const char *name;
5121
5122 /* If this is not NULL, just call this function. The first argument
5123 is the ARG field of this structure, the second argument is
5124 whether the option was negated. */
5125 void (*pfn) PARAMS ((int arg, int on));
5126
5127 /* If this is not NULL, and the PFN field is NULL, set the variable
5128 this points to. Set it to the ARG field if the option was not
5129 negated, and the NOTARG field otherwise. */
5130 int *pvar;
5131
5132 /* The value to pass to PFN or to assign to *PVAR. */
5133 int arg;
5134
5135 /* The value to assign to *PVAR if the option is negated. If PFN is
5136 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5137 the option may not be negated. */
5138 int notarg;
5139};
5140
5141/* The table used to handle the MRI OPT pseudo-op. */
5142
5143static void skip_to_comma PARAMS ((int, int));
5144static void opt_nest PARAMS ((int, int));
5145static void opt_chip PARAMS ((int, int));
5146static void opt_list PARAMS ((int, int));
5147static void opt_list_symbols PARAMS ((int, int));
5148
5149static const struct opt_action opt_table[] =
5150{
5151 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5152
5153 /* We do relaxing, so there is little use for these options. */
5154 { "b", 0, 0, 0, 0 },
5155 { "brs", 0, 0, 0, 0 },
5156 { "brb", 0, 0, 0, 0 },
5157 { "brl", 0, 0, 0, 0 },
5158 { "brw", 0, 0, 0, 0 },
5159
5160 { "c", 0, 0, 0, 0 },
5161 { "cex", 0, 0, 0, 0 },
5162 { "case", 0, &symbols_case_sensitive, 1, 0 },
5163 { "cl", 0, 0, 0, 0 },
5164 { "cre", 0, 0, 0, 0 },
5165 { "d", 0, &flag_keep_locals, 1, 0 },
5166 { "e", 0, 0, 0, 0 },
5167 { "f", 0, &flag_short_refs, 1, 0 },
5168 { "frs", 0, &flag_short_refs, 1, 0 },
5169 { "frl", 0, &flag_short_refs, 0, 1 },
5170 { "g", 0, 0, 0, 0 },
5171 { "i", 0, 0, 0, 0 },
5172 { "m", 0, 0, 0, 0 },
5173 { "mex", 0, 0, 0, 0 },
5174 { "mc", 0, 0, 0, 0 },
5175 { "md", 0, 0, 0, 0 },
5176 { "nest", opt_nest, 0, 0, 0 },
5177 { "next", skip_to_comma, 0, 0, 0 },
5178 { "o", 0, 0, 0, 0 },
5179 { "old", 0, 0, 0, 0 },
5180 { "op", skip_to_comma, 0, 0, 0 },
5181 { "pco", 0, 0, 0, 0 },
5182 { "p", opt_chip, 0, 0, 0 },
5183 { "pcr", 0, 0, 0, 0 },
5184 { "pcs", 0, 0, 0, 0 },
5185 { "r", 0, 0, 0, 0 },
5186 { "quick", 0, &m68k_quick, 1, 0 },
5187 { "rel32", 0, &m68k_rel32, 1, 0 },
5188 { "s", opt_list, 0, 0, 0 },
5189 { "t", opt_list_symbols, 0, 0, 0 },
5190 { "w", 0, &flag_no_warnings, 0, 1 },
5191 { "x", 0, 0, 0, 0 }
5192};
5193
5194#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5195
5196/* The MRI OPT pseudo-op. */
5197
5198static void
5199s_opt (ignore)
5200 int ignore ATTRIBUTE_UNUSED;
5201{
5202 do
5203 {
5204 int t;
5205 char *s;
5206 char c;
5207 int i;
5208 const struct opt_action *o;
5209
5210 SKIP_WHITESPACE ();
5211
5212 t = 1;
5213 if (*input_line_pointer == '-')
5214 {
5215 ++input_line_pointer;
5216 t = 0;
5217 }
5218 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5219 {
5220 input_line_pointer += 2;
5221 t = 0;
5222 }
5223
5224 s = input_line_pointer;
5225 c = get_symbol_end ();
5226
5227 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5228 {
5229 if (strcasecmp (s, o->name) == 0)
5230 {
5231 if (o->pfn)
5232 {
5233 /* Restore input_line_pointer now in case the option
5234 takes arguments. */
5235 *input_line_pointer = c;
5236 (*o->pfn) (o->arg, t);
5237 }
5238 else if (o->pvar != NULL)
5239 {
5240 if (! t && o->arg == o->notarg)
5241 as_bad (_("option `%s' may not be negated"), s);
5242 *input_line_pointer = c;
5243 *o->pvar = t ? o->arg : o->notarg;
5244 }
5245 else
5246 *input_line_pointer = c;
5247 break;
5248 }
5249 }
5250 if (i >= OPTCOUNT)
5251 {
5252 as_bad (_("option `%s' not recognized"), s);
5253 *input_line_pointer = c;
5254 }
5255 }
5256 while (*input_line_pointer++ == ',');
5257
5258 /* Move back to terminating character. */
5259 --input_line_pointer;
5260 demand_empty_rest_of_line ();
5261}
5262
5263/* Skip ahead to a comma. This is used for OPT options which we do
5264 not suppor tand which take arguments. */
5265
5266static void
5267skip_to_comma (arg, on)
5268 int arg ATTRIBUTE_UNUSED;
5269 int on ATTRIBUTE_UNUSED;
5270{
5271 while (*input_line_pointer != ','
5272 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5273 ++input_line_pointer;
5274}
5275
5276/* Handle the OPT NEST=depth option. */
5277
5278static void
5279opt_nest (arg, on)
5280 int arg ATTRIBUTE_UNUSED;
5281 int on ATTRIBUTE_UNUSED;
5282{
5283 if (*input_line_pointer != '=')
5284 {
5285 as_bad (_("bad format of OPT NEST=depth"));
5286 return;
5287 }
5288
5289 ++input_line_pointer;
5290 max_macro_nest = get_absolute_expression ();
5291}
5292
5293/* Handle the OPT P=chip option. */
5294
5295static void
5296opt_chip (arg, on)
5297 int arg ATTRIBUTE_UNUSED;
5298 int on ATTRIBUTE_UNUSED;
5299{
5300 if (*input_line_pointer != '=')
5301 {
5302 /* This is just OPT P, which we do not support. */
5303 return;
5304 }
5305
5306 ++input_line_pointer;
5307 mri_chip ();
5308}
5309
5310/* Handle the OPT S option. */
5311
5312static void
5313opt_list (arg, on)
5314 int arg ATTRIBUTE_UNUSED;
5315 int on;
5316{
5317 listing_list (on);
5318}
5319
5320/* Handle the OPT T option. */
5321
5322static void
5323opt_list_symbols (arg, on)
5324 int arg ATTRIBUTE_UNUSED;
5325 int on;
5326{
5327 if (on)
5328 listing |= LISTING_SYMBOLS;
5329 else
5330 listing &= ~LISTING_SYMBOLS;
5331}
5332
5333/* Handle the MRI REG pseudo-op. */
5334
5335static void
5336s_reg (ignore)
5337 int ignore ATTRIBUTE_UNUSED;
5338{
5339 char *s;
5340 int c;
5341 struct m68k_op rop;
5342 int mask;
5343 char *stop = NULL;
5344 char stopc;
5345
5346 if (line_label == NULL)
5347 {
5348 as_bad (_("missing label"));
5349 ignore_rest_of_line ();
5350 return;
5351 }
5352
5353 if (flag_mri)
5354 stop = mri_comment_field (&stopc);
5355
5356 SKIP_WHITESPACE ();
5357
5358 s = input_line_pointer;
5359 while (ISALNUM (*input_line_pointer)
5360#ifdef REGISTER_PREFIX
5361 || *input_line_pointer == REGISTER_PREFIX
5362#endif
5363 || *input_line_pointer == '/'
5364 || *input_line_pointer == '-')
5365 ++input_line_pointer;
5366 c = *input_line_pointer;
5367 *input_line_pointer = '\0';
5368
5369 if (m68k_ip_op (s, &rop) != 0)
5370 {
5371 if (rop.error == NULL)
5372 as_bad (_("bad register list"));
5373 else
5374 as_bad (_("bad register list: %s"), rop.error);
5375 *input_line_pointer = c;
5376 ignore_rest_of_line ();
5377 return;
5378 }
5379
5380 *input_line_pointer = c;
5381
5382 if (rop.mode == REGLST)
5383 mask = rop.mask;
5384 else if (rop.mode == DREG)
5385 mask = 1 << (rop.reg - DATA0);
5386 else if (rop.mode == AREG)
5387 mask = 1 << (rop.reg - ADDR0 + 8);
5388 else if (rop.mode == FPREG)
5389 mask = 1 << (rop.reg - FP0 + 16);
5390 else if (rop.mode == CONTROL
5391 && rop.reg == FPI)
5392 mask = 1 << 24;
5393 else if (rop.mode == CONTROL
5394 && rop.reg == FPS)
5395 mask = 1 << 25;
5396 else if (rop.mode == CONTROL
5397 && rop.reg == FPC)
5398 mask = 1 << 26;
5399 else
5400 {
5401 as_bad (_("bad register list"));
5402 ignore_rest_of_line ();
5403 return;
5404 }
5405
5406 S_SET_SEGMENT (line_label, reg_section);
5407 S_SET_VALUE (line_label, ~mask);
5408 symbol_set_frag (line_label, &zero_address_frag);
5409
5410 if (flag_mri)
5411 mri_comment_end (stop, stopc);
5412
5413 demand_empty_rest_of_line ();
5414}
5415
5416/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5417
5418struct save_opts
5419{
5420 struct save_opts *next;
5421 int abspcadd;
5422 int symbols_case_sensitive;
5423 int keep_locals;
5424 int short_refs;
5425 int architecture;
5426 int quick;
5427 int rel32;
5428 int listing;
5429 int no_warnings;
5430 /* FIXME: We don't save OPT S. */
5431};
5432
5433/* This variable holds the stack of saved options. */
5434
5435static struct save_opts *save_stack;
5436
5437/* The MRI SAVE pseudo-op. */
5438
5439static void
5440s_save (ignore)
5441 int ignore ATTRIBUTE_UNUSED;
5442{
5443 struct save_opts *s;
5444
5445 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5446 s->abspcadd = m68k_abspcadd;
5447 s->symbols_case_sensitive = symbols_case_sensitive;
5448 s->keep_locals = flag_keep_locals;
5449 s->short_refs = flag_short_refs;
5450 s->architecture = current_architecture;
5451 s->quick = m68k_quick;
5452 s->rel32 = m68k_rel32;
5453 s->listing = listing;
5454 s->no_warnings = flag_no_warnings;
5455
5456 s->next = save_stack;
5457 save_stack = s;
5458
5459 demand_empty_rest_of_line ();
5460}
5461
5462/* The MRI RESTORE pseudo-op. */
5463
5464static void
5465s_restore (ignore)
5466 int ignore ATTRIBUTE_UNUSED;
5467{
5468 struct save_opts *s;
5469
5470 if (save_stack == NULL)
5471 {
5472 as_bad (_("restore without save"));
5473 ignore_rest_of_line ();
5474 return;
5475 }
5476
5477 s = save_stack;
5478 save_stack = s->next;
5479
5480 m68k_abspcadd = s->abspcadd;
5481 symbols_case_sensitive = s->symbols_case_sensitive;
5482 flag_keep_locals = s->keep_locals;
5483 flag_short_refs = s->short_refs;
5484 current_architecture = s->architecture;
5485 m68k_quick = s->quick;
5486 m68k_rel32 = s->rel32;
5487 listing = s->listing;
5488 flag_no_warnings = s->no_warnings;
5489
5490 free (s);
5491
5492 demand_empty_rest_of_line ();
5493}
5494
5495/* Types of MRI structured control directives. */
5496
5497enum mri_control_type
5498{
5499 mri_for,
5500 mri_if,
5501 mri_repeat,
5502 mri_while
5503};
5504
5505/* This structure is used to stack the MRI structured control
5506 directives. */
5507
5508struct mri_control_info
5509{
5510 /* The directive within which this one is enclosed. */
5511 struct mri_control_info *outer;
5512
5513 /* The type of directive. */
5514 enum mri_control_type type;
5515
5516 /* Whether an ELSE has been in an IF. */
5517 int else_seen;
5518
5519 /* The add or sub statement at the end of a FOR. */
5520 char *incr;
5521
5522 /* The label of the top of a FOR or REPEAT loop. */
5523 char *top;
5524
5525 /* The label to jump to for the next iteration, or the else
5526 expression of a conditional. */
5527 char *next;
5528
5529 /* The label to jump to to break out of the loop, or the label past
5530 the end of a conditional. */
5531 char *bottom;
5532};
5533
5534/* The stack of MRI structured control directives. */
5535
5536static struct mri_control_info *mri_control_stack;
5537
5538/* The current MRI structured control directive index number, used to
5539 generate label names. */
5540
5541static int mri_control_index;
5542
5543/* Some function prototypes. */
5544
5545static void mri_assemble PARAMS ((char *));
5546static char *mri_control_label PARAMS ((void));
5547static struct mri_control_info *push_mri_control
5548 PARAMS ((enum mri_control_type));
5549static void pop_mri_control PARAMS ((void));
5550static int parse_mri_condition PARAMS ((int *));
5551static int parse_mri_control_operand
5552 PARAMS ((int *, char **, char **, char **, char **));
5553static int swap_mri_condition PARAMS ((int));
5554static int reverse_mri_condition PARAMS ((int));
5555static void build_mri_control_operand
5556 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5557 const char *, int));
5558static void parse_mri_control_expression
5559 PARAMS ((char *, int, const char *, const char *, int));
5560
5561/* Assemble an instruction for an MRI structured control directive. */
5562
5563static void
5564mri_assemble (str)
5565 char *str;
5566{
5567 char *s;
5568
5569 /* md_assemble expects the opcode to be in lower case. */
5570 for (s = str; *s != ' ' && *s != '\0'; s++)
5571 *s = TOLOWER (*s);
5572
5573 md_assemble (str);
5574}
5575
5576/* Generate a new MRI label structured control directive label name. */
5577
5578static char *
5579mri_control_label ()
5580{
5581 char *n;
5582
5583 n = (char *) xmalloc (20);
5584 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5585 ++mri_control_index;
5586 return n;
5587}
5588
5589/* Create a new MRI structured control directive. */
5590
5591static struct mri_control_info *
5592push_mri_control (type)
5593 enum mri_control_type type;
5594{
5595 struct mri_control_info *n;
5596
5597 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5598
5599 n->type = type;
5600 n->else_seen = 0;
5601 if (type == mri_if || type == mri_while)
5602 n->top = NULL;
5603 else
5604 n->top = mri_control_label ();
5605 n->next = mri_control_label ();
5606 n->bottom = mri_control_label ();
5607
5608 n->outer = mri_control_stack;
5609 mri_control_stack = n;
5610
5611 return n;
5612}
5613
5614/* Pop off the stack of MRI structured control directives. */
5615
5616static void
5617pop_mri_control ()
5618{
5619 struct mri_control_info *n;
5620
5621 n = mri_control_stack;
5622 mri_control_stack = n->outer;
5623 if (n->top != NULL)
5624 free (n->top);
5625 free (n->next);
5626 free (n->bottom);
5627 free (n);
5628}
5629
5630/* Recognize a condition code in an MRI structured control expression. */
5631
5632static int
5633parse_mri_condition (pcc)
5634 int *pcc;
5635{
5636 char c1, c2;
5637
5638 know (*input_line_pointer == '<');
5639
5640 ++input_line_pointer;
5641 c1 = *input_line_pointer++;
5642 c2 = *input_line_pointer++;
5643
5644 if (*input_line_pointer != '>')
5645 {
5646 as_bad (_("syntax error in structured control directive"));
5647 return 0;
5648 }
5649
5650 ++input_line_pointer;
5651 SKIP_WHITESPACE ();
5652
5653 c1 = TOLOWER (c1);
5654 c2 = TOLOWER (c2);
5655
5656 *pcc = (c1 << 8) | c2;
5657
5658 return 1;
5659}
5660
5661/* Parse a single operand in an MRI structured control expression. */
5662
5663static int
5664parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5665 int *pcc;
5666 char **leftstart;
5667 char **leftstop;
5668 char **rightstart;
5669 char **rightstop;
5670{
5671 char *s;
5672
5673 SKIP_WHITESPACE ();
5674
5675 *pcc = -1;
5676 *leftstart = NULL;
5677 *leftstop = NULL;
5678 *rightstart = NULL;
5679 *rightstop = NULL;
5680
5681 if (*input_line_pointer == '<')
5682 {
5683 /* It's just a condition code. */
5684 return parse_mri_condition (pcc);
5685 }
5686
5687 /* Look ahead for the condition code. */
5688 for (s = input_line_pointer; *s != '\0'; ++s)
5689 {
5690 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5691 break;
5692 }
5693 if (*s == '\0')
5694 {
5695 as_bad (_("missing condition code in structured control directive"));
5696 return 0;
5697 }
5698
5699 *leftstart = input_line_pointer;
5700 *leftstop = s;
5701 if (*leftstop > *leftstart
5702 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5703 --*leftstop;
5704
5705 input_line_pointer = s;
5706 if (! parse_mri_condition (pcc))
5707 return 0;
5708
5709 /* Look ahead for AND or OR or end of line. */
5710 for (s = input_line_pointer; *s != '\0'; ++s)
5711 {
5712 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5713 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5714 ^^^ ^^ */
5715 if ((s == input_line_pointer
5716 || *(s-1) == ' '
5717 || *(s-1) == '\t')
5718 && ((strncasecmp (s, "AND", 3) == 0
5719 && (s[3] == '.' || ! is_part_of_name (s[3])))
5720 || (strncasecmp (s, "OR", 2) == 0
5721 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5722 break;
5723 }
5724
5725 *rightstart = input_line_pointer;
5726 *rightstop = s;
5727 if (*rightstop > *rightstart
5728 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5729 --*rightstop;
5730
5731 input_line_pointer = s;
5732
5733 return 1;
5734}
5735
5736#define MCC(b1, b2) (((b1) << 8) | (b2))
5737
5738/* Swap the sense of a condition. This changes the condition so that
5739 it generates the same result when the operands are swapped. */
5740
5741static int
5742swap_mri_condition (cc)
5743 int cc;
5744{
5745 switch (cc)
5746 {
5747 case MCC ('h', 'i'): return MCC ('c', 's');
5748 case MCC ('l', 's'): return MCC ('c', 'c');
5749 /* <HS> is an alias for <CC> */
5750 case MCC ('h', 's'):
5751 case MCC ('c', 'c'): return MCC ('l', 's');
5752 /* <LO> is an alias for <CS> */
5753 case MCC ('l', 'o'):
5754 case MCC ('c', 's'): return MCC ('h', 'i');
5755 case MCC ('p', 'l'): return MCC ('m', 'i');
5756 case MCC ('m', 'i'): return MCC ('p', 'l');
5757 case MCC ('g', 'e'): return MCC ('l', 'e');
5758 case MCC ('l', 't'): return MCC ('g', 't');
5759 case MCC ('g', 't'): return MCC ('l', 't');
5760 case MCC ('l', 'e'): return MCC ('g', 'e');
5761 /* issue a warning for conditions we can not swap */
5762 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5763 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5764 case MCC ('v', 'c'):
5765 case MCC ('v', 's'):
5766 default :
5767 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5768 (char) (cc >> 8), (char) (cc));
5769 break;
5770 }
5771 return cc;
5772}
5773
5774/* Reverse the sense of a condition. */
5775
5776static int
5777reverse_mri_condition (cc)
5778 int cc;
5779{
5780 switch (cc)
5781 {
5782 case MCC ('h', 'i'): return MCC ('l', 's');
5783 case MCC ('l', 's'): return MCC ('h', 'i');
5784 /* <HS> is an alias for <CC> */
5785 case MCC ('h', 's'): return MCC ('l', 'o');
5786 case MCC ('c', 'c'): return MCC ('c', 's');
5787 /* <LO> is an alias for <CS> */
5788 case MCC ('l', 'o'): return MCC ('h', 's');
5789 case MCC ('c', 's'): return MCC ('c', 'c');
5790 case MCC ('n', 'e'): return MCC ('e', 'q');
5791 case MCC ('e', 'q'): return MCC ('n', 'e');
5792 case MCC ('v', 'c'): return MCC ('v', 's');
5793 case MCC ('v', 's'): return MCC ('v', 'c');
5794 case MCC ('p', 'l'): return MCC ('m', 'i');
5795 case MCC ('m', 'i'): return MCC ('p', 'l');
5796 case MCC ('g', 'e'): return MCC ('l', 't');
5797 case MCC ('l', 't'): return MCC ('g', 'e');
5798 case MCC ('g', 't'): return MCC ('l', 'e');
5799 case MCC ('l', 'e'): return MCC ('g', 't');
5800 }
5801 return cc;
5802}
5803
5804/* Build an MRI structured control expression. This generates test
5805 and branch instructions. It goes to TRUELAB if the condition is
5806 true, and to FALSELAB if the condition is false. Exactly one of
5807 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5808 is the size qualifier for the expression. EXTENT is the size to
5809 use for the branch. */
5810
5811static void
5812build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5813 rightstop, truelab, falselab, extent)
5814 int qual;
5815 int cc;
5816 char *leftstart;
5817 char *leftstop;
5818 char *rightstart;
5819 char *rightstop;
5820 const char *truelab;
5821 const char *falselab;
5822 int extent;
5823{
5824 char *buf;
5825 char *s;
5826
5827 if (leftstart != NULL)
5828 {
5829 struct m68k_op leftop, rightop;
5830 char c;
5831
5832 /* Swap the compare operands, if necessary, to produce a legal
5833 m68k compare instruction. Comparing a register operand with
5834 a non-register operand requires the register to be on the
5835 right (cmp, cmpa). Comparing an immediate value with
5836 anything requires the immediate value to be on the left
5837 (cmpi). */
5838
5839 c = *leftstop;
5840 *leftstop = '\0';
5841 (void) m68k_ip_op (leftstart, &leftop);
5842 *leftstop = c;
5843
5844 c = *rightstop;
5845 *rightstop = '\0';
5846 (void) m68k_ip_op (rightstart, &rightop);
5847 *rightstop = c;
5848
5849 if (rightop.mode == IMMED
5850 || ((leftop.mode == DREG || leftop.mode == AREG)
5851 && (rightop.mode != DREG && rightop.mode != AREG)))
5852 {
5853 char *temp;
5854
5855 /* Correct conditional handling:
5856 if #1 <lt> d0 then ;means if (1 < d0)
5857 ...
5858 endi
5859
5860 should assemble to:
5861
5862 cmp #1,d0 if we do *not* swap the operands
5863 bgt true we need the swapped condition!
5864 ble false
5865 true:
5866 ...
5867 false:
5868 */
5869 temp = leftstart;
5870 leftstart = rightstart;
5871 rightstart = temp;
5872 temp = leftstop;
5873 leftstop = rightstop;
5874 rightstop = temp;
5875 }
5876 else
5877 {
5878 cc = swap_mri_condition (cc);
5879 }
5880 }
5881
5882 if (truelab == NULL)
5883 {
5884 cc = reverse_mri_condition (cc);
5885 truelab = falselab;
5886 }
5887
5888 if (leftstart != NULL)
5889 {
5890 buf = (char *) xmalloc (20
5891 + (leftstop - leftstart)
5892 + (rightstop - rightstart));
5893 s = buf;
5894 *s++ = 'c';
5895 *s++ = 'm';
5896 *s++ = 'p';
5897 if (qual != '\0')
5898 *s++ = TOLOWER (qual);
5899 *s++ = ' ';
5900 memcpy (s, leftstart, leftstop - leftstart);
5901 s += leftstop - leftstart;
5902 *s++ = ',';
5903 memcpy (s, rightstart, rightstop - rightstart);
5904 s += rightstop - rightstart;
5905 *s = '\0';
5906 mri_assemble (buf);
5907 free (buf);
5908 }
5909
5910 buf = (char *) xmalloc (20 + strlen (truelab));
5911 s = buf;
5912 *s++ = 'b';
5913 *s++ = cc >> 8;
5914 *s++ = cc & 0xff;
5915 if (extent != '\0')
5916 *s++ = TOLOWER (extent);
5917 *s++ = ' ';
5918 strcpy (s, truelab);
5919 mri_assemble (buf);
5920 free (buf);
5921}
5922
5923/* Parse an MRI structured control expression. This generates test
5924 and branch instructions. STOP is where the expression ends. It
5925 goes to TRUELAB if the condition is true, and to FALSELAB if the
5926 condition is false. Exactly one of TRUELAB and FALSELAB will be
5927 NULL, meaning to fall through. QUAL is the size qualifier for the
5928 expression. EXTENT is the size to use for the branch. */
5929
5930static void
5931parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5932 char *stop;
5933 int qual;
5934 const char *truelab;
5935 const char *falselab;
5936 int extent;
5937{
5938 int c;
5939 int cc;
5940 char *leftstart;
5941 char *leftstop;
5942 char *rightstart;
5943 char *rightstop;
5944
5945 c = *stop;
5946 *stop = '\0';
5947
5948 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5949 &rightstart, &rightstop))
5950 {
5951 *stop = c;
5952 return;
5953 }
5954
5955 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5956 {
5957 const char *flab;
5958
5959 if (falselab != NULL)
5960 flab = falselab;
5961 else
5962 flab = mri_control_label ();
5963
5964 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5965 rightstop, (const char *) NULL, flab, extent);
5966
5967 input_line_pointer += 3;
5968 if (*input_line_pointer != '.'
5969 || input_line_pointer[1] == '\0')
5970 qual = '\0';
5971 else
5972 {
5973 qual = input_line_pointer[1];
5974 input_line_pointer += 2;
5975 }
5976
5977 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5978 &rightstart, &rightstop))
5979 {
5980 *stop = c;
5981 return;
5982 }
5983
5984 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5985 rightstop, truelab, falselab, extent);
5986
5987 if (falselab == NULL)
5988 colon (flab);
5989 }
5990 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5991 {
5992 const char *tlab;
5993
5994 if (truelab != NULL)
5995 tlab = truelab;
5996 else
5997 tlab = mri_control_label ();
5998
5999 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6000 rightstop, tlab, (const char *) NULL, extent);
6001
6002 input_line_pointer += 2;
6003 if (*input_line_pointer != '.'
6004 || input_line_pointer[1] == '\0')
6005 qual = '\0';
6006 else
6007 {
6008 qual = input_line_pointer[1];
6009 input_line_pointer += 2;
6010 }
6011
6012 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6013 &rightstart, &rightstop))
6014 {
6015 *stop = c;
6016 return;
6017 }
6018
6019 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6020 rightstop, truelab, falselab, extent);
6021
6022 if (truelab == NULL)
6023 colon (tlab);
6024 }
6025 else
6026 {
6027 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6028 rightstop, truelab, falselab, extent);
6029 }
6030
6031 *stop = c;
6032 if (input_line_pointer != stop)
6033 as_bad (_("syntax error in structured control directive"));
6034}
6035
6036/* Handle the MRI IF pseudo-op. This may be a structured control
6037 directive, or it may be a regular assembler conditional, depending
6038 on its operands. */
6039
6040static void
6041s_mri_if (qual)
6042 int qual;
6043{
6044 char *s;
6045 int c;
6046 struct mri_control_info *n;
6047
6048 /* A structured control directive must end with THEN with an
6049 optional qualifier. */
6050 s = input_line_pointer;
6051 /* We only accept '*' as introduction of comments if preceded by white space
6052 or at first column of a line (I think this can't actually happen here?)
6053 This is important when assembling:
6054 if d0 <ne> 12(a0,d0*2) then
6055 if d0 <ne> #CONST*20 then */
6056 while ( ! ( is_end_of_line[(unsigned char) *s]
6057 || ( flag_mri
6058 && *s == '*'
6059 && ( s == input_line_pointer
6060 || *(s-1) == ' '
6061 || *(s-1) == '\t'))))
6062 ++s;
6063 --s;
6064 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6065 --s;
6066
6067 if (s - input_line_pointer > 1
6068 && s[-1] == '.')
6069 s -= 2;
6070
6071 if (s - input_line_pointer < 3
6072 || strncasecmp (s - 3, "THEN", 4) != 0)
6073 {
6074 if (qual != '\0')
6075 {
6076 as_bad (_("missing then"));
6077 ignore_rest_of_line ();
6078 return;
6079 }
6080
6081 /* It's a conditional. */
6082 s_if (O_ne);
6083 return;
6084 }
6085
6086 /* Since this might be a conditional if, this pseudo-op will be
6087 called even if we are supported to be ignoring input. Double
6088 check now. Clobber *input_line_pointer so that ignore_input
6089 thinks that this is not a special pseudo-op. */
6090 c = *input_line_pointer;
6091 *input_line_pointer = 0;
6092 if (ignore_input ())
6093 {
6094 *input_line_pointer = c;
6095 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6096 ++input_line_pointer;
6097 demand_empty_rest_of_line ();
6098 return;
6099 }
6100 *input_line_pointer = c;
6101
6102 n = push_mri_control (mri_if);
6103
6104 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6105 n->next, s[1] == '.' ? s[2] : '\0');
6106
6107 if (s[1] == '.')
6108 input_line_pointer = s + 3;
6109 else
6110 input_line_pointer = s + 1;
6111
6112 if (flag_mri)
6113 {
6114 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6115 ++input_line_pointer;
6116 }
6117
6118 demand_empty_rest_of_line ();
6119}
6120
6121/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6122 structured IF, associate the ELSE with the IF. Otherwise, assume
6123 it is a conditional else. */
6124
6125static void
6126s_mri_else (qual)
6127 int qual;
6128{
6129 int c;
6130 char *buf;
6131 char q[2];
6132
6133 if (qual == '\0'
6134 && (mri_control_stack == NULL
6135 || mri_control_stack->type != mri_if
6136 || mri_control_stack->else_seen))
6137 {
6138 s_else (0);
6139 return;
6140 }
6141
6142 c = *input_line_pointer;
6143 *input_line_pointer = 0;
6144 if (ignore_input ())
6145 {
6146 *input_line_pointer = c;
6147 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6148 ++input_line_pointer;
6149 demand_empty_rest_of_line ();
6150 return;
6151 }
6152 *input_line_pointer = c;
6153
6154 if (mri_control_stack == NULL
6155 || mri_control_stack->type != mri_if
6156 || mri_control_stack->else_seen)
6157 {
6158 as_bad (_("else without matching if"));
6159 ignore_rest_of_line ();
6160 return;
6161 }
6162
6163 mri_control_stack->else_seen = 1;
6164
6165 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6166 q[0] = TOLOWER (qual);
6167 q[1] = '\0';
6168 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6169 mri_assemble (buf);
6170 free (buf);
6171
6172 colon (mri_control_stack->next);
6173
6174 if (flag_mri)
6175 {
6176 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6177 ++input_line_pointer;
6178 }
6179
6180 demand_empty_rest_of_line ();
6181}
6182
6183/* Handle the MRI ENDI pseudo-op. */
6184
6185static void
6186s_mri_endi (ignore)
6187 int ignore ATTRIBUTE_UNUSED;
6188{
6189 if (mri_control_stack == NULL
6190 || mri_control_stack->type != mri_if)
6191 {
6192 as_bad (_("endi without matching if"));
6193 ignore_rest_of_line ();
6194 return;
6195 }
6196
6197 /* ignore_input will not return true for ENDI, so we don't need to
6198 worry about checking it again here. */
6199
6200 if (! mri_control_stack->else_seen)
6201 colon (mri_control_stack->next);
6202 colon (mri_control_stack->bottom);
6203
6204 pop_mri_control ();
6205
6206 if (flag_mri)
6207 {
6208 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6209 ++input_line_pointer;
6210 }
6211
6212 demand_empty_rest_of_line ();
6213}
6214
6215/* Handle the MRI BREAK pseudo-op. */
6216
6217static void
6218s_mri_break (extent)
6219 int extent;
6220{
6221 struct mri_control_info *n;
6222 char *buf;
6223 char ex[2];
6224
6225 n = mri_control_stack;
6226 while (n != NULL
6227 && n->type != mri_for
6228 && n->type != mri_repeat
6229 && n->type != mri_while)
6230 n = n->outer;
6231 if (n == NULL)
6232 {
6233 as_bad (_("break outside of structured loop"));
6234 ignore_rest_of_line ();
6235 return;
6236 }
6237
6238 buf = (char *) xmalloc (20 + strlen (n->bottom));
6239 ex[0] = TOLOWER (extent);
6240 ex[1] = '\0';
6241 sprintf (buf, "bra%s %s", ex, n->bottom);
6242 mri_assemble (buf);
6243 free (buf);
6244
6245 if (flag_mri)
6246 {
6247 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6248 ++input_line_pointer;
6249 }
6250
6251 demand_empty_rest_of_line ();
6252}
6253
6254/* Handle the MRI NEXT pseudo-op. */
6255
6256static void
6257s_mri_next (extent)
6258 int extent;
6259{
6260 struct mri_control_info *n;
6261 char *buf;
6262 char ex[2];
6263
6264 n = mri_control_stack;
6265 while (n != NULL
6266 && n->type != mri_for
6267 && n->type != mri_repeat
6268 && n->type != mri_while)
6269 n = n->outer;
6270 if (n == NULL)
6271 {
6272 as_bad (_("next outside of structured loop"));
6273 ignore_rest_of_line ();
6274 return;
6275 }
6276
6277 buf = (char *) xmalloc (20 + strlen (n->next));
6278 ex[0] = TOLOWER (extent);
6279 ex[1] = '\0';
6280 sprintf (buf, "bra%s %s", ex, n->next);
6281 mri_assemble (buf);
6282 free (buf);
6283
6284 if (flag_mri)
6285 {
6286 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6287 ++input_line_pointer;
6288 }
6289
6290 demand_empty_rest_of_line ();
6291}
6292
6293/* Handle the MRI FOR pseudo-op. */
6294
6295static void
6296s_mri_for (qual)
6297 int qual;
6298{
6299 const char *varstart, *varstop;
6300 const char *initstart, *initstop;
6301 const char *endstart, *endstop;
6302 const char *bystart, *bystop;
6303 int up;
6304 int by;
6305 int extent;
6306 struct mri_control_info *n;
6307 char *buf;
6308 char *s;
6309 char ex[2];
6310
6311 /* The syntax is
6312 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6313 */
6314
6315 SKIP_WHITESPACE ();
6316 varstart = input_line_pointer;
6317
6318 /* Look for the '='. */
6319 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6320 && *input_line_pointer != '=')
6321 ++input_line_pointer;
6322 if (*input_line_pointer != '=')
6323 {
6324 as_bad (_("missing ="));
6325 ignore_rest_of_line ();
6326 return;
6327 }
6328
6329 varstop = input_line_pointer;
6330 if (varstop > varstart
6331 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6332 --varstop;
6333
6334 ++input_line_pointer;
6335
6336 initstart = input_line_pointer;
6337
6338 /* Look for TO or DOWNTO. */
6339 up = 1;
6340 initstop = NULL;
6341 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6342 {
6343 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6344 && ! is_part_of_name (input_line_pointer[2]))
6345 {
6346 initstop = input_line_pointer;
6347 input_line_pointer += 2;
6348 break;
6349 }
6350 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6351 && ! is_part_of_name (input_line_pointer[6]))
6352 {
6353 initstop = input_line_pointer;
6354 up = 0;
6355 input_line_pointer += 6;
6356 break;
6357 }
6358 ++input_line_pointer;
6359 }
6360 if (initstop == NULL)
6361 {
6362 as_bad (_("missing to or downto"));
6363 ignore_rest_of_line ();
6364 return;
6365 }
6366 if (initstop > initstart
6367 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6368 --initstop;
6369
6370 SKIP_WHITESPACE ();
6371 endstart = input_line_pointer;
6372
6373 /* Look for BY or DO. */
6374 by = 0;
6375 endstop = NULL;
6376 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6377 {
6378 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6379 && ! is_part_of_name (input_line_pointer[2]))
6380 {
6381 endstop = input_line_pointer;
6382 by = 1;
6383 input_line_pointer += 2;
6384 break;
6385 }
6386 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6387 && (input_line_pointer[2] == '.'
6388 || ! is_part_of_name (input_line_pointer[2])))
6389 {
6390 endstop = input_line_pointer;
6391 input_line_pointer += 2;
6392 break;
6393 }
6394 ++input_line_pointer;
6395 }
6396 if (endstop == NULL)
6397 {
6398 as_bad (_("missing do"));
6399 ignore_rest_of_line ();
6400 return;
6401 }
6402 if (endstop > endstart
6403 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6404 --endstop;
6405
6406 if (! by)
6407 {
6408 bystart = "#1";
6409 bystop = bystart + 2;
6410 }
6411 else
6412 {
6413 SKIP_WHITESPACE ();
6414 bystart = input_line_pointer;
6415
6416 /* Look for DO. */
6417 bystop = NULL;
6418 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6419 {
6420 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6421 && (input_line_pointer[2] == '.'
6422 || ! is_part_of_name (input_line_pointer[2])))
6423 {
6424 bystop = input_line_pointer;
6425 input_line_pointer += 2;
6426 break;
6427 }
6428 ++input_line_pointer;
6429 }
6430 if (bystop == NULL)
6431 {
6432 as_bad (_("missing do"));
6433 ignore_rest_of_line ();
6434 return;
6435 }
6436 if (bystop > bystart
6437 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6438 --bystop;
6439 }
6440
6441 if (*input_line_pointer != '.')
6442 extent = '\0';
6443 else
6444 {
6445 extent = input_line_pointer[1];
6446 input_line_pointer += 2;
6447 }
6448
6449 /* We have fully parsed the FOR operands. Now build the loop. */
6450
6451 n = push_mri_control (mri_for);
6452
6453 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6454
6455 /* move init,var */
6456 s = buf;
6457 *s++ = 'm';
6458 *s++ = 'o';
6459 *s++ = 'v';
6460 *s++ = 'e';
6461 if (qual != '\0')
6462 *s++ = TOLOWER (qual);
6463 *s++ = ' ';
6464 memcpy (s, initstart, initstop - initstart);
6465 s += initstop - initstart;
6466 *s++ = ',';
6467 memcpy (s, varstart, varstop - varstart);
6468 s += varstop - varstart;
6469 *s = '\0';
6470 mri_assemble (buf);
6471
6472 colon (n->top);
6473
6474 /* cmp end,var */
6475 s = buf;
6476 *s++ = 'c';
6477 *s++ = 'm';
6478 *s++ = 'p';
6479 if (qual != '\0')
6480 *s++ = TOLOWER (qual);
6481 *s++ = ' ';
6482 memcpy (s, endstart, endstop - endstart);
6483 s += endstop - endstart;
6484 *s++ = ',';
6485 memcpy (s, varstart, varstop - varstart);
6486 s += varstop - varstart;
6487 *s = '\0';
6488 mri_assemble (buf);
6489
6490 /* bcc bottom */
6491 ex[0] = TOLOWER (extent);
6492 ex[1] = '\0';
6493 if (up)
6494 sprintf (buf, "blt%s %s", ex, n->bottom);
6495 else
6496 sprintf (buf, "bgt%s %s", ex, n->bottom);
6497 mri_assemble (buf);
6498
6499 /* Put together the add or sub instruction used by ENDF. */
6500 s = buf;
6501 if (up)
6502 strcpy (s, "add");
6503 else
6504 strcpy (s, "sub");
6505 s += 3;
6506 if (qual != '\0')
6507 *s++ = TOLOWER (qual);
6508 *s++ = ' ';
6509 memcpy (s, bystart, bystop - bystart);
6510 s += bystop - bystart;
6511 *s++ = ',';
6512 memcpy (s, varstart, varstop - varstart);
6513 s += varstop - varstart;
6514 *s = '\0';
6515 n->incr = buf;
6516
6517 if (flag_mri)
6518 {
6519 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6520 ++input_line_pointer;
6521 }
6522
6523 demand_empty_rest_of_line ();
6524}
6525
6526/* Handle the MRI ENDF pseudo-op. */
6527
6528static void
6529s_mri_endf (ignore)
6530 int ignore ATTRIBUTE_UNUSED;
6531{
6532 if (mri_control_stack == NULL
6533 || mri_control_stack->type != mri_for)
6534 {
6535 as_bad (_("endf without for"));
6536 ignore_rest_of_line ();
6537 return;
6538 }
6539
6540 colon (mri_control_stack->next);
6541
6542 mri_assemble (mri_control_stack->incr);
6543
6544 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6545 mri_assemble (mri_control_stack->incr);
6546
6547 free (mri_control_stack->incr);
6548
6549 colon (mri_control_stack->bottom);
6550
6551 pop_mri_control ();
6552
6553 if (flag_mri)
6554 {
6555 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6556 ++input_line_pointer;
6557 }
6558
6559 demand_empty_rest_of_line ();
6560}
6561
6562/* Handle the MRI REPEAT pseudo-op. */
6563
6564static void
6565s_mri_repeat (ignore)
6566 int ignore ATTRIBUTE_UNUSED;
6567{
6568 struct mri_control_info *n;
6569
6570 n = push_mri_control (mri_repeat);
6571 colon (n->top);
6572 if (flag_mri)
6573 {
6574 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6575 ++input_line_pointer;
6576 }
6577 demand_empty_rest_of_line ();
6578}
6579
6580/* Handle the MRI UNTIL pseudo-op. */
6581
6582static void
6583s_mri_until (qual)
6584 int qual;
6585{
6586 char *s;
6587
6588 if (mri_control_stack == NULL
6589 || mri_control_stack->type != mri_repeat)
6590 {
6591 as_bad (_("until without repeat"));
6592 ignore_rest_of_line ();
6593 return;
6594 }
6595
6596 colon (mri_control_stack->next);
6597
6598 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6599 ;
6600
6601 parse_mri_control_expression (s, qual, (const char *) NULL,
6602 mri_control_stack->top, '\0');
6603
6604 colon (mri_control_stack->bottom);
6605
6606 input_line_pointer = s;
6607
6608 pop_mri_control ();
6609
6610 if (flag_mri)
6611 {
6612 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6613 ++input_line_pointer;
6614 }
6615
6616 demand_empty_rest_of_line ();
6617}
6618
6619/* Handle the MRI WHILE pseudo-op. */
6620
6621static void
6622s_mri_while (qual)
6623 int qual;
6624{
6625 char *s;
6626
6627 struct mri_control_info *n;
6628
6629 s = input_line_pointer;
6630 /* We only accept '*' as introduction of comments if preceded by white space
6631 or at first column of a line (I think this can't actually happen here?)
6632 This is important when assembling:
6633 while d0 <ne> 12(a0,d0*2) do
6634 while d0 <ne> #CONST*20 do */
6635 while (! (is_end_of_line[(unsigned char) *s]
6636 || (flag_mri
6637 && *s == '*'
6638 && (s == input_line_pointer
6639 || *(s-1) == ' '
6640 || *(s-1) == '\t'))))
6641 s++;
6642 --s;
6643 while (*s == ' ' || *s == '\t')
6644 --s;
6645 if (s - input_line_pointer > 1
6646 && s[-1] == '.')
6647 s -= 2;
6648 if (s - input_line_pointer < 2
6649 || strncasecmp (s - 1, "DO", 2) != 0)
6650 {
6651 as_bad (_("missing do"));
6652 ignore_rest_of_line ();
6653 return;
6654 }
6655
6656 n = push_mri_control (mri_while);
6657
6658 colon (n->next);
6659
6660 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6661 s[1] == '.' ? s[2] : '\0');
6662
6663 input_line_pointer = s + 1;
6664 if (*input_line_pointer == '.')
6665 input_line_pointer += 2;
6666
6667 if (flag_mri)
6668 {
6669 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6670 ++input_line_pointer;
6671 }
6672
6673 demand_empty_rest_of_line ();
6674}
6675
6676/* Handle the MRI ENDW pseudo-op. */
6677
6678static void
6679s_mri_endw (ignore)
6680 int ignore ATTRIBUTE_UNUSED;
6681{
6682 char *buf;
6683
6684 if (mri_control_stack == NULL
6685 || mri_control_stack->type != mri_while)
6686 {
6687 as_bad (_("endw without while"));
6688 ignore_rest_of_line ();
6689 return;
6690 }
6691
6692 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6693 sprintf (buf, "bra %s", mri_control_stack->next);
6694 mri_assemble (buf);
6695 free (buf);
6696
6697 colon (mri_control_stack->bottom);
6698
6699 pop_mri_control ();
6700
6701 if (flag_mri)
6702 {
6703 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6704 ++input_line_pointer;
6705 }
6706
6707 demand_empty_rest_of_line ();
6708}
6709
6710
6711/*
6712 * md_parse_option
6713 * Invocation line includes a switch not recognized by the base assembler.
6714 * See if it's a processor-specific option. These are:
6715 *
6716 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6717 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6718 * Select the architecture. Instructions or features not
6719 * supported by the selected architecture cause fatal
6720 * errors. More than one may be specified. The default is
6721 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6722 * for -m68000, and -m68882 is a synonym for -m68881.
6723 * -[A]m[c]no-68851, -[A]m[c]no-68881
6724 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6725 * so don't use or document it, but that's the way the parsing
6726 * works).
6727 *
6728 * -pic Indicates PIC.
6729 * -k Indicates PIC. (Sun 3 only.)
6730 * --pcrel Never turn PC-relative branches into absolute jumps.
6731 *
6732 * --bitwise-or
6733 * Permit `|' to be used in expressions.
6734 *
6735 */
6736
6737#ifdef OBJ_ELF
6738const char *md_shortopts = "lSA:m:kQ:V";
6739#else
6740const char *md_shortopts = "lSA:m:k";
6741#endif
6742
6743struct option md_longopts[] = {
6744#define OPTION_PIC (OPTION_MD_BASE)
6745 {"pic", no_argument, NULL, OPTION_PIC},
6746#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6747 {"register-prefix-optional", no_argument, NULL,
6748 OPTION_REGISTER_PREFIX_OPTIONAL},
6749#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6750 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6751#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6752 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6753#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6754 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6755#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6756 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6757#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6758 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6759#define OPTION_PCREL (OPTION_MD_BASE + 7)
6760 {"pcrel", no_argument, NULL, OPTION_PCREL},
6761 {NULL, no_argument, NULL, 0}
6762};
6763size_t md_longopts_size = sizeof (md_longopts);
6764
6765int
6766md_parse_option (c, arg)
6767 int c;
6768 char *arg;
6769{
6770 switch (c)
6771 {
6772 case 'l': /* -l means keep external to 2 bit offset
6773 rather than 16 bit one */
6774 flag_short_refs = 1;
6775 break;
6776
6777 case 'S': /* -S means that jbsr's always turn into
6778 jsr's. */
6779 flag_long_jumps = 1;
6780 break;
6781
6782 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6783 branches into absolute jumps. */
6784 flag_keep_pcrel = 1;
6785 break;
6786
6787 case 'A':
6788 if (*arg == 'm')
6789 arg++;
6790 /* intentional fall-through */
6791 case 'm':
6792
6793 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6794 {
6795 int i;
6796 unsigned long arch;
6797 const char *oarg = arg;
6798
6799 arg += 3;
6800 if (*arg == 'm')
6801 {
6802 arg++;
6803 if (arg[0] == 'c' && arg[1] == '6')
6804 arg++;
6805 }
6806 for (i = 0; i < n_archs; i++)
6807 if (!strcmp (arg, archs[i].name))
6808 break;
6809 if (i == n_archs)
6810 {
6811 unknown:
6812 as_bad (_("unrecognized option `%s'"), oarg);
6813 return 0;
6814 }
6815 arch = archs[i].arch;
6816 if (arch == m68881)
6817 no_68881 = 1;
6818 else if (arch == m68851)
6819 no_68851 = 1;
6820 else
6821 goto unknown;
6822 }
6823 else
6824 {
6825 int i;
6826
6827 if (arg[0] == 'c' && arg[1] == '6')
6828 arg++;
6829
6830 for (i = 0; i < n_archs; i++)
6831 if (!strcmp (arg, archs[i].name))
6832 {
6833 unsigned long arch = archs[i].arch;
6834 if (cpu_of_arch (arch))
6835 /* It's a cpu spec. */
6836 {
6837 current_architecture &= ~m68000up;
6838 current_architecture |= arch;
6839 }
6840 else if (arch == m68881)
6841 {
6842 current_architecture |= m68881;
6843 no_68881 = 0;
6844 }
6845 else if (arch == m68851)
6846 {
6847 current_architecture |= m68851;
6848 no_68851 = 0;
6849 }
6850 else
6851 /* ??? */
6852 abort ();
6853 break;
6854 }
6855 if (i == n_archs)
6856 {
6857 as_bad (_("unrecognized architecture specification `%s'"), arg);
6858 return 0;
6859 }
6860 }
6861 break;
6862
6863 case OPTION_PIC:
6864 case 'k':
6865 flag_want_pic = 1;
6866 break; /* -pic, Position Independent Code */
6867
6868 case OPTION_REGISTER_PREFIX_OPTIONAL:
6869 flag_reg_prefix_optional = 1;
6870 reg_prefix_optional_seen = 1;
6871 break;
6872
6873 /* -V: SVR4 argument to print version ID. */
6874 case 'V':
6875 print_version_id ();
6876 break;
6877
6878 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6879 should be emitted or not. FIXME: Not implemented. */
6880 case 'Q':
6881 break;
6882
6883 case OPTION_BITWISE_OR:
6884 {
6885 char *n, *t;
6886 const char *s;
6887
6888 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6889 t = n;
6890 for (s = m68k_comment_chars; *s != '\0'; s++)
6891 if (*s != '|')
6892 *t++ = *s;
6893 *t = '\0';
6894 m68k_comment_chars = n;
6895 }
6896 break;
6897
6898 case OPTION_BASE_SIZE_DEFAULT_16:
6899 m68k_index_width_default = SIZE_WORD;
6900 break;
6901
6902 case OPTION_BASE_SIZE_DEFAULT_32:
6903 m68k_index_width_default = SIZE_LONG;
6904 break;
6905
6906 case OPTION_DISP_SIZE_DEFAULT_16:
6907 m68k_rel32 = 0;
6908 m68k_rel32_from_cmdline = 1;
6909 break;
6910
6911 case OPTION_DISP_SIZE_DEFAULT_32:
6912 m68k_rel32 = 1;
6913 m68k_rel32_from_cmdline = 1;
6914 break;
6915
6916 default:
6917 return 0;
6918 }
6919
6920 return 1;
6921}
6922
6923void
6924md_show_usage (stream)
6925 FILE *stream;
6926{
6927 const char *default_cpu = TARGET_CPU;
6928 int i;
6929 unsigned int default_arch;
6930
6931 /* Get the canonical name for the default target CPU. */
6932 if (*default_cpu == 'm')
6933 default_cpu++;
6934 for (i = 0; i < n_archs; i++)
6935 {
6936 if (strcasecmp (default_cpu, archs[i].name) == 0)
6937 {
6938 default_arch = archs[i].arch;
6939 for (i = 0; i < n_archs; i++)
6940 {
6941 if (archs[i].arch == default_arch
6942 && !archs[i].alias)
6943 {
6944 default_cpu = archs[i].name;
6945 break;
6946 }
6947 }
6948 }
6949 }
6950
6951 fprintf (stream, _("\
6952680X0 options:\n\
6953-l use 1 word for refs to undefined symbols [default 2]\n\
6954-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
6955-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6956-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\
6957 specify variant of 680X0 architecture [default %s]\n\
6958-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6959 target has/lacks floating-point coprocessor\n\
6960 [default yes for 68020, 68030, and cpu32]\n"),
6961 default_cpu);
6962 fprintf (stream, _("\
6963-m68851 | -mno-68851\n\
6964 target has/lacks memory-management unit coprocessor\n\
6965 [default yes for 68020 and up]\n\
6966-pic, -k generate position independent code\n\
6967-S turn jbsr into jsr\n\
6968--pcrel never turn PC-relative branches into absolute jumps\n\
6969--register-prefix-optional\n\
6970 recognize register names without prefix character\n\
6971--bitwise-or do not treat `|' as a comment character\n"));
6972 fprintf (stream, _("\
6973--base-size-default-16 base reg without size is 16 bits\n\
6974--base-size-default-32 base reg without size is 32 bits (default)\n\
6975--disp-size-default-16 displacement with unknown size is 16 bits\n\
6976--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6977}
6978
6979
6980#ifdef TEST2
6981
6982/* TEST2: Test md_assemble() */
6983/* Warning, this routine probably doesn't work anymore */
6984
6985main ()
6986{
6987 struct m68k_it the_ins;
6988 char buf[120];
6989 char *cp;
6990 int n;
6991
6992 m68k_ip_begin ();
6993 for (;;)
6994 {
6995 if (!gets (buf) || !*buf)
6996 break;
6997 if (buf[0] == '|' || buf[1] == '.')
6998 continue;
6999 for (cp = buf; *cp; cp++)
7000 if (*cp == '\t')
7001 *cp = ' ';
7002 if (is_label (buf))
7003 continue;
7004 memset (&the_ins, '\0', sizeof (the_ins));
7005 m68k_ip (&the_ins, buf);
7006 if (the_ins.error)
7007 {
7008 printf (_("Error %s in %s\n"), the_ins.error, buf);
7009 }
7010 else
7011 {
7012 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7013 for (n = 0; n < the_ins.numo; n++)
7014 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7015 printf (" ");
7016 print_the_insn (&the_ins.opcode[0], stdout);
7017 (void) putchar ('\n');
7018 }
7019 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7020 {
7021 if (the_ins.operands[n].error)
7022 {
7023 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7024 continue;
7025 }
7026 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7027 if (the_ins.operands[n].b_const)
7028 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7029 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7030 if (the_ins.operands[n].b_iadd)
7031 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7032 (void) putchar ('\n');
7033 }
7034 }
7035 m68k_ip_end ();
7036 return 0;
7037}
7038
7039is_label (str)
7040 char *str;
7041{
7042 while (*str == ' ')
7043 str++;
7044 while (*str && *str != ' ')
7045 str++;
7046 if (str[-1] == ':' || str[1] == '=')
7047 return 1;
7048 return 0;
7049}
7050
7051#endif
7052
7053/* Possible states for relaxation:
7054
7055 0 0 branch offset byte (bra, etc)
7056 0 1 word
7057 0 2 long
7058
7059 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7060 1 1 word
7061 1 2 long
7062
7063 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7064 2 1 word-long
7065 2 2 long-word
7066 2 3 long-long
7067
7068 */
7069
7070/* We have no need to default values of symbols. */
7071
7072symbolS *
7073md_undefined_symbol (name)
7074 char *name ATTRIBUTE_UNUSED;
7075{
7076 return 0;
7077}
7078
7079/* Round up a section size to the appropriate boundary. */
7080valueT
7081md_section_align (segment, size)
7082 segT segment ATTRIBUTE_UNUSED;
7083 valueT size;
7084{
7085#ifdef OBJ_AOUT
7086#ifdef BFD_ASSEMBLER
7087 /* For a.out, force the section size to be aligned. If we don't do
7088 this, BFD will align it for us, but it will not write out the
7089 final bytes of the section. This may be a bug in BFD, but it is
7090 easier to fix it here since that is how the other a.out targets
7091 work. */
7092 int align;
7093
7094 align = bfd_get_section_alignment (stdoutput, segment);
7095 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7096#endif
7097#endif
7098
7099 return size;
7100}
7101
7102/* Exactly what point is a PC-relative offset relative TO?
7103 On the 68k, it is relative to the address of the first extension
7104 word. The difference between the addresses of the offset and the
7105 first extension word is stored in fx_pcrel_adjust. */
7106long
7107md_pcrel_from (fixP)
7108 fixS *fixP;
7109{
7110 int adjust;
7111
7112 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7113 sign extend the value here. */
7114 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7115 if (adjust == 64)
7116 adjust = -1;
7117 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7118}
7119
7120#ifndef BFD_ASSEMBLER
7121#ifdef OBJ_COFF
7122
7123void
7124tc_coff_symbol_emit_hook (ignore)
7125 symbolS *ignore ATTRIBUTE_UNUSED;
7126{
7127}
7128
7129int
7130tc_coff_sizemachdep (frag)
7131 fragS *frag;
7132{
7133 switch (frag->fr_subtype & 0x3)
7134 {
7135 case BYTE:
7136 return 1;
7137 case SHORT:
7138 return 2;
7139 case LONG:
7140 return 4;
7141 default:
7142 abort ();
7143 return 0;
7144 }
7145}
7146
7147#endif
7148#endif
7149#ifdef OBJ_ELF
7150void
7151m68k_elf_final_processing ()
7152{
7153 /* Set file-specific flags if this is a cpu32 processor */
7154 if (cpu_of_arch (current_architecture) & cpu32)
7155 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7156 else if ((cpu_of_arch (current_architecture) & m68000up)
7157 && !(cpu_of_arch (current_architecture) & m68020up))
7158 elf_elfheader (stdoutput)->e_flags |= EF_M68000;
7159}
7160#endif
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