| 1 | /* tc-i386.h -- Header file for tc-i386.c
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| 2 | Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
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| 3 | 2001, 2002, 2003
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| 4 | Free Software Foundation, Inc.
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| 5 |
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| 6 | This file is part of GAS, the GNU Assembler.
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| 7 |
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| 8 | GAS is free software; you can redistribute it and/or modify
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| 9 | it under the terms of the GNU General Public License as published by
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| 10 | the Free Software Foundation; either version 2, or (at your option)
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| 11 | any later version.
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| 12 |
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| 13 | GAS is distributed in the hope that it will be useful,
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| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 16 | GNU General Public License for more details.
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| 17 |
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| 18 | You should have received a copy of the GNU General Public License
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| 19 | along with GAS; see the file COPYING. If not, write to the Free
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| 20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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| 21 | 02111-1307, USA. */
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| 22 |
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| 23 | #ifndef TC_I386
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| 24 | #define TC_I386 1
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| 25 |
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| 26 | #ifdef ANSI_PROTOTYPES
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| 27 | struct fix;
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| 28 | #endif
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| 29 |
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| 30 | #define TARGET_BYTES_BIG_ENDIAN 0
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| 31 |
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| 32 | #ifdef TE_LYNX
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| 33 | #define TARGET_FORMAT "coff-i386-lynx"
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| 34 | #endif
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| 35 |
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| 36 | #ifdef BFD_ASSEMBLER
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| 37 | #define TARGET_ARCH bfd_arch_i386
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| 38 | #define TARGET_MACH (i386_mach ())
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| 39 | extern unsigned long i386_mach PARAMS ((void));
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| 40 |
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| 41 | #ifdef TE_FreeBSD
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| 42 | #define AOUT_TARGET_FORMAT "a.out-i386-freebsd"
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| 43 | #endif
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| 44 | #ifdef TE_NetBSD
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| 45 | #define AOUT_TARGET_FORMAT "a.out-i386-netbsd"
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| 46 | #endif
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| 47 | #ifdef TE_386BSD
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| 48 | #define AOUT_TARGET_FORMAT "a.out-i386-bsd"
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| 49 | #endif
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| 50 | #ifdef TE_LINUX
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| 51 | #define AOUT_TARGET_FORMAT "a.out-i386-linux"
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| 52 | #endif
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| 53 | #ifdef TE_Mach
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| 54 | #define AOUT_TARGET_FORMAT "a.out-mach3"
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| 55 | #endif
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| 56 | #ifdef TE_DYNIX
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| 57 | #define AOUT_TARGET_FORMAT "a.out-i386-dynix"
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| 58 | #endif
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| 59 | #ifdef TE_EMX
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| 60 | #define AOUT_TARGET_FORMAT "a.out-emx"
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| 61 | #endif
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| 62 | #ifndef AOUT_TARGET_FORMAT
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| 63 | #define AOUT_TARGET_FORMAT "a.out-i386"
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| 64 | #endif
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| 65 |
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| 66 | #ifdef TE_FreeBSD
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| 67 | #define ELF_TARGET_FORMAT "elf32-i386-freebsd"
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| 68 | #endif
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| 69 | #ifndef ELF_TARGET_FORMAT
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| 70 | #define ELF_TARGET_FORMAT "elf32-i386"
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| 71 | #endif
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| 72 |
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| 73 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
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| 74 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
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| 75 | extern const char *i386_target_format PARAMS ((void));
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| 76 | #define TARGET_FORMAT i386_target_format ()
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| 77 | #else
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| 78 | #ifdef OBJ_ELF
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| 79 | #define TARGET_FORMAT ELF_TARGET_FORMAT
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| 80 | #endif
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| 81 | #ifdef OBJ_AOUT
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| 82 | #define TARGET_FORMAT AOUT_TARGET_FORMAT
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| 83 | #endif
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| 84 | #endif
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| 85 |
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| 86 | #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
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| 87 | #define md_end i386_elf_emit_arch_note
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| 88 | extern void i386_elf_emit_arch_note PARAMS ((void));
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| 89 | #endif
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| 90 |
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| 91 | #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
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| 92 |
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| 93 | #else /* ! BFD_ASSEMBLER */
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| 94 |
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| 95 | /* COFF STUFF */
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| 96 |
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| 97 | #define COFF_MAGIC I386MAGIC
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| 98 | #define BFD_ARCH bfd_arch_i386
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| 99 | #define COFF_FLAGS F_AR32WR
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| 100 | #define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7)
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| 101 | #define TC_COFF_FIX2RTYPE(FIX) tc_coff_fix2rtype(FIX)
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| 102 | extern short tc_coff_fix2rtype PARAMS ((struct fix *));
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| 103 | #define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep (frag)
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| 104 | extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
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| 105 |
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| 106 | #ifdef TE_GO32
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| 107 | /* DJGPP now expects some sections to be 2**4 aligned. */
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| 108 | #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) \
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| 109 | ((strcmp (obj_segment_name (SEG), ".text") == 0 \
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| 110 | || strcmp (obj_segment_name (SEG), ".data") == 0 \
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| 111 | || strcmp (obj_segment_name (SEG), ".bss") == 0 \
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| 112 | || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0 \
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| 113 | || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0 \
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| 114 | || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0) \
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| 115 | ? 4 \
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| 116 | : 2)
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| 117 | #else
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| 118 | #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 2
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| 119 | #endif
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| 120 |
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| 121 | #ifdef TE_386BSD
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| 122 | /* The BSDI linker apparently rejects objects with a machine type of
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| 123 | M_386 (100). */
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| 124 | #define AOUT_MACHTYPE 0
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| 125 | #else
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| 126 | #define AOUT_MACHTYPE 100
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| 127 | #endif
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| 128 |
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| 129 | #ifndef OBJ_AOUT
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| 130 | #ifndef TE_PE
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| 131 | #ifndef TE_GO32
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| 132 | /* Local labels starts with .L */
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| 133 | #define LOCAL_LABEL(name) (name[0] == '.' \
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| 134 | && (name[1] == 'L' || name[1] == 'X' || name[1] == '.'))
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| 135 | #endif
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| 136 | #endif
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| 137 | #endif
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| 138 |
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| 139 | #define tc_aout_pre_write_hook(x) {;} /* not used */
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| 140 | #define tc_crawl_symbol_chain(a) {;} /* not used */
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| 141 | #define tc_headers_hook(a) {;} /* not used */
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| 142 | #define tc_coff_symbol_emit_hook(a) {;} /* not used */
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| 143 |
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| 144 | #endif /* ! BFD_ASSEMBLER */
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| 145 |
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| 146 | #define LOCAL_LABELS_FB 1
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| 147 |
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| 148 | extern const char extra_symbol_chars[];
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| 149 | #define tc_symbol_chars extra_symbol_chars
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| 150 |
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| 151 | #define MAX_OPERANDS 3 /* max operands per insn */
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| 152 | #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
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| 153 | #define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */
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| 154 |
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| 155 | /* Prefixes will be emitted in the order defined below.
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| 156 | WAIT_PREFIX must be the first prefix since FWAIT is really is an
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| 157 | instruction, and so must come before any prefixes. */
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| 158 | #define WAIT_PREFIX 0
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| 159 | #define LOCKREP_PREFIX 1
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| 160 | #define ADDR_PREFIX 2
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| 161 | #define DATA_PREFIX 3
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| 162 | #define SEG_PREFIX 4
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| 163 | #define REX_PREFIX 5 /* must come last. */
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| 164 | #define MAX_PREFIXES 6 /* max prefixes per opcode */
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| 165 |
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| 166 | /* we define the syntax here (modulo base,index,scale syntax) */
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| 167 | #define REGISTER_PREFIX '%'
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| 168 | #define IMMEDIATE_PREFIX '$'
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| 169 | #define ABSOLUTE_PREFIX '*'
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| 170 |
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| 171 | #define TWO_BYTE_OPCODE_ESCAPE 0x0f
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| 172 | #define NOP_OPCODE (char) 0x90
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| 173 |
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| 174 | /* register numbers */
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| 175 | #define EBP_REG_NUM 5
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| 176 | #define ESP_REG_NUM 4
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| 177 |
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| 178 | /* modrm_byte.regmem for twobyte escape */
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| 179 | #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
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| 180 | /* index_base_byte.index for no index register addressing */
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| 181 | #define NO_INDEX_REGISTER ESP_REG_NUM
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| 182 | /* index_base_byte.base for no base register addressing */
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| 183 | #define NO_BASE_REGISTER EBP_REG_NUM
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| 184 | #define NO_BASE_REGISTER_16 6
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| 185 |
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| 186 | /* these are the instruction mnemonic suffixes. */
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| 187 | #define WORD_MNEM_SUFFIX 'w'
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| 188 | #define BYTE_MNEM_SUFFIX 'b'
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| 189 | #define SHORT_MNEM_SUFFIX 's'
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| 190 | #define LONG_MNEM_SUFFIX 'l'
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| 191 | #define QWORD_MNEM_SUFFIX 'q'
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| 192 | /* Intel Syntax */
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| 193 | #define LONG_DOUBLE_MNEM_SUFFIX 'x'
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| 194 |
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| 195 | /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
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| 196 | #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
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| 197 | #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
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| 198 |
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| 199 | #define END_OF_INSN '\0'
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| 200 |
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| 201 | /* Intel Syntax */
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| 202 | /* Values 0-4 map onto scale factor */
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| 203 | #define BYTE_PTR 0
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| 204 | #define WORD_PTR 1
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| 205 | #define DWORD_PTR 2
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| 206 | #define QWORD_PTR 3
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| 207 | #define XWORD_PTR 4
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| 208 | #define SHORT 5
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| 209 | #define OFFSET_FLAT 6
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| 210 | #define FLAT 7
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| 211 | #define NONE_FOUND 8
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| 212 |
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| 213 | typedef struct
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| 214 | {
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| 215 | /* instruction name sans width suffix ("mov" for movl insns) */
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| 216 | char *name;
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| 217 |
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| 218 | /* how many operands */
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| 219 | unsigned int operands;
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| 220 |
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| 221 | /* base_opcode is the fundamental opcode byte without optional
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| 222 | prefix(es). */
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| 223 | unsigned int base_opcode;
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| 224 |
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| 225 | /* extension_opcode is the 3 bit extension for group <n> insns.
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| 226 | This field is also used to store the 8-bit opcode suffix for the
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| 227 | AMD 3DNow! instructions.
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| 228 | If this template has no extension opcode (the usual case) use None */
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| 229 | unsigned int extension_opcode;
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| 230 | #define None 0xffff /* If no extension_opcode is possible. */
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| 231 |
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| 232 | /* cpu feature flags */
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| 233 | unsigned int cpu_flags;
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| 234 | #define Cpu086 0x1 /* Any old cpu will do, 0 does the same */
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| 235 | #define Cpu186 0x2 /* i186 or better required */
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| 236 | #define Cpu286 0x4 /* i286 or better required */
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| 237 | #define Cpu386 0x8 /* i386 or better required */
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| 238 | #define Cpu486 0x10 /* i486 or better required */
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| 239 | #define Cpu586 0x20 /* i585 or better required */
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| 240 | #define Cpu686 0x40 /* i686 or better required */
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| 241 | #define CpuP4 0x80 /* Pentium4 or better required */
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| 242 | #define CpuK6 0x100 /* AMD K6 or better required*/
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| 243 | #define CpuAthlon 0x200 /* AMD Athlon or better required*/
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| 244 | #define CpuSledgehammer 0x400 /* Sledgehammer or better required */
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| 245 | #define CpuMMX 0x800 /* MMX support required */
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| 246 | #define CpuSSE 0x1000 /* Streaming SIMD extensions required */
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| 247 | #define CpuSSE2 0x2000 /* Streaming SIMD extensions 2 required */
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| 248 | #define Cpu3dnow 0x4000 /* 3dnow! support required */
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| 249 |
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| 250 | /* These flags are set by gas depending on the flag_code. */
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| 251 | #define Cpu64 0x4000000 /* 64bit support required */
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| 252 | #define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
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| 253 |
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| 254 | /* The default value for unknown CPUs - enable all features to avoid problems. */
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| 255 | #define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|Cpu3dnow|CpuK6|CpuAthlon)
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| 256 |
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| 257 | /* the bits in opcode_modifier are used to generate the final opcode from
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| 258 | the base_opcode. These bits also are used to detect alternate forms of
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| 259 | the same instruction */
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| 260 | unsigned int opcode_modifier;
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| 261 |
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| 262 | /* opcode_modifier bits: */
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| 263 | #define W 0x1 /* set if operands can be words or dwords
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| 264 | encoded the canonical way */
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| 265 | #define D 0x2 /* D = 0 if Reg --> Regmem;
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| 266 | D = 1 if Regmem --> Reg: MUST BE 0x2 */
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| 267 | #define Modrm 0x4
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| 268 | #define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */
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| 269 | #define ShortForm 0x10 /* register is in low 3 bits of opcode */
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| 270 | #define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
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| 271 | #define Jump 0x40 /* special case for jump insns. */
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| 272 | #define JumpDword 0x80 /* call and jump */
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| 273 | #define JumpByte 0x100 /* loop and jecxz */
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| 274 | #define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
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| 275 | #define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */
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| 276 | #define Seg2ShortForm 0x800 /* encoding of load segment reg insns */
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| 277 | #define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
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| 278 | #define Size16 0x2000 /* needs size prefix if in 32-bit mode */
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| 279 | #define Size32 0x4000 /* needs size prefix if in 16-bit mode */
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| 280 | #define Size64 0x8000 /* needs size prefix if in 16-bit mode */
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| 281 | #define IgnoreSize 0x10000 /* instruction ignores operand size prefix */
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| 282 | #define DefaultSize 0x20000 /* default insn size depends on mode */
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| 283 | #define No_bSuf 0x40000 /* b suffix on instruction illegal */
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| 284 | #define No_wSuf 0x80000 /* w suffix on instruction illegal */
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| 285 | #define No_lSuf 0x100000 /* l suffix on instruction illegal */
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| 286 | #define No_sSuf 0x200000 /* s suffix on instruction illegal */
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| 287 | #define No_qSuf 0x400000 /* q suffix on instruction illegal */
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| 288 | #define No_xSuf 0x800000 /* x suffix on instruction illegal */
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| 289 | #define FWait 0x1000000 /* instruction needs FWAIT */
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| 290 | #define IsString 0x2000000 /* quick test for string instructions */
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| 291 | #define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */
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| 292 | #define IsPrefix 0x8000000 /* opcode is a prefix */
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| 293 | #define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */
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| 294 | #define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */
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| 295 | #define Rex64 0x40000000 /* instruction require Rex64 prefix. */
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| 296 | #define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
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| 297 |
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| 298 | /* operand_types[i] describes the type of operand i. This is made
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| 299 | by OR'ing together all of the possible type masks. (e.g.
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| 300 | 'operand_types[i] = Reg|Imm' specifies that operand i can be
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| 301 | either a register or an immediate operand. */
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| 302 | unsigned int operand_types[3];
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| 303 |
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| 304 | /* operand_types[i] bits */
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| 305 | /* register */
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| 306 | #define Reg8 0x1 /* 8 bit reg */
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| 307 | #define Reg16 0x2 /* 16 bit reg */
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| 308 | #define Reg32 0x4 /* 32 bit reg */
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| 309 | #define Reg64 0x8 /* 64 bit reg */
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| 310 | /* immediate */
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| 311 | #define Imm8 0x10 /* 8 bit immediate */
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| 312 | #define Imm8S 0x20 /* 8 bit immediate sign extended */
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| 313 | #define Imm16 0x40 /* 16 bit immediate */
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| 314 | #define Imm32 0x80 /* 32 bit immediate */
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| 315 | #define Imm32S 0x100 /* 32 bit immediate sign extended */
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| 316 | #define Imm64 0x200 /* 64 bit immediate */
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| 317 | #define Imm1 0x400 /* 1 bit immediate */
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| 318 | /* memory */
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| 319 | #define BaseIndex 0x800
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| 320 | /* Disp8,16,32 are used in different ways, depending on the
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| 321 | instruction. For jumps, they specify the size of the PC relative
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| 322 | displacement, for baseindex type instructions, they specify the
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| 323 | size of the offset relative to the base register, and for memory
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| 324 | offset instructions such as `mov 1234,%al' they specify the size of
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| 325 | the offset relative to the segment base. */
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| 326 | #define Disp8 0x1000 /* 8 bit displacement */
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| 327 | #define Disp16 0x2000 /* 16 bit displacement */
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| 328 | #define Disp32 0x4000 /* 32 bit displacement */
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| 329 | #define Disp32S 0x8000 /* 32 bit signed displacement */
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| 330 | #define Disp64 0x10000 /* 64 bit displacement */
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| 331 | /* specials */
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| 332 | #define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */
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| 333 | #define ShiftCount 0x40000 /* register to hold shift cound = cl */
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| 334 | #define Control 0x80000 /* Control register */
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| 335 | #define Debug 0x100000 /* Debug register */
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| 336 | #define Test 0x200000 /* Test register */
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| 337 | #define FloatReg 0x400000 /* Float register */
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| 338 | #define FloatAcc 0x800000 /* Float stack top %st(0) */
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| 339 | #define SReg2 0x1000000 /* 2 bit segment register */
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| 340 | #define SReg3 0x2000000 /* 3 bit segment register */
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| 341 | #define Acc 0x4000000 /* Accumulator %al or %ax or %eax */
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| 342 | #define JumpAbsolute 0x8000000
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| 343 | #define RegMMX 0x10000000 /* MMX register */
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| 344 | #define RegXMM 0x20000000 /* XMM registers in PIII */
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| 345 | #define EsSeg 0x40000000 /* String insn operand with fixed es segment */
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| 346 |
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| 347 | /* InvMem is for instructions with a modrm byte that only allow a
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| 348 | general register encoding in the i.tm.mode and i.tm.regmem fields,
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| 349 | eg. control reg moves. They really ought to support a memory form,
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| 350 | but don't, so we add an InvMem flag to the register operand to
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| 351 | indicate that it should be encoded in the i.tm.regmem field. */
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| 352 | #define InvMem 0x80000000
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| 353 |
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| 354 | #define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
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| 355 | #define WordReg (Reg16|Reg32|Reg64)
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| 356 | #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
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| 357 | #define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
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| 358 | #define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
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| 359 | #define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
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| 360 | #define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */
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| 361 | /* The following aliases are defined because the opcode table
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| 362 | carefully specifies the allowed memory types for each instruction.
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| 363 | At the moment we can only tell a memory reference size by the
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| 364 | instruction suffix, so there's not much point in defining Mem8,
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| 365 | Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
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| 366 | the suffix directly to check memory operands. */
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| 367 | #define LLongMem AnyMem /* 64 bits (or more) */
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| 368 | #define LongMem AnyMem /* 32 bit memory ref */
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| 369 | #define ShortMem AnyMem /* 16 bit memory ref */
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| 370 | #define WordMem AnyMem /* 16 or 32 bit memory ref */
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| 371 | #define ByteMem AnyMem /* 8 bit memory ref */
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| 372 | }
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| 373 | template;
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| 374 |
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| 375 | /*
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| 376 | 'templates' is for grouping together 'template' structures for opcodes
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| 377 | of the same name. This is only used for storing the insns in the grand
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| 378 | ole hash table of insns.
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| 379 | The templates themselves start at START and range up to (but not including)
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| 380 | END.
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| 381 | */
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| 382 | typedef struct
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| 383 | {
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| 384 | const template *start;
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| 385 | const template *end;
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| 386 | }
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| 387 | templates;
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| 388 |
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| 389 | /* these are for register name --> number & type hash lookup */
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| 390 | typedef struct
|
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| 391 | {
|
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| 392 | char *reg_name;
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| 393 | unsigned int reg_type;
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| 394 | unsigned int reg_flags;
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| 395 | #define RegRex 0x1 /* Extended register. */
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| 396 | #define RegRex64 0x2 /* Extended 8 bit register. */
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| 397 | unsigned int reg_num;
|
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| 398 | }
|
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| 399 | reg_entry;
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| 400 |
|
|---|
| 401 | typedef struct
|
|---|
| 402 | {
|
|---|
| 403 | char *seg_name;
|
|---|
| 404 | unsigned int seg_prefix;
|
|---|
| 405 | }
|
|---|
| 406 | seg_entry;
|
|---|
| 407 |
|
|---|
| 408 | /* 386 operand encoding bytes: see 386 book for details of this. */
|
|---|
| 409 | typedef struct
|
|---|
| 410 | {
|
|---|
| 411 | unsigned int regmem; /* codes register or memory operand */
|
|---|
| 412 | unsigned int reg; /* codes register operand (or extended opcode) */
|
|---|
| 413 | unsigned int mode; /* how to interpret regmem & reg */
|
|---|
| 414 | }
|
|---|
| 415 | modrm_byte;
|
|---|
| 416 |
|
|---|
| 417 | /* x86-64 extension prefix. */
|
|---|
| 418 | typedef int rex_byte;
|
|---|
| 419 | #define REX_OPCODE 0x40
|
|---|
| 420 |
|
|---|
| 421 | /* Indicates 64 bit operand size. */
|
|---|
| 422 | #define REX_MODE64 8
|
|---|
| 423 | /* High extension to reg field of modrm byte. */
|
|---|
| 424 | #define REX_EXTX 4
|
|---|
| 425 | /* High extension to SIB index field. */
|
|---|
| 426 | #define REX_EXTY 2
|
|---|
| 427 | /* High extension to base field of modrm or SIB, or reg field of opcode. */
|
|---|
| 428 | #define REX_EXTZ 1
|
|---|
| 429 |
|
|---|
| 430 | /* 386 opcode byte to code indirect addressing. */
|
|---|
| 431 | typedef struct
|
|---|
| 432 | {
|
|---|
| 433 | unsigned base;
|
|---|
| 434 | unsigned index;
|
|---|
| 435 | unsigned scale;
|
|---|
| 436 | }
|
|---|
| 437 | sib_byte;
|
|---|
| 438 |
|
|---|
| 439 | /* x86 arch names and features */
|
|---|
| 440 | typedef struct
|
|---|
| 441 | {
|
|---|
| 442 | const char *name; /* arch name */
|
|---|
| 443 | unsigned int flags; /* cpu feature flags */
|
|---|
| 444 | }
|
|---|
| 445 | arch_entry;
|
|---|
| 446 |
|
|---|
| 447 | /* The name of the global offset table generated by the compiler. Allow
|
|---|
| 448 | this to be overridden if need be. */
|
|---|
| 449 | #ifndef GLOBAL_OFFSET_TABLE_NAME
|
|---|
| 450 | #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
|
|---|
| 451 | #endif
|
|---|
| 452 |
|
|---|
| 453 | #ifndef LEX_AT
|
|---|
| 454 | #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
|
|---|
| 455 | extern void x86_cons PARAMS ((expressionS *, int));
|
|---|
| 456 |
|
|---|
| 457 | #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
|
|---|
| 458 | extern void x86_cons_fix_new
|
|---|
| 459 | PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
|
|---|
| 460 | #endif
|
|---|
| 461 |
|
|---|
| 462 | #define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
|
|---|
| 463 |
|
|---|
| 464 | #ifdef BFD_ASSEMBLER
|
|---|
| 465 | #define NO_RELOC BFD_RELOC_NONE
|
|---|
| 466 |
|
|---|
| 467 | void i386_validate_fix PARAMS ((struct fix *));
|
|---|
| 468 | #define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX)
|
|---|
| 469 |
|
|---|
| 470 | #define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
|
|---|
| 471 | extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
|
|---|
| 472 |
|
|---|
| 473 | /* Values passed to md_apply_fix3 don't include the symbol value. */
|
|---|
| 474 | #define MD_APPLY_SYM_VALUE(FIX) 0
|
|---|
| 475 |
|
|---|
| 476 | /* ELF wants external syms kept, as does PE COFF. */
|
|---|
| 477 | #if defined (TE_PE) && defined (STRICT_PE_FORMAT)
|
|---|
| 478 | #define EXTERN_FORCE_RELOC \
|
|---|
| 479 | (OUTPUT_FLAVOR == bfd_target_elf_flavour \
|
|---|
| 480 | || OUTPUT_FLAVOR == bfd_target_coff_flavour)
|
|---|
| 481 | #else
|
|---|
| 482 | #define EXTERN_FORCE_RELOC \
|
|---|
| 483 | (OUTPUT_FLAVOR == bfd_target_elf_flavour)
|
|---|
| 484 | #endif
|
|---|
| 485 |
|
|---|
| 486 | /* This expression evaluates to true if the relocation is for a local
|
|---|
| 487 | object for which we still want to do the relocation at runtime.
|
|---|
| 488 | False if we are willing to perform this relocation while building
|
|---|
| 489 | the .o file. GOTOFF does not need to be checked here because it is
|
|---|
| 490 | not pcrel. I am not sure if some of the others are ever used with
|
|---|
| 491 | pcrel, but it is easier to be safe than sorry. */
|
|---|
| 492 |
|
|---|
| 493 | #define TC_FORCE_RELOCATION_LOCAL(FIX) \
|
|---|
| 494 | (!(FIX)->fx_pcrel \
|
|---|
| 495 | || (FIX)->fx_plt \
|
|---|
| 496 | || (FIX)->fx_r_type == BFD_RELOC_386_PLT32 \
|
|---|
| 497 | || (FIX)->fx_r_type == BFD_RELOC_386_GOT32 \
|
|---|
| 498 | || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC \
|
|---|
| 499 | || TC_FORCE_RELOCATION (FIX))
|
|---|
| 500 |
|
|---|
| 501 | #else /* ! BFD_ASSEMBLER */
|
|---|
| 502 |
|
|---|
| 503 | #define NO_RELOC 0
|
|---|
| 504 |
|
|---|
| 505 | #define TC_RVA_RELOC 7
|
|---|
| 506 |
|
|---|
| 507 | /* Need this for PIC relocations */
|
|---|
| 508 | #define NEED_FX_R_TYPE
|
|---|
| 509 |
|
|---|
| 510 | #undef REVERSE_SORT_RELOCS
|
|---|
| 511 |
|
|---|
| 512 | /* For COFF. */
|
|---|
| 513 | #define TC_FORCE_RELOCATION(FIX) \
|
|---|
| 514 | ((FIX)->fx_r_type == 7 || generic_force_reloc (FIX))
|
|---|
| 515 | #endif /* ! BFD_ASSEMBLER */
|
|---|
| 516 |
|
|---|
| 517 | #define md_operand(x)
|
|---|
| 518 |
|
|---|
| 519 | extern const struct relax_type md_relax_table[];
|
|---|
| 520 | #define TC_GENERIC_RELAX_TABLE md_relax_table
|
|---|
| 521 |
|
|---|
| 522 | #define md_do_align(n, fill, len, max, around) \
|
|---|
| 523 | if ((n) && !need_pass_2 \
|
|---|
| 524 | && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1)) \
|
|---|
| 525 | && subseg_text_p (now_seg)) \
|
|---|
| 526 | { \
|
|---|
| 527 | frag_align_code ((n), (max)); \
|
|---|
| 528 | goto around; \
|
|---|
| 529 | }
|
|---|
| 530 |
|
|---|
| 531 | #define MAX_MEM_FOR_RS_ALIGN_CODE 15
|
|---|
| 532 |
|
|---|
| 533 | extern void i386_align_code PARAMS ((fragS *, int));
|
|---|
| 534 |
|
|---|
| 535 | #define HANDLE_ALIGN(fragP) \
|
|---|
| 536 | if (fragP->fr_type == rs_align_code) \
|
|---|
| 537 | i386_align_code (fragP, (fragP->fr_next->fr_address \
|
|---|
| 538 | - fragP->fr_address \
|
|---|
| 539 | - fragP->fr_fix));
|
|---|
| 540 |
|
|---|
| 541 | void i386_print_statistics PARAMS ((FILE *));
|
|---|
| 542 | #define tc_print_statistics i386_print_statistics
|
|---|
| 543 |
|
|---|
| 544 | #define md_number_to_chars number_to_chars_littleendian
|
|---|
| 545 |
|
|---|
| 546 | #ifdef SCO_ELF
|
|---|
| 547 | #define tc_init_after_args() sco_id ()
|
|---|
| 548 | extern void sco_id PARAMS ((void));
|
|---|
| 549 | #endif
|
|---|
| 550 |
|
|---|
| 551 | #endif /* TC_I386 */
|
|---|
