source: trunk/binutils/bfd/coff-sh.c@ 3020

Last change on this file since 3020 was 610, checked in by bird, 22 years ago

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1/* BFD back-end for Renesas Super-H COFF binaries.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Cygnus Support.
5 Written by Steve Chamberlain, <sac@cygnus.com>.
6 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
7
8 This file is part of BFD, the Binary File Descriptor library.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24#include "bfd.h"
25#include "sysdep.h"
26#include "libiberty.h"
27#include "libbfd.h"
28#include "bfdlink.h"
29#include "coff/sh.h"
30#include "coff/internal.h"
31
32#ifdef COFF_WITH_PE
33#include "coff/pe.h"
34
35#ifndef COFF_IMAGE_WITH_PE
36static bfd_boolean sh_align_load_span
37 PARAMS ((bfd *, asection *, bfd_byte *,
38 bfd_boolean (*) (bfd *, asection *, PTR, bfd_byte *, bfd_vma),
39 PTR, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, bfd_boolean *));
40
41#define _bfd_sh_align_load_span sh_align_load_span
42#endif
43#endif
44
45#include "libcoff.h"
46
47/* Internal functions. */
48static bfd_reloc_status_type sh_reloc
49 PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
50static long get_symbol_value PARAMS ((asymbol *));
51static bfd_boolean sh_relax_section
52 PARAMS ((bfd *, asection *, struct bfd_link_info *, bfd_boolean *));
53static bfd_boolean sh_relax_delete_bytes
54 PARAMS ((bfd *, asection *, bfd_vma, int));
55#ifndef COFF_IMAGE_WITH_PE
56static const struct sh_opcode *sh_insn_info PARAMS ((unsigned int));
57#endif
58static bfd_boolean sh_align_loads
59 PARAMS ((bfd *, asection *, struct internal_reloc *, bfd_byte *,
60 bfd_boolean *));
61static bfd_boolean sh_swap_insns
62 PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
63static bfd_boolean sh_relocate_section
64 PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
65 struct internal_reloc *, struct internal_syment *, asection **));
66static bfd_byte *sh_coff_get_relocated_section_contents
67 PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *,
68 bfd_byte *, bfd_boolean, asymbol **));
69static reloc_howto_type * sh_coff_reloc_type_lookup PARAMS ((bfd *, bfd_reloc_code_real_type));
70
71#ifdef COFF_WITH_PE
72/* Can't build import tables with 2**4 alignment. */
73#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2
74#else
75/* Default section alignment to 2**4. */
76#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4
77#endif
78
79#ifdef COFF_IMAGE_WITH_PE
80/* Align PE executables. */
81#define COFF_PAGE_SIZE 0x1000
82#endif
83
84/* Generate long file names. */
85#define COFF_LONG_FILENAMES
86
87#ifdef COFF_WITH_PE
88static bfd_boolean in_reloc_p PARAMS ((bfd *, reloc_howto_type *));
89/* Return TRUE if this relocation should
90 appear in the output .reloc section. */
91static bfd_boolean in_reloc_p (abfd, howto)
92 bfd * abfd ATTRIBUTE_UNUSED;
93 reloc_howto_type * howto;
94{
95 return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE;
96}
97#endif
98
99/* The supported relocations. There are a lot of relocations defined
100 in coff/internal.h which we do not expect to ever see. */
101static reloc_howto_type sh_coff_howtos[] =
102{
103 EMPTY_HOWTO (0),
104 EMPTY_HOWTO (1),
105#ifdef COFF_WITH_PE
106 /* Windows CE */
107 HOWTO (R_SH_IMM32CE, /* type */
108 0, /* rightshift */
109 2, /* size (0 = byte, 1 = short, 2 = long) */
110 32, /* bitsize */
111 FALSE, /* pc_relative */
112 0, /* bitpos */
113 complain_overflow_bitfield, /* complain_on_overflow */
114 sh_reloc, /* special_function */
115 "r_imm32ce", /* name */
116 TRUE, /* partial_inplace */
117 0xffffffff, /* src_mask */
118 0xffffffff, /* dst_mask */
119 FALSE), /* pcrel_offset */
120#else
121 EMPTY_HOWTO (2),
122#endif
123 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
124 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
125 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
126 EMPTY_HOWTO (6), /* R_SH_IMM24 */
127 EMPTY_HOWTO (7), /* R_SH_LOW16 */
128 EMPTY_HOWTO (8),
129 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
130
131 HOWTO (R_SH_PCDISP8BY2, /* type */
132 1, /* rightshift */
133 1, /* size (0 = byte, 1 = short, 2 = long) */
134 8, /* bitsize */
135 TRUE, /* pc_relative */
136 0, /* bitpos */
137 complain_overflow_signed, /* complain_on_overflow */
138 sh_reloc, /* special_function */
139 "r_pcdisp8by2", /* name */
140 TRUE, /* partial_inplace */
141 0xff, /* src_mask */
142 0xff, /* dst_mask */
143 TRUE), /* pcrel_offset */
144
145 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
146
147 HOWTO (R_SH_PCDISP, /* type */
148 1, /* rightshift */
149 1, /* size (0 = byte, 1 = short, 2 = long) */
150 12, /* bitsize */
151 TRUE, /* pc_relative */
152 0, /* bitpos */
153 complain_overflow_signed, /* complain_on_overflow */
154 sh_reloc, /* special_function */
155 "r_pcdisp12by2", /* name */
156 TRUE, /* partial_inplace */
157 0xfff, /* src_mask */
158 0xfff, /* dst_mask */
159 TRUE), /* pcrel_offset */
160
161 EMPTY_HOWTO (13),
162
163 HOWTO (R_SH_IMM32, /* type */
164 0, /* rightshift */
165 2, /* size (0 = byte, 1 = short, 2 = long) */
166 32, /* bitsize */
167 FALSE, /* pc_relative */
168 0, /* bitpos */
169 complain_overflow_bitfield, /* complain_on_overflow */
170 sh_reloc, /* special_function */
171 "r_imm32", /* name */
172 TRUE, /* partial_inplace */
173 0xffffffff, /* src_mask */
174 0xffffffff, /* dst_mask */
175 FALSE), /* pcrel_offset */
176
177 EMPTY_HOWTO (15),
178#ifdef COFF_WITH_PE
179 HOWTO (R_SH_IMAGEBASE, /* type */
180 0, /* rightshift */
181 2, /* size (0 = byte, 1 = short, 2 = long) */
182 32, /* bitsize */
183 FALSE, /* pc_relative */
184 0, /* bitpos */
185 complain_overflow_bitfield, /* complain_on_overflow */
186 sh_reloc, /* special_function */
187 "rva32", /* name */
188 TRUE, /* partial_inplace */
189 0xffffffff, /* src_mask */
190 0xffffffff, /* dst_mask */
191 FALSE), /* pcrel_offset */
192#else
193 EMPTY_HOWTO (16), /* R_SH_IMM8 */
194#endif
195 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
196 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
197 EMPTY_HOWTO (19), /* R_SH_IMM4 */
198 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
199 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
200
201 HOWTO (R_SH_PCRELIMM8BY2, /* type */
202 1, /* rightshift */
203 1, /* size (0 = byte, 1 = short, 2 = long) */
204 8, /* bitsize */
205 TRUE, /* pc_relative */
206 0, /* bitpos */
207 complain_overflow_unsigned, /* complain_on_overflow */
208 sh_reloc, /* special_function */
209 "r_pcrelimm8by2", /* name */
210 TRUE, /* partial_inplace */
211 0xff, /* src_mask */
212 0xff, /* dst_mask */
213 TRUE), /* pcrel_offset */
214
215 HOWTO (R_SH_PCRELIMM8BY4, /* type */
216 2, /* rightshift */
217 1, /* size (0 = byte, 1 = short, 2 = long) */
218 8, /* bitsize */
219 TRUE, /* pc_relative */
220 0, /* bitpos */
221 complain_overflow_unsigned, /* complain_on_overflow */
222 sh_reloc, /* special_function */
223 "r_pcrelimm8by4", /* name */
224 TRUE, /* partial_inplace */
225 0xff, /* src_mask */
226 0xff, /* dst_mask */
227 TRUE), /* pcrel_offset */
228
229 HOWTO (R_SH_IMM16, /* type */
230 0, /* rightshift */
231 1, /* size (0 = byte, 1 = short, 2 = long) */
232 16, /* bitsize */
233 FALSE, /* pc_relative */
234 0, /* bitpos */
235 complain_overflow_bitfield, /* complain_on_overflow */
236 sh_reloc, /* special_function */
237 "r_imm16", /* name */
238 TRUE, /* partial_inplace */
239 0xffff, /* src_mask */
240 0xffff, /* dst_mask */
241 FALSE), /* pcrel_offset */
242
243 HOWTO (R_SH_SWITCH16, /* type */
244 0, /* rightshift */
245 1, /* size (0 = byte, 1 = short, 2 = long) */
246 16, /* bitsize */
247 FALSE, /* pc_relative */
248 0, /* bitpos */
249 complain_overflow_bitfield, /* complain_on_overflow */
250 sh_reloc, /* special_function */
251 "r_switch16", /* name */
252 TRUE, /* partial_inplace */
253 0xffff, /* src_mask */
254 0xffff, /* dst_mask */
255 FALSE), /* pcrel_offset */
256
257 HOWTO (R_SH_SWITCH32, /* type */
258 0, /* rightshift */
259 2, /* size (0 = byte, 1 = short, 2 = long) */
260 32, /* bitsize */
261 FALSE, /* pc_relative */
262 0, /* bitpos */
263 complain_overflow_bitfield, /* complain_on_overflow */
264 sh_reloc, /* special_function */
265 "r_switch32", /* name */
266 TRUE, /* partial_inplace */
267 0xffffffff, /* src_mask */
268 0xffffffff, /* dst_mask */
269 FALSE), /* pcrel_offset */
270
271 HOWTO (R_SH_USES, /* type */
272 0, /* rightshift */
273 1, /* size (0 = byte, 1 = short, 2 = long) */
274 16, /* bitsize */
275 FALSE, /* pc_relative */
276 0, /* bitpos */
277 complain_overflow_bitfield, /* complain_on_overflow */
278 sh_reloc, /* special_function */
279 "r_uses", /* name */
280 TRUE, /* partial_inplace */
281 0xffff, /* src_mask */
282 0xffff, /* dst_mask */
283 FALSE), /* pcrel_offset */
284
285 HOWTO (R_SH_COUNT, /* type */
286 0, /* rightshift */
287 2, /* size (0 = byte, 1 = short, 2 = long) */
288 32, /* bitsize */
289 FALSE, /* pc_relative */
290 0, /* bitpos */
291 complain_overflow_bitfield, /* complain_on_overflow */
292 sh_reloc, /* special_function */
293 "r_count", /* name */
294 TRUE, /* partial_inplace */
295 0xffffffff, /* src_mask */
296 0xffffffff, /* dst_mask */
297 FALSE), /* pcrel_offset */
298
299 HOWTO (R_SH_ALIGN, /* type */
300 0, /* rightshift */
301 2, /* size (0 = byte, 1 = short, 2 = long) */
302 32, /* bitsize */
303 FALSE, /* pc_relative */
304 0, /* bitpos */
305 complain_overflow_bitfield, /* complain_on_overflow */
306 sh_reloc, /* special_function */
307 "r_align", /* name */
308 TRUE, /* partial_inplace */
309 0xffffffff, /* src_mask */
310 0xffffffff, /* dst_mask */
311 FALSE), /* pcrel_offset */
312
313 HOWTO (R_SH_CODE, /* type */
314 0, /* rightshift */
315 2, /* size (0 = byte, 1 = short, 2 = long) */
316 32, /* bitsize */
317 FALSE, /* pc_relative */
318 0, /* bitpos */
319 complain_overflow_bitfield, /* complain_on_overflow */
320 sh_reloc, /* special_function */
321 "r_code", /* name */
322 TRUE, /* partial_inplace */
323 0xffffffff, /* src_mask */
324 0xffffffff, /* dst_mask */
325 FALSE), /* pcrel_offset */
326
327 HOWTO (R_SH_DATA, /* type */
328 0, /* rightshift */
329 2, /* size (0 = byte, 1 = short, 2 = long) */
330 32, /* bitsize */
331 FALSE, /* pc_relative */
332 0, /* bitpos */
333 complain_overflow_bitfield, /* complain_on_overflow */
334 sh_reloc, /* special_function */
335 "r_data", /* name */
336 TRUE, /* partial_inplace */
337 0xffffffff, /* src_mask */
338 0xffffffff, /* dst_mask */
339 FALSE), /* pcrel_offset */
340
341 HOWTO (R_SH_LABEL, /* type */
342 0, /* rightshift */
343 2, /* size (0 = byte, 1 = short, 2 = long) */
344 32, /* bitsize */
345 FALSE, /* pc_relative */
346 0, /* bitpos */
347 complain_overflow_bitfield, /* complain_on_overflow */
348 sh_reloc, /* special_function */
349 "r_label", /* name */
350 TRUE, /* partial_inplace */
351 0xffffffff, /* src_mask */
352 0xffffffff, /* dst_mask */
353 FALSE), /* pcrel_offset */
354
355 HOWTO (R_SH_SWITCH8, /* type */
356 0, /* rightshift */
357 0, /* size (0 = byte, 1 = short, 2 = long) */
358 8, /* bitsize */
359 FALSE, /* pc_relative */
360 0, /* bitpos */
361 complain_overflow_bitfield, /* complain_on_overflow */
362 sh_reloc, /* special_function */
363 "r_switch8", /* name */
364 TRUE, /* partial_inplace */
365 0xff, /* src_mask */
366 0xff, /* dst_mask */
367 FALSE) /* pcrel_offset */
368};
369
370#define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
371
372/* Check for a bad magic number. */
373#define BADMAG(x) SHBADMAG(x)
374
375/* Customize coffcode.h (this is not currently used). */
376#define SH 1
377
378/* FIXME: This should not be set here. */
379#define __A_MAGIC_SET__
380
381#ifndef COFF_WITH_PE
382/* Swap the r_offset field in and out. */
383#define SWAP_IN_RELOC_OFFSET H_GET_32
384#define SWAP_OUT_RELOC_OFFSET H_PUT_32
385
386/* Swap out extra information in the reloc structure. */
387#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
388 do \
389 { \
390 dst->r_stuff[0] = 'S'; \
391 dst->r_stuff[1] = 'C'; \
392 } \
393 while (0)
394#endif
395
396/* Get the value of a symbol, when performing a relocation. */
397
398static long
399get_symbol_value (symbol)
400 asymbol *symbol;
401{
402 bfd_vma relocation;
403
404 if (bfd_is_com_section (symbol->section))
405 relocation = 0;
406 else
407 relocation = (symbol->value +
408 symbol->section->output_section->vma +
409 symbol->section->output_offset);
410
411 return relocation;
412}
413
414#ifdef COFF_WITH_PE
415/* Convert an rtype to howto for the COFF backend linker.
416 Copied from coff-i386. */
417#define coff_rtype_to_howto coff_sh_rtype_to_howto
418static reloc_howto_type * coff_sh_rtype_to_howto PARAMS ((bfd *, asection *, struct internal_reloc *, struct coff_link_hash_entry *, struct internal_syment *, bfd_vma *));
419
420static reloc_howto_type *
421coff_sh_rtype_to_howto (abfd, sec, rel, h, sym, addendp)
422 bfd * abfd ATTRIBUTE_UNUSED;
423 asection * sec;
424 struct internal_reloc * rel;
425 struct coff_link_hash_entry * h;
426 struct internal_syment * sym;
427 bfd_vma * addendp;
428{
429 reloc_howto_type * howto;
430
431 howto = sh_coff_howtos + rel->r_type;
432
433 *addendp = 0;
434
435 if (howto->pc_relative)
436 *addendp += sec->vma;
437
438 if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0)
439 {
440 /* This is a common symbol. The section contents include the
441 size (sym->n_value) as an addend. The relocate_section
442 function will be adding in the final value of the symbol. We
443 need to subtract out the current size in order to get the
444 correct result. */
445 BFD_ASSERT (h != NULL);
446 }
447
448 if (howto->pc_relative)
449 {
450 *addendp -= 4;
451
452 /* If the symbol is defined, then the generic code is going to
453 add back the symbol value in order to cancel out an
454 adjustment it made to the addend. However, we set the addend
455 to 0 at the start of this function. We need to adjust here,
456 to avoid the adjustment the generic code will make. FIXME:
457 This is getting a bit hackish. */
458 if (sym != NULL && sym->n_scnum != 0)
459 *addendp -= sym->n_value;
460 }
461
462 if (rel->r_type == R_SH_IMAGEBASE)
463 *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase;
464
465 return howto;
466}
467
468#endif /* COFF_WITH_PE */
469
470/* This structure is used to map BFD reloc codes to SH PE relocs. */
471struct shcoff_reloc_map
472{
473 bfd_reloc_code_real_type bfd_reloc_val;
474 unsigned char shcoff_reloc_val;
475};
476
477#ifdef COFF_WITH_PE
478/* An array mapping BFD reloc codes to SH PE relocs. */
479static const struct shcoff_reloc_map sh_reloc_map[] =
480{
481 { BFD_RELOC_32, R_SH_IMM32CE },
482 { BFD_RELOC_RVA, R_SH_IMAGEBASE },
483 { BFD_RELOC_CTOR, R_SH_IMM32CE },
484};
485#else
486/* An array mapping BFD reloc codes to SH PE relocs. */
487static const struct shcoff_reloc_map sh_reloc_map[] =
488{
489 { BFD_RELOC_32, R_SH_IMM32 },
490 { BFD_RELOC_CTOR, R_SH_IMM32 },
491};
492#endif
493
494/* Given a BFD reloc code, return the howto structure for the
495 corresponding SH PE reloc. */
496#define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
497
498static reloc_howto_type *
499sh_coff_reloc_type_lookup (abfd, code)
500 bfd * abfd ATTRIBUTE_UNUSED;
501 bfd_reloc_code_real_type code;
502{
503 unsigned int i;
504
505 for (i = ARRAY_SIZE (sh_reloc_map); i--;)
506 if (sh_reloc_map[i].bfd_reloc_val == code)
507 return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val];
508
509 fprintf (stderr, "SH Error: unknown reloc type %d\n", code);
510 return NULL;
511}
512
513/* This macro is used in coffcode.h to get the howto corresponding to
514 an internal reloc. */
515
516#define RTYPE2HOWTO(relent, internal) \
517 ((relent)->howto = \
518 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
519 ? &sh_coff_howtos[(internal)->r_type] \
520 : (reloc_howto_type *) NULL))
521
522/* This is the same as the macro in coffcode.h, except that it copies
523 r_offset into reloc_entry->addend for some relocs. */
524#define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
525 { \
526 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
527 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
528 coffsym = (obj_symbols (abfd) \
529 + (cache_ptr->sym_ptr_ptr - symbols)); \
530 else if (ptr) \
531 coffsym = coff_symbol_from (abfd, ptr); \
532 if (coffsym != (coff_symbol_type *) NULL \
533 && coffsym->native->u.syment.n_scnum == 0) \
534 cache_ptr->addend = 0; \
535 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
536 && ptr->section != (asection *) NULL) \
537 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
538 else \
539 cache_ptr->addend = 0; \
540 if ((reloc).r_type == R_SH_SWITCH8 \
541 || (reloc).r_type == R_SH_SWITCH16 \
542 || (reloc).r_type == R_SH_SWITCH32 \
543 || (reloc).r_type == R_SH_USES \
544 || (reloc).r_type == R_SH_COUNT \
545 || (reloc).r_type == R_SH_ALIGN) \
546 cache_ptr->addend = (reloc).r_offset; \
547 }
548
549/* This is the howto function for the SH relocations. */
550
551static bfd_reloc_status_type
552sh_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd,
553 error_message)
554 bfd *abfd;
555 arelent *reloc_entry;
556 asymbol *symbol_in;
557 PTR data;
558 asection *input_section;
559 bfd *output_bfd;
560 char **error_message ATTRIBUTE_UNUSED;
561{
562 unsigned long insn;
563 bfd_vma sym_value;
564 unsigned short r_type;
565 bfd_vma addr = reloc_entry->address;
566 bfd_byte *hit_data = addr + (bfd_byte *) data;
567
568 r_type = reloc_entry->howto->type;
569
570 if (output_bfd != NULL)
571 {
572 /* Partial linking--do nothing. */
573 reloc_entry->address += input_section->output_offset;
574 return bfd_reloc_ok;
575 }
576
577 /* Almost all relocs have to do with relaxing. If any work must be
578 done for them, it has been done in sh_relax_section. */
579 if (r_type != R_SH_IMM32
580#ifdef COFF_WITH_PE
581 && r_type != R_SH_IMM32CE
582 && r_type != R_SH_IMAGEBASE
583#endif
584 && (r_type != R_SH_PCDISP
585 || (symbol_in->flags & BSF_LOCAL) != 0))
586 return bfd_reloc_ok;
587
588 if (symbol_in != NULL
589 && bfd_is_und_section (symbol_in->section))
590 return bfd_reloc_undefined;
591
592 sym_value = get_symbol_value (symbol_in);
593
594 switch (r_type)
595 {
596 case R_SH_IMM32:
597#ifdef COFF_WITH_PE
598 case R_SH_IMM32CE:
599#endif
600 insn = bfd_get_32 (abfd, hit_data);
601 insn += sym_value + reloc_entry->addend;
602 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
603 break;
604#ifdef COFF_WITH_PE
605 case R_SH_IMAGEBASE:
606 insn = bfd_get_32 (abfd, hit_data);
607 insn += sym_value + reloc_entry->addend;
608 insn -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
609 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
610 break;
611#endif
612 case R_SH_PCDISP:
613 insn = bfd_get_16 (abfd, hit_data);
614 sym_value += reloc_entry->addend;
615 sym_value -= (input_section->output_section->vma
616 + input_section->output_offset
617 + addr
618 + 4);
619 sym_value += (insn & 0xfff) << 1;
620 if (insn & 0x800)
621 sym_value -= 0x1000;
622 insn = (insn & 0xf000) | (sym_value & 0xfff);
623 bfd_put_16 (abfd, (bfd_vma) insn, hit_data);
624 if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000)
625 return bfd_reloc_overflow;
626 break;
627 default:
628 abort ();
629 break;
630 }
631
632 return bfd_reloc_ok;
633}
634
635#define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
636
637/* We can do relaxing. */
638#define coff_bfd_relax_section sh_relax_section
639
640/* We use the special COFF backend linker. */
641#define coff_relocate_section sh_relocate_section
642
643/* When relaxing, we need to use special code to get the relocated
644 section contents. */
645#define coff_bfd_get_relocated_section_contents \
646 sh_coff_get_relocated_section_contents
647
648#include "coffcode.h"
649
650
651/* This function handles relaxing on the SH.
652
653 Function calls on the SH look like this:
654
655 movl L1,r0
656 ...
657 jsr @r0
658 ...
659 L1:
660 .long function
661
662 The compiler and assembler will cooperate to create R_SH_USES
663 relocs on the jsr instructions. The r_offset field of the
664 R_SH_USES reloc is the PC relative offset to the instruction which
665 loads the register (the r_offset field is computed as though it
666 were a jump instruction, so the offset value is actually from four
667 bytes past the instruction). The linker can use this reloc to
668 determine just which function is being called, and thus decide
669 whether it is possible to replace the jsr with a bsr.
670
671 If multiple function calls are all based on a single register load
672 (i.e., the same function is called multiple times), the compiler
673 guarantees that each function call will have an R_SH_USES reloc.
674 Therefore, if the linker is able to convert each R_SH_USES reloc
675 which refers to that address, it can safely eliminate the register
676 load.
677
678 When the assembler creates an R_SH_USES reloc, it examines it to
679 determine which address is being loaded (L1 in the above example).
680 It then counts the number of references to that address, and
681 creates an R_SH_COUNT reloc at that address. The r_offset field of
682 the R_SH_COUNT reloc will be the number of references. If the
683 linker is able to eliminate a register load, it can use the
684 R_SH_COUNT reloc to see whether it can also eliminate the function
685 address.
686
687 SH relaxing also handles another, unrelated, matter. On the SH, if
688 a load or store instruction is not aligned on a four byte boundary,
689 the memory cycle interferes with the 32 bit instruction fetch,
690 causing a one cycle bubble in the pipeline. Therefore, we try to
691 align load and store instructions on four byte boundaries if we
692 can, by swapping them with one of the adjacent instructions. */
693
694static bfd_boolean
695sh_relax_section (abfd, sec, link_info, again)
696 bfd *abfd;
697 asection *sec;
698 struct bfd_link_info *link_info;
699 bfd_boolean *again;
700{
701 struct internal_reloc *internal_relocs;
702 struct internal_reloc *free_relocs = NULL;
703 bfd_boolean have_code;
704 struct internal_reloc *irel, *irelend;
705 bfd_byte *contents = NULL;
706 bfd_byte *free_contents = NULL;
707
708 *again = FALSE;
709
710 if (link_info->relocateable
711 || (sec->flags & SEC_RELOC) == 0
712 || sec->reloc_count == 0)
713 return TRUE;
714
715 /* If this is the first time we have been called for this section,
716 initialize the cooked size. */
717 if (sec->_cooked_size == 0)
718 sec->_cooked_size = sec->_raw_size;
719
720 internal_relocs = (_bfd_coff_read_internal_relocs
721 (abfd, sec, link_info->keep_memory,
722 (bfd_byte *) NULL, FALSE,
723 (struct internal_reloc *) NULL));
724 if (internal_relocs == NULL)
725 goto error_return;
726 if (! link_info->keep_memory)
727 free_relocs = internal_relocs;
728
729 have_code = FALSE;
730
731 irelend = internal_relocs + sec->reloc_count;
732 for (irel = internal_relocs; irel < irelend; irel++)
733 {
734 bfd_vma laddr, paddr, symval;
735 unsigned short insn;
736 struct internal_reloc *irelfn, *irelscan, *irelcount;
737 struct internal_syment sym;
738 bfd_signed_vma foff;
739
740 if (irel->r_type == R_SH_CODE)
741 have_code = TRUE;
742
743 if (irel->r_type != R_SH_USES)
744 continue;
745
746 /* Get the section contents. */
747 if (contents == NULL)
748 {
749 if (coff_section_data (abfd, sec) != NULL
750 && coff_section_data (abfd, sec)->contents != NULL)
751 contents = coff_section_data (abfd, sec)->contents;
752 else
753 {
754 contents = (bfd_byte *) bfd_malloc (sec->_raw_size);
755 if (contents == NULL)
756 goto error_return;
757 free_contents = contents;
758
759 if (! bfd_get_section_contents (abfd, sec, contents,
760 (file_ptr) 0, sec->_raw_size))
761 goto error_return;
762 }
763 }
764
765 /* The r_offset field of the R_SH_USES reloc will point us to
766 the register load. The 4 is because the r_offset field is
767 computed as though it were a jump offset, which are based
768 from 4 bytes after the jump instruction. */
769 laddr = irel->r_vaddr - sec->vma + 4;
770 /* Careful to sign extend the 32-bit offset. */
771 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
772 if (laddr >= sec->_raw_size)
773 {
774 (*_bfd_error_handler) ("%s: 0x%lx: warning: bad R_SH_USES offset",
775 bfd_archive_filename (abfd),
776 (unsigned long) irel->r_vaddr);
777 continue;
778 }
779 insn = bfd_get_16 (abfd, contents + laddr);
780
781 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
782 if ((insn & 0xf000) != 0xd000)
783 {
784 ((*_bfd_error_handler)
785 ("%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x",
786 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr, insn));
787 continue;
788 }
789
790 /* Get the address from which the register is being loaded. The
791 displacement in the mov.l instruction is quadrupled. It is a
792 displacement from four bytes after the movl instruction, but,
793 before adding in the PC address, two least significant bits
794 of the PC are cleared. We assume that the section is aligned
795 on a four byte boundary. */
796 paddr = insn & 0xff;
797 paddr *= 4;
798 paddr += (laddr + 4) &~ (bfd_vma) 3;
799 if (paddr >= sec->_raw_size)
800 {
801 ((*_bfd_error_handler)
802 ("%s: 0x%lx: warning: bad R_SH_USES load offset",
803 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr));
804 continue;
805 }
806
807 /* Get the reloc for the address from which the register is
808 being loaded. This reloc will tell us which function is
809 actually being called. */
810 paddr += sec->vma;
811 for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
812 if (irelfn->r_vaddr == paddr
813#ifdef COFF_WITH_PE
814 && (irelfn->r_type == R_SH_IMM32
815 || irelfn->r_type == R_SH_IMM32CE
816 || irelfn->r_type == R_SH_IMAGEBASE))
817
818#else
819 && irelfn->r_type == R_SH_IMM32)
820#endif
821 break;
822 if (irelfn >= irelend)
823 {
824 ((*_bfd_error_handler)
825 ("%s: 0x%lx: warning: could not find expected reloc",
826 bfd_archive_filename (abfd), (unsigned long) paddr));
827 continue;
828 }
829
830 /* Get the value of the symbol referred to by the reloc. */
831 if (! _bfd_coff_get_external_symbols (abfd))
832 goto error_return;
833 bfd_coff_swap_sym_in (abfd,
834 ((bfd_byte *) obj_coff_external_syms (abfd)
835 + (irelfn->r_symndx
836 * bfd_coff_symesz (abfd))),
837 &sym);
838 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
839 {
840 ((*_bfd_error_handler)
841 ("%s: 0x%lx: warning: symbol in unexpected section",
842 bfd_archive_filename (abfd), (unsigned long) paddr));
843 continue;
844 }
845
846 if (sym.n_sclass != C_EXT)
847 {
848 symval = (sym.n_value
849 - sec->vma
850 + sec->output_section->vma
851 + sec->output_offset);
852 }
853 else
854 {
855 struct coff_link_hash_entry *h;
856
857 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
858 BFD_ASSERT (h != NULL);
859 if (h->root.type != bfd_link_hash_defined
860 && h->root.type != bfd_link_hash_defweak)
861 {
862 /* This appears to be a reference to an undefined
863 symbol. Just ignore it--it will be caught by the
864 regular reloc processing. */
865 continue;
866 }
867
868 symval = (h->root.u.def.value
869 + h->root.u.def.section->output_section->vma
870 + h->root.u.def.section->output_offset);
871 }
872
873 symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
874
875 /* See if this function call can be shortened. */
876 foff = (symval
877 - (irel->r_vaddr
878 - sec->vma
879 + sec->output_section->vma
880 + sec->output_offset
881 + 4));
882 if (foff < -0x1000 || foff >= 0x1000)
883 {
884 /* After all that work, we can't shorten this function call. */
885 continue;
886 }
887
888 /* Shorten the function call. */
889
890 /* For simplicity of coding, we are going to modify the section
891 contents, the section relocs, and the BFD symbol table. We
892 must tell the rest of the code not to free up this
893 information. It would be possible to instead create a table
894 of changes which have to be made, as is done in coff-mips.c;
895 that would be more work, but would require less memory when
896 the linker is run. */
897
898 if (coff_section_data (abfd, sec) == NULL)
899 {
900 bfd_size_type amt = sizeof (struct coff_section_tdata);
901 sec->used_by_bfd = (PTR) bfd_zalloc (abfd, amt);
902 if (sec->used_by_bfd == NULL)
903 goto error_return;
904 }
905
906 coff_section_data (abfd, sec)->relocs = internal_relocs;
907 coff_section_data (abfd, sec)->keep_relocs = TRUE;
908 free_relocs = NULL;
909
910 coff_section_data (abfd, sec)->contents = contents;
911 coff_section_data (abfd, sec)->keep_contents = TRUE;
912 free_contents = NULL;
913
914 obj_coff_keep_syms (abfd) = TRUE;
915
916 /* Replace the jsr with a bsr. */
917
918 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
919 replace the jsr with a bsr. */
920 irel->r_type = R_SH_PCDISP;
921 irel->r_symndx = irelfn->r_symndx;
922 if (sym.n_sclass != C_EXT)
923 {
924 /* If this needs to be changed because of future relaxing,
925 it will be handled here like other internal PCDISP
926 relocs. */
927 bfd_put_16 (abfd,
928 (bfd_vma) 0xb000 | ((foff >> 1) & 0xfff),
929 contents + irel->r_vaddr - sec->vma);
930 }
931 else
932 {
933 /* We can't fully resolve this yet, because the external
934 symbol value may be changed by future relaxing. We let
935 the final link phase handle it. */
936 bfd_put_16 (abfd, (bfd_vma) 0xb000,
937 contents + irel->r_vaddr - sec->vma);
938 }
939
940 /* See if there is another R_SH_USES reloc referring to the same
941 register load. */
942 for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
943 if (irelscan->r_type == R_SH_USES
944 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
945 break;
946 if (irelscan < irelend)
947 {
948 /* Some other function call depends upon this register load,
949 and we have not yet converted that function call.
950 Indeed, we may never be able to convert it. There is
951 nothing else we can do at this point. */
952 continue;
953 }
954
955 /* Look for a R_SH_COUNT reloc on the location where the
956 function address is stored. Do this before deleting any
957 bytes, to avoid confusion about the address. */
958 for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
959 if (irelcount->r_vaddr == paddr
960 && irelcount->r_type == R_SH_COUNT)
961 break;
962
963 /* Delete the register load. */
964 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
965 goto error_return;
966
967 /* That will change things, so, just in case it permits some
968 other function call to come within range, we should relax
969 again. Note that this is not required, and it may be slow. */
970 *again = TRUE;
971
972 /* Now check whether we got a COUNT reloc. */
973 if (irelcount >= irelend)
974 {
975 ((*_bfd_error_handler)
976 ("%s: 0x%lx: warning: could not find expected COUNT reloc",
977 bfd_archive_filename (abfd), (unsigned long) paddr));
978 continue;
979 }
980
981 /* The number of uses is stored in the r_offset field. We've
982 just deleted one. */
983 if (irelcount->r_offset == 0)
984 {
985 ((*_bfd_error_handler) ("%s: 0x%lx: warning: bad count",
986 bfd_archive_filename (abfd),
987 (unsigned long) paddr));
988 continue;
989 }
990
991 --irelcount->r_offset;
992
993 /* If there are no more uses, we can delete the address. Reload
994 the address from irelfn, in case it was changed by the
995 previous call to sh_relax_delete_bytes. */
996 if (irelcount->r_offset == 0)
997 {
998 if (! sh_relax_delete_bytes (abfd, sec,
999 irelfn->r_vaddr - sec->vma, 4))
1000 goto error_return;
1001 }
1002
1003 /* We've done all we can with that function call. */
1004 }
1005
1006 /* Look for load and store instructions that we can align on four
1007 byte boundaries. */
1008 if (have_code)
1009 {
1010 bfd_boolean swapped;
1011
1012 /* Get the section contents. */
1013 if (contents == NULL)
1014 {
1015 if (coff_section_data (abfd, sec) != NULL
1016 && coff_section_data (abfd, sec)->contents != NULL)
1017 contents = coff_section_data (abfd, sec)->contents;
1018 else
1019 {
1020 contents = (bfd_byte *) bfd_malloc (sec->_raw_size);
1021 if (contents == NULL)
1022 goto error_return;
1023 free_contents = contents;
1024
1025 if (! bfd_get_section_contents (abfd, sec, contents,
1026 (file_ptr) 0, sec->_raw_size))
1027 goto error_return;
1028 }
1029 }
1030
1031 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
1032 goto error_return;
1033
1034 if (swapped)
1035 {
1036 if (coff_section_data (abfd, sec) == NULL)
1037 {
1038 bfd_size_type amt = sizeof (struct coff_section_tdata);
1039 sec->used_by_bfd = (PTR) bfd_zalloc (abfd, amt);
1040 if (sec->used_by_bfd == NULL)
1041 goto error_return;
1042 }
1043
1044 coff_section_data (abfd, sec)->relocs = internal_relocs;
1045 coff_section_data (abfd, sec)->keep_relocs = TRUE;
1046 free_relocs = NULL;
1047
1048 coff_section_data (abfd, sec)->contents = contents;
1049 coff_section_data (abfd, sec)->keep_contents = TRUE;
1050 free_contents = NULL;
1051
1052 obj_coff_keep_syms (abfd) = TRUE;
1053 }
1054 }
1055
1056 if (free_relocs != NULL)
1057 {
1058 free (free_relocs);
1059 free_relocs = NULL;
1060 }
1061
1062 if (free_contents != NULL)
1063 {
1064 if (! link_info->keep_memory)
1065 free (free_contents);
1066 else
1067 {
1068 /* Cache the section contents for coff_link_input_bfd. */
1069 if (coff_section_data (abfd, sec) == NULL)
1070 {
1071 bfd_size_type amt = sizeof (struct coff_section_tdata);
1072 sec->used_by_bfd = (PTR) bfd_zalloc (abfd, amt);
1073 if (sec->used_by_bfd == NULL)
1074 goto error_return;
1075 coff_section_data (abfd, sec)->relocs = NULL;
1076 }
1077 coff_section_data (abfd, sec)->contents = contents;
1078 }
1079 }
1080
1081 return TRUE;
1082
1083 error_return:
1084 if (free_relocs != NULL)
1085 free (free_relocs);
1086 if (free_contents != NULL)
1087 free (free_contents);
1088 return FALSE;
1089}
1090
1091/* Delete some bytes from a section while relaxing. */
1092
1093static bfd_boolean
1094sh_relax_delete_bytes (abfd, sec, addr, count)
1095 bfd *abfd;
1096 asection *sec;
1097 bfd_vma addr;
1098 int count;
1099{
1100 bfd_byte *contents;
1101 struct internal_reloc *irel, *irelend;
1102 struct internal_reloc *irelalign;
1103 bfd_vma toaddr;
1104 bfd_byte *esym, *esymend;
1105 bfd_size_type symesz;
1106 struct coff_link_hash_entry **sym_hash;
1107 asection *o;
1108
1109 contents = coff_section_data (abfd, sec)->contents;
1110
1111 /* The deletion must stop at the next ALIGN reloc for an aligment
1112 power larger than the number of bytes we are deleting. */
1113
1114 irelalign = NULL;
1115 toaddr = sec->_cooked_size;
1116
1117 irel = coff_section_data (abfd, sec)->relocs;
1118 irelend = irel + sec->reloc_count;
1119 for (; irel < irelend; irel++)
1120 {
1121 if (irel->r_type == R_SH_ALIGN
1122 && irel->r_vaddr - sec->vma > addr
1123 && count < (1 << irel->r_offset))
1124 {
1125 irelalign = irel;
1126 toaddr = irel->r_vaddr - sec->vma;
1127 break;
1128 }
1129 }
1130
1131 /* Actually delete the bytes. */
1132 memmove (contents + addr, contents + addr + count,
1133 (size_t) (toaddr - addr - count));
1134 if (irelalign == NULL)
1135 sec->_cooked_size -= count;
1136 else
1137 {
1138 int i;
1139
1140#define NOP_OPCODE (0x0009)
1141
1142 BFD_ASSERT ((count & 1) == 0);
1143 for (i = 0; i < count; i += 2)
1144 bfd_put_16 (abfd, (bfd_vma) NOP_OPCODE, contents + toaddr - count + i);
1145 }
1146
1147 /* Adjust all the relocs. */
1148 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
1149 {
1150 bfd_vma nraddr, stop;
1151 bfd_vma start = 0;
1152 int insn = 0;
1153 struct internal_syment sym;
1154 int off, adjust, oinsn;
1155 bfd_signed_vma voff = 0;
1156 bfd_boolean overflow;
1157
1158 /* Get the new reloc address. */
1159 nraddr = irel->r_vaddr - sec->vma;
1160 if ((irel->r_vaddr - sec->vma > addr
1161 && irel->r_vaddr - sec->vma < toaddr)
1162 || (irel->r_type == R_SH_ALIGN
1163 && irel->r_vaddr - sec->vma == toaddr))
1164 nraddr -= count;
1165
1166 /* See if this reloc was for the bytes we have deleted, in which
1167 case we no longer care about it. Don't delete relocs which
1168 represent addresses, though. */
1169 if (irel->r_vaddr - sec->vma >= addr
1170 && irel->r_vaddr - sec->vma < addr + count
1171 && irel->r_type != R_SH_ALIGN
1172 && irel->r_type != R_SH_CODE
1173 && irel->r_type != R_SH_DATA
1174 && irel->r_type != R_SH_LABEL)
1175 irel->r_type = R_SH_UNUSED;
1176
1177 /* If this is a PC relative reloc, see if the range it covers
1178 includes the bytes we have deleted. */
1179 switch (irel->r_type)
1180 {
1181 default:
1182 break;
1183
1184 case R_SH_PCDISP8BY2:
1185 case R_SH_PCDISP:
1186 case R_SH_PCRELIMM8BY2:
1187 case R_SH_PCRELIMM8BY4:
1188 start = irel->r_vaddr - sec->vma;
1189 insn = bfd_get_16 (abfd, contents + nraddr);
1190 break;
1191 }
1192
1193 switch (irel->r_type)
1194 {
1195 default:
1196 start = stop = addr;
1197 break;
1198
1199 case R_SH_IMM32:
1200#ifdef COFF_WITH_PE
1201 case R_SH_IMM32CE:
1202 case R_SH_IMAGEBASE:
1203#endif
1204 /* If this reloc is against a symbol defined in this
1205 section, and the symbol will not be adjusted below, we
1206 must check the addend to see it will put the value in
1207 range to be adjusted, and hence must be changed. */
1208 bfd_coff_swap_sym_in (abfd,
1209 ((bfd_byte *) obj_coff_external_syms (abfd)
1210 + (irel->r_symndx
1211 * bfd_coff_symesz (abfd))),
1212 &sym);
1213 if (sym.n_sclass != C_EXT
1214 && sym.n_scnum == sec->target_index
1215 && ((bfd_vma) sym.n_value <= addr
1216 || (bfd_vma) sym.n_value >= toaddr))
1217 {
1218 bfd_vma val;
1219
1220 val = bfd_get_32 (abfd, contents + nraddr);
1221 val += sym.n_value;
1222 if (val > addr && val < toaddr)
1223 bfd_put_32 (abfd, val - count, contents + nraddr);
1224 }
1225 start = stop = addr;
1226 break;
1227
1228 case R_SH_PCDISP8BY2:
1229 off = insn & 0xff;
1230 if (off & 0x80)
1231 off -= 0x100;
1232 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1233 break;
1234
1235 case R_SH_PCDISP:
1236 bfd_coff_swap_sym_in (abfd,
1237 ((bfd_byte *) obj_coff_external_syms (abfd)
1238 + (irel->r_symndx
1239 * bfd_coff_symesz (abfd))),
1240 &sym);
1241 if (sym.n_sclass == C_EXT)
1242 start = stop = addr;
1243 else
1244 {
1245 off = insn & 0xfff;
1246 if (off & 0x800)
1247 off -= 0x1000;
1248 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1249 }
1250 break;
1251
1252 case R_SH_PCRELIMM8BY2:
1253 off = insn & 0xff;
1254 stop = start + 4 + off * 2;
1255 break;
1256
1257 case R_SH_PCRELIMM8BY4:
1258 off = insn & 0xff;
1259 stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
1260 break;
1261
1262 case R_SH_SWITCH8:
1263 case R_SH_SWITCH16:
1264 case R_SH_SWITCH32:
1265 /* These relocs types represent
1266 .word L2-L1
1267 The r_offset field holds the difference between the reloc
1268 address and L1. That is the start of the reloc, and
1269 adding in the contents gives us the top. We must adjust
1270 both the r_offset field and the section contents. */
1271
1272 start = irel->r_vaddr - sec->vma;
1273 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
1274
1275 if (start > addr
1276 && start < toaddr
1277 && (stop <= addr || stop >= toaddr))
1278 irel->r_offset += count;
1279 else if (stop > addr
1280 && stop < toaddr
1281 && (start <= addr || start >= toaddr))
1282 irel->r_offset -= count;
1283
1284 start = stop;
1285
1286 if (irel->r_type == R_SH_SWITCH16)
1287 voff = bfd_get_signed_16 (abfd, contents + nraddr);
1288 else if (irel->r_type == R_SH_SWITCH8)
1289 voff = bfd_get_8 (abfd, contents + nraddr);
1290 else
1291 voff = bfd_get_signed_32 (abfd, contents + nraddr);
1292 stop = (bfd_vma) ((bfd_signed_vma) start + voff);
1293
1294 break;
1295
1296 case R_SH_USES:
1297 start = irel->r_vaddr - sec->vma;
1298 stop = (bfd_vma) ((bfd_signed_vma) start
1299 + (long) irel->r_offset
1300 + 4);
1301 break;
1302 }
1303
1304 if (start > addr
1305 && start < toaddr
1306 && (stop <= addr || stop >= toaddr))
1307 adjust = count;
1308 else if (stop > addr
1309 && stop < toaddr
1310 && (start <= addr || start >= toaddr))
1311 adjust = - count;
1312 else
1313 adjust = 0;
1314
1315 if (adjust != 0)
1316 {
1317 oinsn = insn;
1318 overflow = FALSE;
1319 switch (irel->r_type)
1320 {
1321 default:
1322 abort ();
1323 break;
1324
1325 case R_SH_PCDISP8BY2:
1326 case R_SH_PCRELIMM8BY2:
1327 insn += adjust / 2;
1328 if ((oinsn & 0xff00) != (insn & 0xff00))
1329 overflow = TRUE;
1330 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
1331 break;
1332
1333 case R_SH_PCDISP:
1334 insn += adjust / 2;
1335 if ((oinsn & 0xf000) != (insn & 0xf000))
1336 overflow = TRUE;
1337 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
1338 break;
1339
1340 case R_SH_PCRELIMM8BY4:
1341 BFD_ASSERT (adjust == count || count >= 4);
1342 if (count >= 4)
1343 insn += adjust / 4;
1344 else
1345 {
1346 if ((irel->r_vaddr & 3) == 0)
1347 ++insn;
1348 }
1349 if ((oinsn & 0xff00) != (insn & 0xff00))
1350 overflow = TRUE;
1351 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
1352 break;
1353
1354 case R_SH_SWITCH8:
1355 voff += adjust;
1356 if (voff < 0 || voff >= 0xff)
1357 overflow = TRUE;
1358 bfd_put_8 (abfd, (bfd_vma) voff, contents + nraddr);
1359 break;
1360
1361 case R_SH_SWITCH16:
1362 voff += adjust;
1363 if (voff < - 0x8000 || voff >= 0x8000)
1364 overflow = TRUE;
1365 bfd_put_signed_16 (abfd, (bfd_vma) voff, contents + nraddr);
1366 break;
1367
1368 case R_SH_SWITCH32:
1369 voff += adjust;
1370 bfd_put_signed_32 (abfd, (bfd_vma) voff, contents + nraddr);
1371 break;
1372
1373 case R_SH_USES:
1374 irel->r_offset += adjust;
1375 break;
1376 }
1377
1378 if (overflow)
1379 {
1380 ((*_bfd_error_handler)
1381 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
1382 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr));
1383 bfd_set_error (bfd_error_bad_value);
1384 return FALSE;
1385 }
1386 }
1387
1388 irel->r_vaddr = nraddr + sec->vma;
1389 }
1390
1391 /* Look through all the other sections. If there contain any IMM32
1392 relocs against internal symbols which we are not going to adjust
1393 below, we may need to adjust the addends. */
1394 for (o = abfd->sections; o != NULL; o = o->next)
1395 {
1396 struct internal_reloc *internal_relocs;
1397 struct internal_reloc *irelscan, *irelscanend;
1398 bfd_byte *ocontents;
1399
1400 if (o == sec
1401 || (o->flags & SEC_RELOC) == 0
1402 || o->reloc_count == 0)
1403 continue;
1404
1405 /* We always cache the relocs. Perhaps, if info->keep_memory is
1406 FALSE, we should free them, if we are permitted to, when we
1407 leave sh_coff_relax_section. */
1408 internal_relocs = (_bfd_coff_read_internal_relocs
1409 (abfd, o, TRUE, (bfd_byte *) NULL, FALSE,
1410 (struct internal_reloc *) NULL));
1411 if (internal_relocs == NULL)
1412 return FALSE;
1413
1414 ocontents = NULL;
1415 irelscanend = internal_relocs + o->reloc_count;
1416 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
1417 {
1418 struct internal_syment sym;
1419
1420#ifdef COFF_WITH_PE
1421 if (irelscan->r_type != R_SH_IMM32
1422 && irelscan->r_type != R_SH_IMAGEBASE
1423 && irelscan->r_type != R_SH_IMM32CE)
1424#else
1425 if (irelscan->r_type != R_SH_IMM32)
1426#endif
1427 continue;
1428
1429 bfd_coff_swap_sym_in (abfd,
1430 ((bfd_byte *) obj_coff_external_syms (abfd)
1431 + (irelscan->r_symndx
1432 * bfd_coff_symesz (abfd))),
1433 &sym);
1434 if (sym.n_sclass != C_EXT
1435 && sym.n_scnum == sec->target_index
1436 && ((bfd_vma) sym.n_value <= addr
1437 || (bfd_vma) sym.n_value >= toaddr))
1438 {
1439 bfd_vma val;
1440
1441 if (ocontents == NULL)
1442 {
1443 if (coff_section_data (abfd, o)->contents != NULL)
1444 ocontents = coff_section_data (abfd, o)->contents;
1445 else
1446 {
1447 /* We always cache the section contents.
1448 Perhaps, if info->keep_memory is FALSE, we
1449 should free them, if we are permitted to,
1450 when we leave sh_coff_relax_section. */
1451 ocontents = (bfd_byte *) bfd_malloc (o->_raw_size);
1452 if (ocontents == NULL)
1453 return FALSE;
1454 if (! bfd_get_section_contents (abfd, o, ocontents,
1455 (file_ptr) 0,
1456 o->_raw_size))
1457 return FALSE;
1458 coff_section_data (abfd, o)->contents = ocontents;
1459 }
1460 }
1461
1462 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
1463 val += sym.n_value;
1464 if (val > addr && val < toaddr)
1465 bfd_put_32 (abfd, val - count,
1466 ocontents + irelscan->r_vaddr - o->vma);
1467
1468 coff_section_data (abfd, o)->keep_contents = TRUE;
1469 }
1470 }
1471 }
1472
1473 /* Adjusting the internal symbols will not work if something has
1474 already retrieved the generic symbols. It would be possible to
1475 make this work by adjusting the generic symbols at the same time.
1476 However, this case should not arise in normal usage. */
1477 if (obj_symbols (abfd) != NULL
1478 || obj_raw_syments (abfd) != NULL)
1479 {
1480 ((*_bfd_error_handler)
1481 ("%s: fatal: generic symbols retrieved before relaxing",
1482 bfd_archive_filename (abfd)));
1483 bfd_set_error (bfd_error_invalid_operation);
1484 return FALSE;
1485 }
1486
1487 /* Adjust all the symbols. */
1488 sym_hash = obj_coff_sym_hashes (abfd);
1489 symesz = bfd_coff_symesz (abfd);
1490 esym = (bfd_byte *) obj_coff_external_syms (abfd);
1491 esymend = esym + obj_raw_syment_count (abfd) * symesz;
1492 while (esym < esymend)
1493 {
1494 struct internal_syment isym;
1495
1496 bfd_coff_swap_sym_in (abfd, (PTR) esym, (PTR) &isym);
1497
1498 if (isym.n_scnum == sec->target_index
1499 && (bfd_vma) isym.n_value > addr
1500 && (bfd_vma) isym.n_value < toaddr)
1501 {
1502 isym.n_value -= count;
1503
1504 bfd_coff_swap_sym_out (abfd, (PTR) &isym, (PTR) esym);
1505
1506 if (*sym_hash != NULL)
1507 {
1508 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
1509 || (*sym_hash)->root.type == bfd_link_hash_defweak);
1510 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
1511 && (*sym_hash)->root.u.def.value < toaddr);
1512 (*sym_hash)->root.u.def.value -= count;
1513 }
1514 }
1515
1516 esym += (isym.n_numaux + 1) * symesz;
1517 sym_hash += isym.n_numaux + 1;
1518 }
1519
1520 /* See if we can move the ALIGN reloc forward. We have adjusted
1521 r_vaddr for it already. */
1522 if (irelalign != NULL)
1523 {
1524 bfd_vma alignto, alignaddr;
1525
1526 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
1527 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
1528 1 << irelalign->r_offset);
1529 if (alignto != alignaddr)
1530 {
1531 /* Tail recursion. */
1532 return sh_relax_delete_bytes (abfd, sec, alignaddr,
1533 (int) (alignto - alignaddr));
1534 }
1535 }
1536
1537 return TRUE;
1538}
1539
1540
1541/* This is yet another version of the SH opcode table, used to rapidly
1542 get information about a particular instruction. */
1543
1544/* The opcode map is represented by an array of these structures. The
1545 array is indexed by the high order four bits in the instruction. */
1546
1547struct sh_major_opcode
1548{
1549 /* A pointer to the instruction list. This is an array which
1550 contains all the instructions with this major opcode. */
1551 const struct sh_minor_opcode *minor_opcodes;
1552 /* The number of elements in minor_opcodes. */
1553 unsigned short count;
1554};
1555
1556/* This structure holds information for a set of SH opcodes. The
1557 instruction code is anded with the mask value, and the resulting
1558 value is used to search the order opcode list. */
1559
1560struct sh_minor_opcode
1561{
1562 /* The sorted opcode list. */
1563 const struct sh_opcode *opcodes;
1564 /* The number of elements in opcodes. */
1565 unsigned short count;
1566 /* The mask value to use when searching the opcode list. */
1567 unsigned short mask;
1568};
1569
1570/* This structure holds information for an SH instruction. An array
1571 of these structures is sorted in order by opcode. */
1572
1573struct sh_opcode
1574{
1575 /* The code for this instruction, after it has been anded with the
1576 mask value in the sh_major_opcode structure. */
1577 unsigned short opcode;
1578 /* Flags for this instruction. */
1579 unsigned long flags;
1580};
1581
1582/* Flag which appear in the sh_opcode structure. */
1583
1584/* This instruction loads a value from memory. */
1585#define LOAD (0x1)
1586
1587/* This instruction stores a value to memory. */
1588#define STORE (0x2)
1589
1590/* This instruction is a branch. */
1591#define BRANCH (0x4)
1592
1593/* This instruction has a delay slot. */
1594#define DELAY (0x8)
1595
1596/* This instruction uses the value in the register in the field at
1597 mask 0x0f00 of the instruction. */
1598#define USES1 (0x10)
1599#define USES1_REG(x) ((x & 0x0f00) >> 8)
1600
1601/* This instruction uses the value in the register in the field at
1602 mask 0x00f0 of the instruction. */
1603#define USES2 (0x20)
1604#define USES2_REG(x) ((x & 0x00f0) >> 4)
1605
1606/* This instruction uses the value in register 0. */
1607#define USESR0 (0x40)
1608
1609/* This instruction sets the value in the register in the field at
1610 mask 0x0f00 of the instruction. */
1611#define SETS1 (0x80)
1612#define SETS1_REG(x) ((x & 0x0f00) >> 8)
1613
1614/* This instruction sets the value in the register in the field at
1615 mask 0x00f0 of the instruction. */
1616#define SETS2 (0x100)
1617#define SETS2_REG(x) ((x & 0x00f0) >> 4)
1618
1619/* This instruction sets register 0. */
1620#define SETSR0 (0x200)
1621
1622/* This instruction sets a special register. */
1623#define SETSSP (0x400)
1624
1625/* This instruction uses a special register. */
1626#define USESSP (0x800)
1627
1628/* This instruction uses the floating point register in the field at
1629 mask 0x0f00 of the instruction. */
1630#define USESF1 (0x1000)
1631#define USESF1_REG(x) ((x & 0x0f00) >> 8)
1632
1633/* This instruction uses the floating point register in the field at
1634 mask 0x00f0 of the instruction. */
1635#define USESF2 (0x2000)
1636#define USESF2_REG(x) ((x & 0x00f0) >> 4)
1637
1638/* This instruction uses floating point register 0. */
1639#define USESF0 (0x4000)
1640
1641/* This instruction sets the floating point register in the field at
1642 mask 0x0f00 of the instruction. */
1643#define SETSF1 (0x8000)
1644#define SETSF1_REG(x) ((x & 0x0f00) >> 8)
1645
1646#define USESAS (0x10000)
1647#define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
1648#define USESR8 (0x20000)
1649#define SETSAS (0x40000)
1650#define SETSAS_REG(x) USESAS_REG (x)
1651
1652#ifndef COFF_IMAGE_WITH_PE
1653static bfd_boolean sh_insn_uses_reg
1654 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1655static bfd_boolean sh_insn_sets_reg
1656 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1657static bfd_boolean sh_insn_uses_or_sets_reg
1658 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1659static bfd_boolean sh_insn_uses_freg
1660 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1661static bfd_boolean sh_insn_sets_freg
1662 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1663static bfd_boolean sh_insn_uses_or_sets_freg
1664 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1665static bfd_boolean sh_insns_conflict
1666 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1667 const struct sh_opcode *));
1668static bfd_boolean sh_load_use
1669 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1670 const struct sh_opcode *));
1671#endif
1672/* The opcode maps. */
1673
1674#define MAP(a) a, sizeof a / sizeof a[0]
1675
1676static const struct sh_opcode sh_opcode00[] =
1677{
1678 { 0x0008, SETSSP }, /* clrt */
1679 { 0x0009, 0 }, /* nop */
1680 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */
1681 { 0x0018, SETSSP }, /* sett */
1682 { 0x0019, SETSSP }, /* div0u */
1683 { 0x001b, 0 }, /* sleep */
1684 { 0x0028, SETSSP }, /* clrmac */
1685 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */
1686 { 0x0038, USESSP | SETSSP }, /* ldtlb */
1687 { 0x0048, SETSSP }, /* clrs */
1688 { 0x0058, SETSSP } /* sets */
1689};
1690
1691static const struct sh_opcode sh_opcode01[] =
1692{
1693 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */
1694 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */
1695 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */
1696 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */
1697 { 0x0029, SETS1 | USESSP }, /* movt rn */
1698 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */
1699 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */
1700 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn / sts dsr,rn */
1701 { 0x0083, LOAD | USES1 }, /* pref @rn */
1702 { 0x007a, SETS1 | USESSP }, /* sts a0,rn */
1703 { 0x008a, SETS1 | USESSP }, /* sts x0,rn */
1704 { 0x009a, SETS1 | USESSP }, /* sts x1,rn */
1705 { 0x00aa, SETS1 | USESSP }, /* sts y0,rn */
1706 { 0x00ba, SETS1 | USESSP } /* sts y1,rn */
1707};
1708
1709/* These sixteen instructions can be handled with one table entry below. */
1710#if 0
1711 { 0x0002, SETS1 | USESSP }, /* stc sr,rn */
1712 { 0x0012, SETS1 | USESSP }, /* stc gbr,rn */
1713 { 0x0022, SETS1 | USESSP }, /* stc vbr,rn */
1714 { 0x0032, SETS1 | USESSP }, /* stc ssr,rn */
1715 { 0x0042, SETS1 | USESSP }, /* stc spc,rn */
1716 { 0x0052, SETS1 | USESSP }, /* stc mod,rn */
1717 { 0x0062, SETS1 | USESSP }, /* stc rs,rn */
1718 { 0x0072, SETS1 | USESSP }, /* stc re,rn */
1719 { 0x0082, SETS1 | USESSP }, /* stc r0_bank,rn */
1720 { 0x0092, SETS1 | USESSP }, /* stc r1_bank,rn */
1721 { 0x00a2, SETS1 | USESSP }, /* stc r2_bank,rn */
1722 { 0x00b2, SETS1 | USESSP }, /* stc r3_bank,rn */
1723 { 0x00c2, SETS1 | USESSP }, /* stc r4_bank,rn */
1724 { 0x00d2, SETS1 | USESSP }, /* stc r5_bank,rn */
1725 { 0x00e2, SETS1 | USESSP }, /* stc r6_bank,rn */
1726 { 0x00f2, SETS1 | USESSP } /* stc r7_bank,rn */
1727#endif
1728
1729static const struct sh_opcode sh_opcode02[] =
1730{
1731 { 0x0002, SETS1 | USESSP }, /* stc <special_reg>,rn */
1732 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1733 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1734 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1735 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */
1736 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */
1737 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */
1738 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */
1739 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
1740};
1741
1742static const struct sh_minor_opcode sh_opcode0[] =
1743{
1744 { MAP (sh_opcode00), 0xffff },
1745 { MAP (sh_opcode01), 0xf0ff },
1746 { MAP (sh_opcode02), 0xf00f }
1747};
1748
1749static const struct sh_opcode sh_opcode10[] =
1750{
1751 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1752};
1753
1754static const struct sh_minor_opcode sh_opcode1[] =
1755{
1756 { MAP (sh_opcode10), 0xf000 }
1757};
1758
1759static const struct sh_opcode sh_opcode20[] =
1760{
1761 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1762 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1763 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1764 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1765 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1766 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1767 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */
1768 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */
1769 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */
1770 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */
1771 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */
1772 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */
1773 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */
1774 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */
1775 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */
1776};
1777
1778static const struct sh_minor_opcode sh_opcode2[] =
1779{
1780 { MAP (sh_opcode20), 0xf00f }
1781};
1782
1783static const struct sh_opcode sh_opcode30[] =
1784{
1785 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */
1786 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */
1787 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */
1788 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */
1789 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */
1790 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */
1791 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */
1792 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */
1793 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
1794 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */
1795 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */
1796 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */
1797 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
1798 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */
1799};
1800
1801static const struct sh_minor_opcode sh_opcode3[] =
1802{
1803 { MAP (sh_opcode30), 0xf00f }
1804};
1805
1806static const struct sh_opcode sh_opcode40[] =
1807{
1808 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */
1809 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */
1810 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
1811 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */
1812 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */
1813 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */
1814 { 0x4008, SETS1 | USES1 }, /* shll2 rn */
1815 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */
1816 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */
1817 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */
1818 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */
1819 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */
1820 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
1821 { 0x4014, SETSSP | USES1 }, /* setrc rm */
1822 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */
1823 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */
1824 { 0x4018, SETS1 | USES1 }, /* shll8 rn */
1825 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */
1826 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */
1827 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */
1828 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */
1829 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */
1830 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
1831 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */
1832 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */
1833 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */
1834 { 0x4028, SETS1 | USES1 }, /* shll16 rn */
1835 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */
1836 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */
1837 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */
1838 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1839 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */
1840 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */
1841 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */
1842 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr / dsr */
1843 { 0x406a, SETSSP | USES1 }, /* lds rm,fpscr / lds rm,dsr */
1844 { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */
1845 { 0x4076, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,a0 */
1846 { 0x407a, SETSSP | USES1 }, /* lds.l rm,a0 */
1847 { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */
1848 { 0x4086, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x0 */
1849 { 0x408a, SETSSP | USES1 }, /* lds.l rm,x0 */
1850 { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */
1851 { 0x4096, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x1 */
1852 { 0x409a, SETSSP | USES1 }, /* lds.l rm,x1 */
1853 { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */
1854 { 0x40a6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y0 */
1855 { 0x40aa, SETSSP | USES1 }, /* lds.l rm,y0 */
1856 { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */
1857 { 0x40b6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y1 */
1858 { 0x40ba, SETSSP | USES1 } /* lds.l rm,y1 */
1859#if 0 /* These groups sixteen insns can be
1860 handled with one table entry each below. */
1861 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l sr,@-rn */
1862 { 0x4013, STORE | SETS1 | USES1 | USESSP }, /* stc.l gbr,@-rn */
1863 { 0x4023, STORE | SETS1 | USES1 | USESSP }, /* stc.l vbr,@-rn */
1864 { 0x4033, STORE | SETS1 | USES1 | USESSP }, /* stc.l ssr,@-rn */
1865 { 0x4043, STORE | SETS1 | USES1 | USESSP }, /* stc.l spc,@-rn */
1866 { 0x4053, STORE | SETS1 | USES1 | USESSP }, /* stc.l mod,@-rn */
1867 { 0x4063, STORE | SETS1 | USES1 | USESSP }, /* stc.l rs,@-rn */
1868 { 0x4073, STORE | SETS1 | USES1 | USESSP }, /* stc.l re,@-rn */
1869 { 0x4083, STORE | SETS1 | USES1 | USESSP }, /* stc.l r0_bank,@-rn */
1870 ..
1871 { 0x40f3, STORE | SETS1 | USES1 | USESSP }, /* stc.l r7_bank,@-rn */
1872
1873 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,sr */
1874 { 0x4017, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,gbr */
1875 { 0x4027, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,vbr */
1876 { 0x4037, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,ssr */
1877 { 0x4047, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,spc */
1878 { 0x4057, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,mod */
1879 { 0x4067, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,rs */
1880 { 0x4077, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,re */
1881 { 0x4087, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,r0_bank */
1882 ..
1883 { 0x40f7, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,r7_bank */
1884
1885 { 0x400e, SETSSP | USES1 }, /* ldc rm,sr */
1886 { 0x401e, SETSSP | USES1 }, /* ldc rm,gbr */
1887 { 0x402e, SETSSP | USES1 }, /* ldc rm,vbr */
1888 { 0x403e, SETSSP | USES1 }, /* ldc rm,ssr */
1889 { 0x404e, SETSSP | USES1 }, /* ldc rm,spc */
1890 { 0x405e, SETSSP | USES1 }, /* ldc rm,mod */
1891 { 0x406e, SETSSP | USES1 }, /* ldc rm,rs */
1892 { 0x407e, SETSSP | USES1 } /* ldc rm,re */
1893 { 0x408e, SETSSP | USES1 } /* ldc rm,r0_bank */
1894 ..
1895 { 0x40fe, SETSSP | USES1 } /* ldc rm,r7_bank */
1896#endif
1897};
1898
1899static const struct sh_opcode sh_opcode41[] =
1900{
1901 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */
1902 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,<special_reg> */
1903 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */
1904 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */
1905 { 0x400e, SETSSP | USES1 }, /* ldc rm,<special_reg> */
1906 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
1907};
1908
1909static const struct sh_minor_opcode sh_opcode4[] =
1910{
1911 { MAP (sh_opcode40), 0xf0ff },
1912 { MAP (sh_opcode41), 0xf00f }
1913};
1914
1915static const struct sh_opcode sh_opcode50[] =
1916{
1917 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
1918};
1919
1920static const struct sh_minor_opcode sh_opcode5[] =
1921{
1922 { MAP (sh_opcode50), 0xf000 }
1923};
1924
1925static const struct sh_opcode sh_opcode60[] =
1926{
1927 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */
1928 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */
1929 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */
1930 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */
1931 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */
1932 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */
1933 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */
1934 { 0x6007, SETS1 | USES2 }, /* not rm,rn */
1935 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */
1936 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */
1937 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */
1938 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */
1939 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */
1940 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */
1941 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */
1942 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */
1943};
1944
1945static const struct sh_minor_opcode sh_opcode6[] =
1946{
1947 { MAP (sh_opcode60), 0xf00f }
1948};
1949
1950static const struct sh_opcode sh_opcode70[] =
1951{
1952 { 0x7000, SETS1 | USES1 } /* add #imm,rn */
1953};
1954
1955static const struct sh_minor_opcode sh_opcode7[] =
1956{
1957 { MAP (sh_opcode70), 0xf000 }
1958};
1959
1960static const struct sh_opcode sh_opcode80[] =
1961{
1962 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1963 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
1964 { 0x8200, SETSSP }, /* setrc #imm */
1965 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */
1966 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */
1967 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */
1968 { 0x8900, BRANCH | USESSP }, /* bt label */
1969 { 0x8b00, BRANCH | USESSP }, /* bf label */
1970 { 0x8c00, SETSSP }, /* ldrs @(disp,pc) */
1971 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */
1972 { 0x8e00, SETSSP }, /* ldre @(disp,pc) */
1973 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */
1974};
1975
1976static const struct sh_minor_opcode sh_opcode8[] =
1977{
1978 { MAP (sh_opcode80), 0xff00 }
1979};
1980
1981static const struct sh_opcode sh_opcode90[] =
1982{
1983 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */
1984};
1985
1986static const struct sh_minor_opcode sh_opcode9[] =
1987{
1988 { MAP (sh_opcode90), 0xf000 }
1989};
1990
1991static const struct sh_opcode sh_opcodea0[] =
1992{
1993 { 0xa000, BRANCH | DELAY } /* bra label */
1994};
1995
1996static const struct sh_minor_opcode sh_opcodea[] =
1997{
1998 { MAP (sh_opcodea0), 0xf000 }
1999};
2000
2001static const struct sh_opcode sh_opcodeb0[] =
2002{
2003 { 0xb000, BRANCH | DELAY } /* bsr label */
2004};
2005
2006static const struct sh_minor_opcode sh_opcodeb[] =
2007{
2008 { MAP (sh_opcodeb0), 0xf000 }
2009};
2010
2011static const struct sh_opcode sh_opcodec0[] =
2012{
2013 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
2014 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
2015 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
2016 { 0xc300, BRANCH | USESSP }, /* trapa #imm */
2017 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */
2018 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */
2019 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */
2020 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */
2021 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */
2022 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */
2023 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */
2024 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */
2025 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */
2026 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
2027 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
2028 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
2029};
2030
2031static const struct sh_minor_opcode sh_opcodec[] =
2032{
2033 { MAP (sh_opcodec0), 0xff00 }
2034};
2035
2036static const struct sh_opcode sh_opcoded0[] =
2037{
2038 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */
2039};
2040
2041static const struct sh_minor_opcode sh_opcoded[] =
2042{
2043 { MAP (sh_opcoded0), 0xf000 }
2044};
2045
2046static const struct sh_opcode sh_opcodee0[] =
2047{
2048 { 0xe000, SETS1 } /* mov #imm,rn */
2049};
2050
2051static const struct sh_minor_opcode sh_opcodee[] =
2052{
2053 { MAP (sh_opcodee0), 0xf000 }
2054};
2055
2056static const struct sh_opcode sh_opcodef0[] =
2057{
2058 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */
2059 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */
2060 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */
2061 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */
2062 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */
2063 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */
2064 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */
2065 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
2066 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */
2067 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */
2068 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
2069 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
2070 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */
2071 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */
2072};
2073
2074static const struct sh_opcode sh_opcodef1[] =
2075{
2076 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */
2077 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */
2078 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */
2079 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */
2080 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */
2081 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */
2082 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */
2083 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */
2084 { 0xf08d, SETSF1 }, /* fldi0 fn */
2085 { 0xf09d, SETSF1 } /* fldi1 fn */
2086};
2087
2088static const struct sh_minor_opcode sh_opcodef[] =
2089{
2090 { MAP (sh_opcodef0), 0xf00f },
2091 { MAP (sh_opcodef1), 0xf0ff }
2092};
2093
2094#ifndef COFF_IMAGE_WITH_PE
2095static struct sh_major_opcode sh_opcodes[] =
2096{
2097 { MAP (sh_opcode0) },
2098 { MAP (sh_opcode1) },
2099 { MAP (sh_opcode2) },
2100 { MAP (sh_opcode3) },
2101 { MAP (sh_opcode4) },
2102 { MAP (sh_opcode5) },
2103 { MAP (sh_opcode6) },
2104 { MAP (sh_opcode7) },
2105 { MAP (sh_opcode8) },
2106 { MAP (sh_opcode9) },
2107 { MAP (sh_opcodea) },
2108 { MAP (sh_opcodeb) },
2109 { MAP (sh_opcodec) },
2110 { MAP (sh_opcoded) },
2111 { MAP (sh_opcodee) },
2112 { MAP (sh_opcodef) }
2113};
2114#endif
2115
2116/* The double data transfer / parallel processing insns are not
2117 described here. This will cause sh_align_load_span to leave them alone. */
2118
2119static const struct sh_opcode sh_dsp_opcodef0[] =
2120{
2121 { 0xf400, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @-as,ds */
2122 { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */
2123 { 0xf404, USESAS | LOAD | SETSSP }, /* movs.x @as,ds */
2124 { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */
2125 { 0xf408, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @as+,ds */
2126 { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */
2127 { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */
2128 { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */
2129};
2130
2131static const struct sh_minor_opcode sh_dsp_opcodef[] =
2132{
2133 { MAP (sh_dsp_opcodef0), 0xfc0d }
2134};
2135
2136#ifndef COFF_IMAGE_WITH_PE
2137/* Given an instruction, return a pointer to the corresponding
2138 sh_opcode structure. Return NULL if the instruction is not
2139 recognized. */
2140
2141static const struct sh_opcode *
2142sh_insn_info (insn)
2143 unsigned int insn;
2144{
2145 const struct sh_major_opcode *maj;
2146 const struct sh_minor_opcode *min, *minend;
2147
2148 maj = &sh_opcodes[(insn & 0xf000) >> 12];
2149 min = maj->minor_opcodes;
2150 minend = min + maj->count;
2151 for (; min < minend; min++)
2152 {
2153 unsigned int l;
2154 const struct sh_opcode *op, *opend;
2155
2156 l = insn & min->mask;
2157 op = min->opcodes;
2158 opend = op + min->count;
2159
2160 /* Since the opcodes tables are sorted, we could use a binary
2161 search here if the count were above some cutoff value. */
2162 for (; op < opend; op++)
2163 if (op->opcode == l)
2164 return op;
2165 }
2166
2167 return NULL;
2168}
2169
2170/* See whether an instruction uses or sets a general purpose register */
2171
2172static bfd_boolean
2173sh_insn_uses_or_sets_reg (insn, op, reg)
2174 unsigned int insn;
2175 const struct sh_opcode *op;
2176 unsigned int reg;
2177{
2178 if (sh_insn_uses_reg (insn, op, reg))
2179 return TRUE;
2180
2181 return sh_insn_sets_reg (insn, op, reg);
2182}
2183
2184/* See whether an instruction uses a general purpose register. */
2185
2186static bfd_boolean
2187sh_insn_uses_reg (insn, op, reg)
2188 unsigned int insn;
2189 const struct sh_opcode *op;
2190 unsigned int reg;
2191{
2192 unsigned int f;
2193
2194 f = op->flags;
2195
2196 if ((f & USES1) != 0
2197 && USES1_REG (insn) == reg)
2198 return TRUE;
2199 if ((f & USES2) != 0
2200 && USES2_REG (insn) == reg)
2201 return TRUE;
2202 if ((f & USESR0) != 0
2203 && reg == 0)
2204 return TRUE;
2205 if ((f & USESAS) && reg == USESAS_REG (insn))
2206 return TRUE;
2207 if ((f & USESR8) && reg == 8)
2208 return TRUE;
2209
2210 return FALSE;
2211}
2212
2213/* See whether an instruction sets a general purpose register. */
2214
2215static bfd_boolean
2216sh_insn_sets_reg (insn, op, reg)
2217 unsigned int insn;
2218 const struct sh_opcode *op;
2219 unsigned int reg;
2220{
2221 unsigned int f;
2222
2223 f = op->flags;
2224
2225 if ((f & SETS1) != 0
2226 && SETS1_REG (insn) == reg)
2227 return TRUE;
2228 if ((f & SETS2) != 0
2229 && SETS2_REG (insn) == reg)
2230 return TRUE;
2231 if ((f & SETSR0) != 0
2232 && reg == 0)
2233 return TRUE;
2234 if ((f & SETSAS) && reg == SETSAS_REG (insn))
2235 return TRUE;
2236
2237 return FALSE;
2238}
2239
2240/* See whether an instruction uses or sets a floating point register */
2241
2242static bfd_boolean
2243sh_insn_uses_or_sets_freg (insn, op, reg)
2244 unsigned int insn;
2245 const struct sh_opcode *op;
2246 unsigned int reg;
2247{
2248 if (sh_insn_uses_freg (insn, op, reg))
2249 return TRUE;
2250
2251 return sh_insn_sets_freg (insn, op, reg);
2252}
2253
2254/* See whether an instruction uses a floating point register. */
2255
2256static bfd_boolean
2257sh_insn_uses_freg (insn, op, freg)
2258 unsigned int insn;
2259 const struct sh_opcode *op;
2260 unsigned int freg;
2261{
2262 unsigned int f;
2263
2264 f = op->flags;
2265
2266 /* We can't tell if this is a double-precision insn, so just play safe
2267 and assume that it might be. So not only have we test FREG against
2268 itself, but also even FREG against FREG+1 - if the using insn uses
2269 just the low part of a double precision value - but also an odd
2270 FREG against FREG-1 - if the setting insn sets just the low part
2271 of a double precision value.
2272 So what this all boils down to is that we have to ignore the lowest
2273 bit of the register number. */
2274
2275 if ((f & USESF1) != 0
2276 && (USESF1_REG (insn) & 0xe) == (freg & 0xe))
2277 return TRUE;
2278 if ((f & USESF2) != 0
2279 && (USESF2_REG (insn) & 0xe) == (freg & 0xe))
2280 return TRUE;
2281 if ((f & USESF0) != 0
2282 && freg == 0)
2283 return TRUE;
2284
2285 return FALSE;
2286}
2287
2288/* See whether an instruction sets a floating point register. */
2289
2290static bfd_boolean
2291sh_insn_sets_freg (insn, op, freg)
2292 unsigned int insn;
2293 const struct sh_opcode *op;
2294 unsigned int freg;
2295{
2296 unsigned int f;
2297
2298 f = op->flags;
2299
2300 /* We can't tell if this is a double-precision insn, so just play safe
2301 and assume that it might be. So not only have we test FREG against
2302 itself, but also even FREG against FREG+1 - if the using insn uses
2303 just the low part of a double precision value - but also an odd
2304 FREG against FREG-1 - if the setting insn sets just the low part
2305 of a double precision value.
2306 So what this all boils down to is that we have to ignore the lowest
2307 bit of the register number. */
2308
2309 if ((f & SETSF1) != 0
2310 && (SETSF1_REG (insn) & 0xe) == (freg & 0xe))
2311 return TRUE;
2312
2313 return FALSE;
2314}
2315
2316/* See whether instructions I1 and I2 conflict, assuming I1 comes
2317 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
2318 This should return TRUE if there is a conflict, or FALSE if the
2319 instructions can be swapped safely. */
2320
2321static bfd_boolean
2322sh_insns_conflict (i1, op1, i2, op2)
2323 unsigned int i1;
2324 const struct sh_opcode *op1;
2325 unsigned int i2;
2326 const struct sh_opcode *op2;
2327{
2328 unsigned int f1, f2;
2329
2330 f1 = op1->flags;
2331 f2 = op2->flags;
2332
2333 /* Load of fpscr conflicts with floating point operations.
2334 FIXME: shouldn't test raw opcodes here. */
2335 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000)
2336 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000))
2337 return TRUE;
2338
2339 if ((f1 & (BRANCH | DELAY)) != 0
2340 || (f2 & (BRANCH | DELAY)) != 0)
2341 return TRUE;
2342
2343 if (((f1 | f2) & SETSSP)
2344 && (f1 & (SETSSP | USESSP))
2345 && (f2 & (SETSSP | USESSP)))
2346 return TRUE;
2347
2348 if ((f1 & SETS1) != 0
2349 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1)))
2350 return TRUE;
2351 if ((f1 & SETS2) != 0
2352 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1)))
2353 return TRUE;
2354 if ((f1 & SETSR0) != 0
2355 && sh_insn_uses_or_sets_reg (i2, op2, 0))
2356 return TRUE;
2357 if ((f1 & SETSAS)
2358 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1)))
2359 return TRUE;
2360 if ((f1 & SETSF1) != 0
2361 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1)))
2362 return TRUE;
2363
2364 if ((f2 & SETS1) != 0
2365 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2)))
2366 return TRUE;
2367 if ((f2 & SETS2) != 0
2368 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2)))
2369 return TRUE;
2370 if ((f2 & SETSR0) != 0
2371 && sh_insn_uses_or_sets_reg (i1, op1, 0))
2372 return TRUE;
2373 if ((f2 & SETSAS)
2374 && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2)))
2375 return TRUE;
2376 if ((f2 & SETSF1) != 0
2377 && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2)))
2378 return TRUE;
2379
2380 /* The instructions do not conflict. */
2381 return FALSE;
2382}
2383
2384/* I1 is a load instruction, and I2 is some other instruction. Return
2385 TRUE if I1 loads a register which I2 uses. */
2386
2387static bfd_boolean
2388sh_load_use (i1, op1, i2, op2)
2389 unsigned int i1;
2390 const struct sh_opcode *op1;
2391 unsigned int i2;
2392 const struct sh_opcode *op2;
2393{
2394 unsigned int f1;
2395
2396 f1 = op1->flags;
2397
2398 if ((f1 & LOAD) == 0)
2399 return FALSE;
2400
2401 /* If both SETS1 and SETSSP are set, that means a load to a special
2402 register using postincrement addressing mode, which we don't care
2403 about here. */
2404 if ((f1 & SETS1) != 0
2405 && (f1 & SETSSP) == 0
2406 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
2407 return TRUE;
2408
2409 if ((f1 & SETSR0) != 0
2410 && sh_insn_uses_reg (i2, op2, 0))
2411 return TRUE;
2412
2413 if ((f1 & SETSF1) != 0
2414 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
2415 return TRUE;
2416
2417 return FALSE;
2418}
2419
2420/* Try to align loads and stores within a span of memory. This is
2421 called by both the ELF and the COFF sh targets. ABFD and SEC are
2422 the BFD and section we are examining. CONTENTS is the contents of
2423 the section. SWAP is the routine to call to swap two instructions.
2424 RELOCS is a pointer to the internal relocation information, to be
2425 passed to SWAP. PLABEL is a pointer to the current label in a
2426 sorted list of labels; LABEL_END is the end of the list. START and
2427 STOP are the range of memory to examine. If a swap is made,
2428 *PSWAPPED is set to TRUE. */
2429
2430#ifdef COFF_WITH_PE
2431static
2432#endif
2433bfd_boolean
2434_bfd_sh_align_load_span (abfd, sec, contents, swap, relocs,
2435 plabel, label_end, start, stop, pswapped)
2436 bfd *abfd;
2437 asection *sec;
2438 bfd_byte *contents;
2439 bfd_boolean (*swap) PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
2440 PTR relocs;
2441 bfd_vma **plabel;
2442 bfd_vma *label_end;
2443 bfd_vma start;
2444 bfd_vma stop;
2445 bfd_boolean *pswapped;
2446{
2447 int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp
2448 || abfd->arch_info->mach == bfd_mach_sh3_dsp);
2449 bfd_vma i;
2450
2451 /* The SH4 has a Harvard architecture, hence aligning loads is not
2452 desirable. In fact, it is counter-productive, since it interferes
2453 with the schedules generated by the compiler. */
2454 if (abfd->arch_info->mach == bfd_mach_sh4)
2455 return TRUE;
2456
2457 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
2458 instructions. */
2459 if (dsp)
2460 {
2461 sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef;
2462 sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef;
2463 }
2464
2465 /* Instructions should be aligned on 2 byte boundaries. */
2466 if ((start & 1) == 1)
2467 ++start;
2468
2469 /* Now look through the unaligned addresses. */
2470 i = start;
2471 if ((i & 2) == 0)
2472 i += 2;
2473 for (; i < stop; i += 4)
2474 {
2475 unsigned int insn;
2476 const struct sh_opcode *op;
2477 unsigned int prev_insn = 0;
2478 const struct sh_opcode *prev_op = NULL;
2479
2480 insn = bfd_get_16 (abfd, contents + i);
2481 op = sh_insn_info (insn);
2482 if (op == NULL
2483 || (op->flags & (LOAD | STORE)) == 0)
2484 continue;
2485
2486 /* This is a load or store which is not on a four byte boundary. */
2487
2488 while (*plabel < label_end && **plabel < i)
2489 ++*plabel;
2490
2491 if (i > start)
2492 {
2493 prev_insn = bfd_get_16 (abfd, contents + i - 2);
2494 /* If INSN is the field b of a parallel processing insn, it is not
2495 a load / store after all. Note that the test here might mistake
2496 the field_b of a pcopy insn for the starting code of a parallel
2497 processing insn; this might miss a swapping opportunity, but at
2498 least we're on the safe side. */
2499 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2500 continue;
2501
2502 /* Check if prev_insn is actually the field b of a parallel
2503 processing insn. Again, this can give a spurious match
2504 after a pcopy. */
2505 if (dsp && i - 2 > start)
2506 {
2507 unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4);
2508
2509 if ((pprev_insn & 0xfc00) == 0xf800)
2510 prev_op = NULL;
2511 else
2512 prev_op = sh_insn_info (prev_insn);
2513 }
2514 else
2515 prev_op = sh_insn_info (prev_insn);
2516
2517 /* If the load/store instruction is in a delay slot, we
2518 can't swap. */
2519 if (prev_op == NULL
2520 || (prev_op->flags & DELAY) != 0)
2521 continue;
2522 }
2523 if (i > start
2524 && (*plabel >= label_end || **plabel != i)
2525 && prev_op != NULL
2526 && (prev_op->flags & (LOAD | STORE)) == 0
2527 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2528 {
2529 bfd_boolean ok;
2530
2531 /* The load/store instruction does not have a label, and
2532 there is a previous instruction; PREV_INSN is not
2533 itself a load/store instruction, and PREV_INSN and
2534 INSN do not conflict. */
2535
2536 ok = TRUE;
2537
2538 if (i >= start + 4)
2539 {
2540 unsigned int prev2_insn;
2541 const struct sh_opcode *prev2_op;
2542
2543 prev2_insn = bfd_get_16 (abfd, contents + i - 4);
2544 prev2_op = sh_insn_info (prev2_insn);
2545
2546 /* If the instruction before PREV_INSN has a delay
2547 slot--that is, PREV_INSN is in a delay slot--we
2548 can not swap. */
2549 if (prev2_op == NULL
2550 || (prev2_op->flags & DELAY) != 0)
2551 ok = FALSE;
2552
2553 /* If the instruction before PREV_INSN is a load,
2554 and it sets a register which INSN uses, then
2555 putting INSN immediately after PREV_INSN will
2556 cause a pipeline bubble, so there is no point to
2557 making the swap. */
2558 if (ok
2559 && (prev2_op->flags & LOAD) != 0
2560 && sh_load_use (prev2_insn, prev2_op, insn, op))
2561 ok = FALSE;
2562 }
2563
2564 if (ok)
2565 {
2566 if (! (*swap) (abfd, sec, relocs, contents, i - 2))
2567 return FALSE;
2568 *pswapped = TRUE;
2569 continue;
2570 }
2571 }
2572
2573 while (*plabel < label_end && **plabel < i + 2)
2574 ++*plabel;
2575
2576 if (i + 2 < stop
2577 && (*plabel >= label_end || **plabel != i + 2))
2578 {
2579 unsigned int next_insn;
2580 const struct sh_opcode *next_op;
2581
2582 /* There is an instruction after the load/store
2583 instruction, and it does not have a label. */
2584 next_insn = bfd_get_16 (abfd, contents + i + 2);
2585 next_op = sh_insn_info (next_insn);
2586 if (next_op != NULL
2587 && (next_op->flags & (LOAD | STORE)) == 0
2588 && ! sh_insns_conflict (insn, op, next_insn, next_op))
2589 {
2590 bfd_boolean ok;
2591
2592 /* NEXT_INSN is not itself a load/store instruction,
2593 and it does not conflict with INSN. */
2594
2595 ok = TRUE;
2596
2597 /* If PREV_INSN is a load, and it sets a register
2598 which NEXT_INSN uses, then putting NEXT_INSN
2599 immediately after PREV_INSN will cause a pipeline
2600 bubble, so there is no reason to make this swap. */
2601 if (prev_op != NULL
2602 && (prev_op->flags & LOAD) != 0
2603 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
2604 ok = FALSE;
2605
2606 /* If INSN is a load, and it sets a register which
2607 the insn after NEXT_INSN uses, then doing the
2608 swap will cause a pipeline bubble, so there is no
2609 reason to make the swap. However, if the insn
2610 after NEXT_INSN is itself a load or store
2611 instruction, then it is misaligned, so
2612 optimistically hope that it will be swapped
2613 itself, and just live with the pipeline bubble if
2614 it isn't. */
2615 if (ok
2616 && i + 4 < stop
2617 && (op->flags & LOAD) != 0)
2618 {
2619 unsigned int next2_insn;
2620 const struct sh_opcode *next2_op;
2621
2622 next2_insn = bfd_get_16 (abfd, contents + i + 4);
2623 next2_op = sh_insn_info (next2_insn);
2624 if ((next2_op->flags & (LOAD | STORE)) == 0
2625 && sh_load_use (insn, op, next2_insn, next2_op))
2626 ok = FALSE;
2627 }
2628
2629 if (ok)
2630 {
2631 if (! (*swap) (abfd, sec, relocs, contents, i))
2632 return FALSE;
2633 *pswapped = TRUE;
2634 continue;
2635 }
2636 }
2637 }
2638 }
2639
2640 return TRUE;
2641}
2642#endif /* not COFF_IMAGE_WITH_PE */
2643
2644/* Look for loads and stores which we can align to four byte
2645 boundaries. See the longer comment above sh_relax_section for why
2646 this is desirable. This sets *PSWAPPED if some instruction was
2647 swapped. */
2648
2649static bfd_boolean
2650sh_align_loads (abfd, sec, internal_relocs, contents, pswapped)
2651 bfd *abfd;
2652 asection *sec;
2653 struct internal_reloc *internal_relocs;
2654 bfd_byte *contents;
2655 bfd_boolean *pswapped;
2656{
2657 struct internal_reloc *irel, *irelend;
2658 bfd_vma *labels = NULL;
2659 bfd_vma *label, *label_end;
2660 bfd_size_type amt;
2661
2662 *pswapped = FALSE;
2663
2664 irelend = internal_relocs + sec->reloc_count;
2665
2666 /* Get all the addresses with labels on them. */
2667 amt = (bfd_size_type) sec->reloc_count * sizeof (bfd_vma);
2668 labels = (bfd_vma *) bfd_malloc (amt);
2669 if (labels == NULL)
2670 goto error_return;
2671 label_end = labels;
2672 for (irel = internal_relocs; irel < irelend; irel++)
2673 {
2674 if (irel->r_type == R_SH_LABEL)
2675 {
2676 *label_end = irel->r_vaddr - sec->vma;
2677 ++label_end;
2678 }
2679 }
2680
2681 /* Note that the assembler currently always outputs relocs in
2682 address order. If that ever changes, this code will need to sort
2683 the label values and the relocs. */
2684
2685 label = labels;
2686
2687 for (irel = internal_relocs; irel < irelend; irel++)
2688 {
2689 bfd_vma start, stop;
2690
2691 if (irel->r_type != R_SH_CODE)
2692 continue;
2693
2694 start = irel->r_vaddr - sec->vma;
2695
2696 for (irel++; irel < irelend; irel++)
2697 if (irel->r_type == R_SH_DATA)
2698 break;
2699 if (irel < irelend)
2700 stop = irel->r_vaddr - sec->vma;
2701 else
2702 stop = sec->_cooked_size;
2703
2704 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
2705 (PTR) internal_relocs, &label,
2706 label_end, start, stop, pswapped))
2707 goto error_return;
2708 }
2709
2710 free (labels);
2711
2712 return TRUE;
2713
2714 error_return:
2715 if (labels != NULL)
2716 free (labels);
2717 return FALSE;
2718}
2719
2720/* Swap two SH instructions. */
2721
2722static bfd_boolean
2723sh_swap_insns (abfd, sec, relocs, contents, addr)
2724 bfd *abfd;
2725 asection *sec;
2726 PTR relocs;
2727 bfd_byte *contents;
2728 bfd_vma addr;
2729{
2730 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
2731 unsigned short i1, i2;
2732 struct internal_reloc *irel, *irelend;
2733
2734 /* Swap the instructions themselves. */
2735 i1 = bfd_get_16 (abfd, contents + addr);
2736 i2 = bfd_get_16 (abfd, contents + addr + 2);
2737 bfd_put_16 (abfd, (bfd_vma) i2, contents + addr);
2738 bfd_put_16 (abfd, (bfd_vma) i1, contents + addr + 2);
2739
2740 /* Adjust all reloc addresses. */
2741 irelend = internal_relocs + sec->reloc_count;
2742 for (irel = internal_relocs; irel < irelend; irel++)
2743 {
2744 int type, add;
2745
2746 /* There are a few special types of relocs that we don't want to
2747 adjust. These relocs do not apply to the instruction itself,
2748 but are only associated with the address. */
2749 type = irel->r_type;
2750 if (type == R_SH_ALIGN
2751 || type == R_SH_CODE
2752 || type == R_SH_DATA
2753 || type == R_SH_LABEL)
2754 continue;
2755
2756 /* If an R_SH_USES reloc points to one of the addresses being
2757 swapped, we must adjust it. It would be incorrect to do this
2758 for a jump, though, since we want to execute both
2759 instructions after the jump. (We have avoided swapping
2760 around a label, so the jump will not wind up executing an
2761 instruction it shouldn't). */
2762 if (type == R_SH_USES)
2763 {
2764 bfd_vma off;
2765
2766 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
2767 if (off == addr)
2768 irel->r_offset += 2;
2769 else if (off == addr + 2)
2770 irel->r_offset -= 2;
2771 }
2772
2773 if (irel->r_vaddr - sec->vma == addr)
2774 {
2775 irel->r_vaddr += 2;
2776 add = -2;
2777 }
2778 else if (irel->r_vaddr - sec->vma == addr + 2)
2779 {
2780 irel->r_vaddr -= 2;
2781 add = 2;
2782 }
2783 else
2784 add = 0;
2785
2786 if (add != 0)
2787 {
2788 bfd_byte *loc;
2789 unsigned short insn, oinsn;
2790 bfd_boolean overflow;
2791
2792 loc = contents + irel->r_vaddr - sec->vma;
2793 overflow = FALSE;
2794 switch (type)
2795 {
2796 default:
2797 break;
2798
2799 case R_SH_PCDISP8BY2:
2800 case R_SH_PCRELIMM8BY2:
2801 insn = bfd_get_16 (abfd, loc);
2802 oinsn = insn;
2803 insn += add / 2;
2804 if ((oinsn & 0xff00) != (insn & 0xff00))
2805 overflow = TRUE;
2806 bfd_put_16 (abfd, (bfd_vma) insn, loc);
2807 break;
2808
2809 case R_SH_PCDISP:
2810 insn = bfd_get_16 (abfd, loc);
2811 oinsn = insn;
2812 insn += add / 2;
2813 if ((oinsn & 0xf000) != (insn & 0xf000))
2814 overflow = TRUE;
2815 bfd_put_16 (abfd, (bfd_vma) insn, loc);
2816 break;
2817
2818 case R_SH_PCRELIMM8BY4:
2819 /* This reloc ignores the least significant 3 bits of
2820 the program counter before adding in the offset.
2821 This means that if ADDR is at an even address, the
2822 swap will not affect the offset. If ADDR is an at an
2823 odd address, then the instruction will be crossing a
2824 four byte boundary, and must be adjusted. */
2825 if ((addr & 3) != 0)
2826 {
2827 insn = bfd_get_16 (abfd, loc);
2828 oinsn = insn;
2829 insn += add / 2;
2830 if ((oinsn & 0xff00) != (insn & 0xff00))
2831 overflow = TRUE;
2832 bfd_put_16 (abfd, (bfd_vma) insn, loc);
2833 }
2834
2835 break;
2836 }
2837
2838 if (overflow)
2839 {
2840 ((*_bfd_error_handler)
2841 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
2842 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr));
2843 bfd_set_error (bfd_error_bad_value);
2844 return FALSE;
2845 }
2846 }
2847 }
2848
2849 return TRUE;
2850}
2851
2852
2853/* This is a modification of _bfd_coff_generic_relocate_section, which
2854 will handle SH relaxing. */
2855
2856static bfd_boolean
2857sh_relocate_section (output_bfd, info, input_bfd, input_section, contents,
2858 relocs, syms, sections)
2859 bfd *output_bfd ATTRIBUTE_UNUSED;
2860 struct bfd_link_info *info;
2861 bfd *input_bfd;
2862 asection *input_section;
2863 bfd_byte *contents;
2864 struct internal_reloc *relocs;
2865 struct internal_syment *syms;
2866 asection **sections;
2867{
2868 struct internal_reloc *rel;
2869 struct internal_reloc *relend;
2870
2871 rel = relocs;
2872 relend = rel + input_section->reloc_count;
2873 for (; rel < relend; rel++)
2874 {
2875 long symndx;
2876 struct coff_link_hash_entry *h;
2877 struct internal_syment *sym;
2878 bfd_vma addend;
2879 bfd_vma val;
2880 reloc_howto_type *howto;
2881 bfd_reloc_status_type rstat;
2882
2883 /* Almost all relocs have to do with relaxing. If any work must
2884 be done for them, it has been done in sh_relax_section. */
2885 if (rel->r_type != R_SH_IMM32
2886#ifdef COFF_WITH_PE
2887 && rel->r_type != R_SH_IMM32CE
2888 && rel->r_type != R_SH_IMAGEBASE
2889#endif
2890 && rel->r_type != R_SH_PCDISP)
2891 continue;
2892
2893 symndx = rel->r_symndx;
2894
2895 if (symndx == -1)
2896 {
2897 h = NULL;
2898 sym = NULL;
2899 }
2900 else
2901 {
2902 if (symndx < 0
2903 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
2904 {
2905 (*_bfd_error_handler)
2906 ("%s: illegal symbol index %ld in relocs",
2907 bfd_archive_filename (input_bfd), symndx);
2908 bfd_set_error (bfd_error_bad_value);
2909 return FALSE;
2910 }
2911 h = obj_coff_sym_hashes (input_bfd)[symndx];
2912 sym = syms + symndx;
2913 }
2914
2915 if (sym != NULL && sym->n_scnum != 0)
2916 addend = - sym->n_value;
2917 else
2918 addend = 0;
2919
2920 if (rel->r_type == R_SH_PCDISP)
2921 addend -= 4;
2922
2923 if (rel->r_type >= SH_COFF_HOWTO_COUNT)
2924 howto = NULL;
2925 else
2926 howto = &sh_coff_howtos[rel->r_type];
2927
2928 if (howto == NULL)
2929 {
2930 bfd_set_error (bfd_error_bad_value);
2931 return FALSE;
2932 }
2933
2934#ifdef COFF_WITH_PE
2935 if (rel->r_type == R_SH_IMAGEBASE)
2936 addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
2937#endif
2938
2939 val = 0;
2940
2941 if (h == NULL)
2942 {
2943 asection *sec;
2944
2945 /* There is nothing to do for an internal PCDISP reloc. */
2946 if (rel->r_type == R_SH_PCDISP)
2947 continue;
2948
2949 if (symndx == -1)
2950 {
2951 sec = bfd_abs_section_ptr;
2952 val = 0;
2953 }
2954 else
2955 {
2956 sec = sections[symndx];
2957 val = (sec->output_section->vma
2958 + sec->output_offset
2959 + sym->n_value
2960 - sec->vma);
2961 }
2962 }
2963 else
2964 {
2965 if (h->root.type == bfd_link_hash_defined
2966 || h->root.type == bfd_link_hash_defweak)
2967 {
2968 asection *sec;
2969
2970 sec = h->root.u.def.section;
2971 val = (h->root.u.def.value
2972 + sec->output_section->vma
2973 + sec->output_offset);
2974 }
2975 else if (! info->relocateable)
2976 {
2977 if (! ((*info->callbacks->undefined_symbol)
2978 (info, h->root.root.string, input_bfd, input_section,
2979 rel->r_vaddr - input_section->vma, TRUE)))
2980 return FALSE;
2981 }
2982 }
2983
2984 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
2985 contents,
2986 rel->r_vaddr - input_section->vma,
2987 val, addend);
2988
2989 switch (rstat)
2990 {
2991 default:
2992 abort ();
2993 case bfd_reloc_ok:
2994 break;
2995 case bfd_reloc_overflow:
2996 {
2997 const char *name;
2998 char buf[SYMNMLEN + 1];
2999
3000 if (symndx == -1)
3001 name = "*ABS*";
3002 else if (h != NULL)
3003 name = h->root.root.string;
3004 else if (sym->_n._n_n._n_zeroes == 0
3005 && sym->_n._n_n._n_offset != 0)
3006 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
3007 else
3008 {
3009 strncpy (buf, sym->_n._n_name, SYMNMLEN);
3010 buf[SYMNMLEN] = '\0';
3011 name = buf;
3012 }
3013
3014 if (! ((*info->callbacks->reloc_overflow)
3015 (info, name, howto->name, (bfd_vma) 0, input_bfd,
3016 input_section, rel->r_vaddr - input_section->vma)))
3017 return FALSE;
3018 }
3019 }
3020 }
3021
3022 return TRUE;
3023}
3024
3025/* This is a version of bfd_generic_get_relocated_section_contents
3026 which uses sh_relocate_section. */
3027
3028static bfd_byte *
3029sh_coff_get_relocated_section_contents (output_bfd, link_info, link_order,
3030 data, relocateable, symbols)
3031 bfd *output_bfd;
3032 struct bfd_link_info *link_info;
3033 struct bfd_link_order *link_order;
3034 bfd_byte *data;
3035 bfd_boolean relocateable;
3036 asymbol **symbols;
3037{
3038 asection *input_section = link_order->u.indirect.section;
3039 bfd *input_bfd = input_section->owner;
3040 asection **sections = NULL;
3041 struct internal_reloc *internal_relocs = NULL;
3042 struct internal_syment *internal_syms = NULL;
3043
3044 /* We only need to handle the case of relaxing, or of having a
3045 particular set of section contents, specially. */
3046 if (relocateable
3047 || coff_section_data (input_bfd, input_section) == NULL
3048 || coff_section_data (input_bfd, input_section)->contents == NULL)
3049 return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
3050 link_order, data,
3051 relocateable,
3052 symbols);
3053
3054 memcpy (data, coff_section_data (input_bfd, input_section)->contents,
3055 (size_t) input_section->_raw_size);
3056
3057 if ((input_section->flags & SEC_RELOC) != 0
3058 && input_section->reloc_count > 0)
3059 {
3060 bfd_size_type symesz = bfd_coff_symesz (input_bfd);
3061 bfd_byte *esym, *esymend;
3062 struct internal_syment *isymp;
3063 asection **secpp;
3064 bfd_size_type amt;
3065
3066 if (! _bfd_coff_get_external_symbols (input_bfd))
3067 goto error_return;
3068
3069 internal_relocs = (_bfd_coff_read_internal_relocs
3070 (input_bfd, input_section, FALSE, (bfd_byte *) NULL,
3071 FALSE, (struct internal_reloc *) NULL));
3072 if (internal_relocs == NULL)
3073 goto error_return;
3074
3075 amt = obj_raw_syment_count (input_bfd);
3076 amt *= sizeof (struct internal_syment);
3077 internal_syms = (struct internal_syment *) bfd_malloc (amt);
3078 if (internal_syms == NULL)
3079 goto error_return;
3080
3081 amt = obj_raw_syment_count (input_bfd);
3082 amt *= sizeof (asection *);
3083 sections = (asection **) bfd_malloc (amt);
3084 if (sections == NULL)
3085 goto error_return;
3086
3087 isymp = internal_syms;
3088 secpp = sections;
3089 esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
3090 esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
3091 while (esym < esymend)
3092 {
3093 bfd_coff_swap_sym_in (input_bfd, (PTR) esym, (PTR) isymp);
3094
3095 if (isymp->n_scnum != 0)
3096 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
3097 else
3098 {
3099 if (isymp->n_value == 0)
3100 *secpp = bfd_und_section_ptr;
3101 else
3102 *secpp = bfd_com_section_ptr;
3103 }
3104
3105 esym += (isymp->n_numaux + 1) * symesz;
3106 secpp += isymp->n_numaux + 1;
3107 isymp += isymp->n_numaux + 1;
3108 }
3109
3110 if (! sh_relocate_section (output_bfd, link_info, input_bfd,
3111 input_section, data, internal_relocs,
3112 internal_syms, sections))
3113 goto error_return;
3114
3115 free (sections);
3116 sections = NULL;
3117 free (internal_syms);
3118 internal_syms = NULL;
3119 free (internal_relocs);
3120 internal_relocs = NULL;
3121 }
3122
3123 return data;
3124
3125 error_return:
3126 if (internal_relocs != NULL)
3127 free (internal_relocs);
3128 if (internal_syms != NULL)
3129 free (internal_syms);
3130 if (sections != NULL)
3131 free (sections);
3132 return NULL;
3133}
3134
3135/* The target vectors. */
3136
3137#ifndef TARGET_SHL_SYM
3138CREATE_BIG_COFF_TARGET_VEC (shcoff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL)
3139#endif
3140
3141#ifdef TARGET_SHL_SYM
3142#define TARGET_SYM TARGET_SHL_SYM
3143#else
3144#define TARGET_SYM shlcoff_vec
3145#endif
3146
3147#ifndef TARGET_SHL_NAME
3148#define TARGET_SHL_NAME "coff-shl"
3149#endif
3150
3151#ifdef COFF_WITH_PE
3152CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3153 SEC_CODE | SEC_DATA, '_', NULL);
3154#else
3155CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3156 0, '_', NULL)
3157#endif
3158
3159#ifndef TARGET_SHL_SYM
3160static const bfd_target * coff_small_object_p PARAMS ((bfd *));
3161static bfd_boolean coff_small_new_section_hook PARAMS ((bfd *, asection *));
3162/* Some people want versions of the SH COFF target which do not align
3163 to 16 byte boundaries. We implement that by adding a couple of new
3164 target vectors. These are just like the ones above, but they
3165 change the default section alignment. To generate them in the
3166 assembler, use -small. To use them in the linker, use -b
3167 coff-sh{l}-small and -oformat coff-sh{l}-small.
3168
3169 Yes, this is a horrible hack. A general solution for setting
3170 section alignment in COFF is rather complex. ELF handles this
3171 correctly. */
3172
3173/* Only recognize the small versions if the target was not defaulted.
3174 Otherwise we won't recognize the non default endianness. */
3175
3176static const bfd_target *
3177coff_small_object_p (abfd)
3178 bfd *abfd;
3179{
3180 if (abfd->target_defaulted)
3181 {
3182 bfd_set_error (bfd_error_wrong_format);
3183 return NULL;
3184 }
3185 return coff_object_p (abfd);
3186}
3187
3188/* Set the section alignment for the small versions. */
3189
3190static bfd_boolean
3191coff_small_new_section_hook (abfd, section)
3192 bfd *abfd;
3193 asection *section;
3194{
3195 if (! coff_new_section_hook (abfd, section))
3196 return FALSE;
3197
3198 /* We must align to at least a four byte boundary, because longword
3199 accesses must be on a four byte boundary. */
3200 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
3201 section->alignment_power = 2;
3202
3203 return TRUE;
3204}
3205
3206/* This is copied from bfd_coff_std_swap_table so that we can change
3207 the default section alignment power. */
3208
3209static const bfd_coff_backend_data bfd_coff_small_swap_table =
3210{
3211 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
3212 coff_swap_aux_out, coff_swap_sym_out,
3213 coff_swap_lineno_out, coff_swap_reloc_out,
3214 coff_swap_filehdr_out, coff_swap_aouthdr_out,
3215 coff_swap_scnhdr_out,
3216 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN,
3217#ifdef COFF_LONG_FILENAMES
3218 TRUE,
3219#else
3220 FALSE,
3221#endif
3222#ifdef COFF_LONG_SECTION_NAMES
3223 TRUE,
3224#else
3225 FALSE,
3226#endif
3227 2,
3228#ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
3229 TRUE,
3230#else
3231 FALSE,
3232#endif
3233#ifdef COFF_DEBUG_STRING_WIDE_PREFIX
3234 4,
3235#else
3236 2,
3237#endif
3238 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
3239 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
3240 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
3241 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
3242 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
3243 coff_classify_symbol, coff_compute_section_file_positions,
3244 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
3245 coff_adjust_symndx, coff_link_add_one_symbol,
3246 coff_link_output_has_begun, coff_final_link_postscript
3247};
3248
3249#define coff_small_close_and_cleanup \
3250 coff_close_and_cleanup
3251#define coff_small_bfd_free_cached_info \
3252 coff_bfd_free_cached_info
3253#define coff_small_get_section_contents \
3254 coff_get_section_contents
3255#define coff_small_get_section_contents_in_window \
3256 coff_get_section_contents_in_window
3257
3258extern const bfd_target shlcoff_small_vec;
3259
3260const bfd_target shcoff_small_vec =
3261{
3262 "coff-sh-small", /* name */
3263 bfd_target_coff_flavour,
3264 BFD_ENDIAN_BIG, /* data byte order is big */
3265 BFD_ENDIAN_BIG, /* header byte order is big */
3266
3267 (HAS_RELOC | EXEC_P | /* object flags */
3268 HAS_LINENO | HAS_DEBUG |
3269 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3270
3271 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3272 '_', /* leading symbol underscore */
3273 '/', /* ar_pad_char */
3274 15, /* ar_max_namelen */
3275 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3276 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3277 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
3278 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3279 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3280 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
3281
3282 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
3283 bfd_generic_archive_p, _bfd_dummy_target},
3284 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3285 bfd_false},
3286 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3287 _bfd_write_archive_contents, bfd_false},
3288
3289 BFD_JUMP_TABLE_GENERIC (coff_small),
3290 BFD_JUMP_TABLE_COPY (coff),
3291 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3292 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3293 BFD_JUMP_TABLE_SYMBOLS (coff),
3294 BFD_JUMP_TABLE_RELOCS (coff),
3295 BFD_JUMP_TABLE_WRITE (coff),
3296 BFD_JUMP_TABLE_LINK (coff),
3297 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3298
3299 & shlcoff_small_vec,
3300
3301 (PTR) &bfd_coff_small_swap_table
3302};
3303
3304const bfd_target shlcoff_small_vec =
3305{
3306 "coff-shl-small", /* name */
3307 bfd_target_coff_flavour,
3308 BFD_ENDIAN_LITTLE, /* data byte order is little */
3309 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
3310
3311 (HAS_RELOC | EXEC_P | /* object flags */
3312 HAS_LINENO | HAS_DEBUG |
3313 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3314
3315 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3316 '_', /* leading symbol underscore */
3317 '/', /* ar_pad_char */
3318 15, /* ar_max_namelen */
3319 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3320 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3321 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
3322 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3323 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3324 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
3325
3326 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
3327 bfd_generic_archive_p, _bfd_dummy_target},
3328 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3329 bfd_false},
3330 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3331 _bfd_write_archive_contents, bfd_false},
3332
3333 BFD_JUMP_TABLE_GENERIC (coff_small),
3334 BFD_JUMP_TABLE_COPY (coff),
3335 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3336 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3337 BFD_JUMP_TABLE_SYMBOLS (coff),
3338 BFD_JUMP_TABLE_RELOCS (coff),
3339 BFD_JUMP_TABLE_WRITE (coff),
3340 BFD_JUMP_TABLE_LINK (coff),
3341 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3342
3343 & shcoff_small_vec,
3344
3345 (PTR) &bfd_coff_small_swap_table
3346};
3347#endif
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