source: branches/libc-0.6/src/binutils/opcodes/frv-dis.c

Last change on this file was 607, checked in by bird, 22 years ago

Initial revision
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File size: 24.8 KB
Line 
1/* Disassembler interface for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4THIS FILE IS MACHINE GENERATED WITH CGEN.
5- the resultant file is machine generated, cgen-dis.in isn't
6
7Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
8Free Software Foundation, Inc.
9
10This file is part of the GNU Binutils and GDB, the GNU debugger.
11
12This program is free software; you can redistribute it and/or modify
13it under the terms of the GNU General Public License as published by
14the Free Software Foundation; either version 2, or (at your option)
15any later version.
16
17This program is distributed in the hope that it will be useful,
18but WITHOUT ANY WARRANTY; without even the implied warranty of
19MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20GNU General Public License for more details.
21
22You should have received a copy of the GNU General Public License
23along with this program; if not, write to the Free Software Foundation, Inc.,
2459 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25
26/* ??? Eventually more and more of this stuff can go to cpu-independent files.
27 Keep that in mind. */
28
29#include "sysdep.h"
30#include <stdio.h>
31#include "ansidecl.h"
32#include "dis-asm.h"
33#include "bfd.h"
34#include "symcat.h"
35#include "libiberty.h"
36#include "frv-desc.h"
37#include "frv-opc.h"
38#include "opintl.h"
39
40/* Default text to print if an instruction isn't recognized. */
41#define UNKNOWN_INSN_MSG _("*unknown*")
42
43static void print_normal
44 PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
45static void print_address
46 PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
47static void print_keyword
48 PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
49static void print_insn_normal
50 PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
51 bfd_vma, int));
52static int print_insn
53 PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned));
54static int default_print_insn
55 PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
56static int read_insn
57 PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
58 CGEN_EXTRACT_INFO *, unsigned long *));
59
60
61/* -- disassembler routines inserted here */
62
63/* -- dis.c */
64static void print_spr
65 PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned));
66static void print_hi
67 PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
68static void print_lo
69 PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
70
71static void
72print_spr (cd, dis_info, names, regno, attrs)
73 CGEN_CPU_DESC cd;
74 PTR dis_info;
75 CGEN_KEYWORD *names;
76 long regno;
77 unsigned int attrs;
78{
79 /* Use the register index format for any unnamed registers. */
80 if (cgen_keyword_lookup_value (names, regno) == NULL)
81 {
82 disassemble_info *info = (disassemble_info *) dis_info;
83 (*info->fprintf_func) (info->stream, "spr[%ld]", regno);
84 }
85 else
86 print_keyword (cd, dis_info, names, regno, attrs);
87}
88
89static void
90print_hi (cd, dis_info, value, attrs, pc, length)
91 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
92 PTR dis_info;
93 long value;
94 unsigned int attrs ATTRIBUTE_UNUSED;
95 bfd_vma pc ATTRIBUTE_UNUSED;
96 int length ATTRIBUTE_UNUSED;
97{
98 disassemble_info *info = (disassemble_info *) dis_info;
99 if (value)
100 (*info->fprintf_func) (info->stream, "0x%lx", value);
101 else
102 (*info->fprintf_func) (info->stream, "hi(0x%lx)", value);
103}
104
105static void
106print_lo (cd, dis_info, value, attrs, pc, length)
107 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
108 PTR dis_info;
109 long value;
110 unsigned int attrs ATTRIBUTE_UNUSED;
111 bfd_vma pc ATTRIBUTE_UNUSED;
112 int length ATTRIBUTE_UNUSED;
113{
114 disassemble_info *info = (disassemble_info *) dis_info;
115 if (value)
116 (*info->fprintf_func) (info->stream, "0x%lx", value);
117 else
118 (*info->fprintf_func) (info->stream, "lo(0x%lx)", value);
119}
120
121/* -- */
122
123void frv_cgen_print_operand
124 PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
125 void const *, bfd_vma, int));
126
127/* Main entry point for printing operands.
128 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
129 of dis-asm.h on cgen.h.
130
131 This function is basically just a big switch statement. Earlier versions
132 used tables to look up the function to use, but
133 - if the table contains both assembler and disassembler functions then
134 the disassembler contains much of the assembler and vice-versa,
135 - there's a lot of inlining possibilities as things grow,
136 - using a switch statement avoids the function call overhead.
137
138 This function could be moved into `print_insn_normal', but keeping it
139 separate makes clear the interface between `print_insn_normal' and each of
140 the handlers. */
141
142void
143frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
144 CGEN_CPU_DESC cd;
145 int opindex;
146 PTR xinfo;
147 CGEN_FIELDS *fields;
148 void const *attrs ATTRIBUTE_UNUSED;
149 bfd_vma pc;
150 int length;
151{
152 disassemble_info *info = (disassemble_info *) xinfo;
153
154 switch (opindex)
155 {
156 case FRV_OPERAND_A :
157 print_normal (cd, info, fields->f_A, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
158 break;
159 case FRV_OPERAND_ACC40SI :
160 print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Si, 0);
161 break;
162 case FRV_OPERAND_ACC40SK :
163 print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Sk, 0);
164 break;
165 case FRV_OPERAND_ACC40UI :
166 print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Ui, 0);
167 break;
168 case FRV_OPERAND_ACC40UK :
169 print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Uk, 0);
170 break;
171 case FRV_OPERAND_ACCGI :
172 print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGi, 0);
173 break;
174 case FRV_OPERAND_ACCGK :
175 print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGk, 0);
176 break;
177 case FRV_OPERAND_CCI :
178 print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CCi, 0);
179 break;
180 case FRV_OPERAND_CPRDOUBLEK :
181 print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0);
182 break;
183 case FRV_OPERAND_CPRI :
184 print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRi, 0);
185 break;
186 case FRV_OPERAND_CPRJ :
187 print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRj, 0);
188 break;
189 case FRV_OPERAND_CPRK :
190 print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0);
191 break;
192 case FRV_OPERAND_CRI :
193 print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRi, 0);
194 break;
195 case FRV_OPERAND_CRJ :
196 print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj, 0);
197 break;
198 case FRV_OPERAND_CRJ_FLOAT :
199 print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_float, 0);
200 break;
201 case FRV_OPERAND_CRJ_INT :
202 print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_int, 0);
203 break;
204 case FRV_OPERAND_CRK :
205 print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRk, 0);
206 break;
207 case FRV_OPERAND_FCCI_1 :
208 print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_1, 0);
209 break;
210 case FRV_OPERAND_FCCI_2 :
211 print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_2, 0);
212 break;
213 case FRV_OPERAND_FCCI_3 :
214 print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_3, 0);
215 break;
216 case FRV_OPERAND_FCCK :
217 print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCk, 0);
218 break;
219 case FRV_OPERAND_FRDOUBLEI :
220 print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
221 break;
222 case FRV_OPERAND_FRDOUBLEJ :
223 print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
224 break;
225 case FRV_OPERAND_FRDOUBLEK :
226 print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
227 break;
228 case FRV_OPERAND_FRI :
229 print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
230 break;
231 case FRV_OPERAND_FRINTI :
232 print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
233 break;
234 case FRV_OPERAND_FRINTJ :
235 print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
236 break;
237 case FRV_OPERAND_FRINTK :
238 print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
239 break;
240 case FRV_OPERAND_FRJ :
241 print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
242 break;
243 case FRV_OPERAND_FRK :
244 print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
245 break;
246 case FRV_OPERAND_FRKHI :
247 print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
248 break;
249 case FRV_OPERAND_FRKLO :
250 print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
251 break;
252 case FRV_OPERAND_GRDOUBLEK :
253 print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
254 break;
255 case FRV_OPERAND_GRI :
256 print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRi, 0);
257 break;
258 case FRV_OPERAND_GRJ :
259 print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRj, 0);
260 break;
261 case FRV_OPERAND_GRK :
262 print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
263 break;
264 case FRV_OPERAND_GRKHI :
265 print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
266 break;
267 case FRV_OPERAND_GRKLO :
268 print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
269 break;
270 case FRV_OPERAND_ICCI_1 :
271 print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_1, 0);
272 break;
273 case FRV_OPERAND_ICCI_2 :
274 print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_2, 0);
275 break;
276 case FRV_OPERAND_ICCI_3 :
277 print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_3, 0);
278 break;
279 case FRV_OPERAND_LI :
280 print_normal (cd, info, fields->f_LI, 0, pc, length);
281 break;
282 case FRV_OPERAND_AE :
283 print_normal (cd, info, fields->f_ae, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
284 break;
285 case FRV_OPERAND_CCOND :
286 print_normal (cd, info, fields->f_ccond, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
287 break;
288 case FRV_OPERAND_COND :
289 print_normal (cd, info, fields->f_cond, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
290 break;
291 case FRV_OPERAND_D12 :
292 print_normal (cd, info, fields->f_d12, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
293 break;
294 case FRV_OPERAND_DEBUG :
295 print_normal (cd, info, fields->f_debug, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
296 break;
297 case FRV_OPERAND_EIR :
298 print_normal (cd, info, fields->f_eir, 0, pc, length);
299 break;
300 case FRV_OPERAND_HINT :
301 print_normal (cd, info, fields->f_hint, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
302 break;
303 case FRV_OPERAND_HINT_NOT_TAKEN :
304 print_keyword (cd, info, & frv_cgen_opval_h_hint_not_taken, fields->f_hint, 0);
305 break;
306 case FRV_OPERAND_HINT_TAKEN :
307 print_keyword (cd, info, & frv_cgen_opval_h_hint_taken, fields->f_hint, 0);
308 break;
309 case FRV_OPERAND_LABEL16 :
310 print_address (cd, info, fields->f_label16, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
311 break;
312 case FRV_OPERAND_LABEL24 :
313 print_address (cd, info, fields->f_label24, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
314 break;
315 case FRV_OPERAND_LOCK :
316 print_normal (cd, info, fields->f_lock, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
317 break;
318 case FRV_OPERAND_PACK :
319 print_keyword (cd, info, & frv_cgen_opval_h_pack, fields->f_pack, 0);
320 break;
321 case FRV_OPERAND_S10 :
322 print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
323 break;
324 case FRV_OPERAND_S12 :
325 print_normal (cd, info, fields->f_d12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
326 break;
327 case FRV_OPERAND_S16 :
328 print_normal (cd, info, fields->f_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
329 break;
330 case FRV_OPERAND_S5 :
331 print_normal (cd, info, fields->f_s5, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
332 break;
333 case FRV_OPERAND_S6 :
334 print_normal (cd, info, fields->f_s6, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
335 break;
336 case FRV_OPERAND_S6_1 :
337 print_normal (cd, info, fields->f_s6_1, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
338 break;
339 case FRV_OPERAND_SLO16 :
340 print_lo (cd, info, fields->f_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
341 break;
342 case FRV_OPERAND_SPR :
343 print_spr (cd, info, & frv_cgen_opval_spr_names, fields->f_spr, 0|(1<<CGEN_OPERAND_VIRTUAL));
344 break;
345 case FRV_OPERAND_U12 :
346 print_normal (cd, info, fields->f_u12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
347 break;
348 case FRV_OPERAND_U16 :
349 print_normal (cd, info, fields->f_u16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
350 break;
351 case FRV_OPERAND_U6 :
352 print_normal (cd, info, fields->f_u6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
353 break;
354 case FRV_OPERAND_UHI16 :
355 print_hi (cd, info, fields->f_u16, 0, pc, length);
356 break;
357 case FRV_OPERAND_ULO16 :
358 print_lo (cd, info, fields->f_u16, 0, pc, length);
359 break;
360
361 default :
362 /* xgettext:c-format */
363 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
364 opindex);
365 abort ();
366 }
367}
368
369cgen_print_fn * const frv_cgen_print_handlers[] =
370{
371 print_insn_normal,
372};
373
374
375void
376frv_cgen_init_dis (cd)
377 CGEN_CPU_DESC cd;
378{
379 frv_cgen_init_opcode_table (cd);
380 frv_cgen_init_ibld_table (cd);
381 cd->print_handlers = & frv_cgen_print_handlers[0];
382 cd->print_operand = frv_cgen_print_operand;
383}
384
385
386
387/* Default print handler. */
388
389static void
390print_normal (cd, dis_info, value, attrs, pc, length)
391 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
392 PTR dis_info;
393 long value;
394 unsigned int attrs;
395 bfd_vma pc ATTRIBUTE_UNUSED;
396 int length ATTRIBUTE_UNUSED;
397{
398 disassemble_info *info = (disassemble_info *) dis_info;
399
400#ifdef CGEN_PRINT_NORMAL
401 CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
402#endif
403
404 /* Print the operand as directed by the attributes. */
405 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
406 ; /* nothing to do */
407 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
408 (*info->fprintf_func) (info->stream, "%ld", value);
409 else
410 (*info->fprintf_func) (info->stream, "0x%lx", value);
411}
412
413/* Default address handler. */
414
415static void
416print_address (cd, dis_info, value, attrs, pc, length)
417 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
418 PTR dis_info;
419 bfd_vma value;
420 unsigned int attrs;
421 bfd_vma pc ATTRIBUTE_UNUSED;
422 int length ATTRIBUTE_UNUSED;
423{
424 disassemble_info *info = (disassemble_info *) dis_info;
425
426#ifdef CGEN_PRINT_ADDRESS
427 CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
428#endif
429
430 /* Print the operand as directed by the attributes. */
431 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
432 ; /* nothing to do */
433 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
434 (*info->print_address_func) (value, info);
435 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
436 (*info->print_address_func) (value, info);
437 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
438 (*info->fprintf_func) (info->stream, "%ld", (long) value);
439 else
440 (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
441}
442
443/* Keyword print handler. */
444
445static void
446print_keyword (cd, dis_info, keyword_table, value, attrs)
447 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
448 PTR dis_info;
449 CGEN_KEYWORD *keyword_table;
450 long value;
451 unsigned int attrs ATTRIBUTE_UNUSED;
452{
453 disassemble_info *info = (disassemble_info *) dis_info;
454 const CGEN_KEYWORD_ENTRY *ke;
455
456 ke = cgen_keyword_lookup_value (keyword_table, value);
457 if (ke != NULL)
458 (*info->fprintf_func) (info->stream, "%s", ke->name);
459 else
460 (*info->fprintf_func) (info->stream, "???");
461}
462
463
464/* Default insn printer.
465
466 DIS_INFO is defined as `PTR' so the disassembler needn't know anything
467 about disassemble_info. */
468
469static void
470print_insn_normal (cd, dis_info, insn, fields, pc, length)
471 CGEN_CPU_DESC cd;
472 PTR dis_info;
473 const CGEN_INSN *insn;
474 CGEN_FIELDS *fields;
475 bfd_vma pc;
476 int length;
477{
478 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
479 disassemble_info *info = (disassemble_info *) dis_info;
480 const CGEN_SYNTAX_CHAR_TYPE *syn;
481
482 CGEN_INIT_PRINT (cd);
483
484 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
485 {
486 if (CGEN_SYNTAX_MNEMONIC_P (*syn))
487 {
488 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
489 continue;
490 }
491 if (CGEN_SYNTAX_CHAR_P (*syn))
492 {
493 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
494 continue;
495 }
496
497 /* We have an operand. */
498 frv_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
499 fields, CGEN_INSN_ATTRS (insn), pc, length);
500 }
501}
502
503
504/* Subroutine of print_insn. Reads an insn into the given buffers and updates
505 the extract info.
506 Returns 0 if all is well, non-zero otherwise. */
507
508static int
509read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
510 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
511 bfd_vma pc;
512 disassemble_info *info;
513 char *buf;
514 int buflen;
515 CGEN_EXTRACT_INFO *ex_info;
516 unsigned long *insn_value;
517{
518 int status = (*info->read_memory_func) (pc, buf, buflen, info);
519 if (status != 0)
520 {
521 (*info->memory_error_func) (status, pc, info);
522 return -1;
523 }
524
525 ex_info->dis_info = info;
526 ex_info->valid = (1 << buflen) - 1;
527 ex_info->insn_bytes = buf;
528
529 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
530 return 0;
531}
532
533/* Utility to print an insn.
534 BUF is the base part of the insn, target byte order, BUFLEN bytes long.
535 The result is the size of the insn in bytes or zero for an unknown insn
536 or -1 if an error occurs fetching data (memory_error_func will have
537 been called). */
538
539static int
540print_insn (cd, pc, info, buf, buflen)
541 CGEN_CPU_DESC cd;
542 bfd_vma pc;
543 disassemble_info *info;
544 char *buf;
545 unsigned int buflen;
546{
547 CGEN_INSN_INT insn_value;
548 const CGEN_INSN_LIST *insn_list;
549 CGEN_EXTRACT_INFO ex_info;
550 int basesize;
551
552 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
553 basesize = cd->base_insn_bitsize < buflen * 8 ?
554 cd->base_insn_bitsize : buflen * 8;
555 insn_value = cgen_get_insn_value (cd, buf, basesize);
556
557
558 /* Fill in ex_info fields like read_insn would. Don't actually call
559 read_insn, since the incoming buffer is already read (and possibly
560 modified a la m32r). */
561 ex_info.valid = (1 << buflen) - 1;
562 ex_info.dis_info = info;
563 ex_info.insn_bytes = buf;
564
565 /* The instructions are stored in hash lists.
566 Pick the first one and keep trying until we find the right one. */
567
568 insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
569 while (insn_list != NULL)
570 {
571 const CGEN_INSN *insn = insn_list->insn;
572 CGEN_FIELDS fields;
573 int length;
574 unsigned long insn_value_cropped;
575
576#ifdef CGEN_VALIDATE_INSN_SUPPORTED
577 /* Not needed as insn shouldn't be in hash lists if not supported. */
578 /* Supported by this cpu? */
579 if (! frv_cgen_insn_supported (cd, insn))
580 {
581 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
582 continue;
583 }
584#endif
585
586 /* Basic bit mask must be correct. */
587 /* ??? May wish to allow target to defer this check until the extract
588 handler. */
589
590 /* Base size may exceed this instruction's size. Extract the
591 relevant part from the buffer. */
592 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
593 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
594 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
595 info->endian == BFD_ENDIAN_BIG);
596 else
597 insn_value_cropped = insn_value;
598
599 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
600 == CGEN_INSN_BASE_VALUE (insn))
601 {
602 /* Printing is handled in two passes. The first pass parses the
603 machine insn and extracts the fields. The second pass prints
604 them. */
605
606 /* Make sure the entire insn is loaded into insn_value, if it
607 can fit. */
608 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
609 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
610 {
611 unsigned long full_insn_value;
612 int rc = read_insn (cd, pc, info, buf,
613 CGEN_INSN_BITSIZE (insn) / 8,
614 & ex_info, & full_insn_value);
615 if (rc != 0)
616 return rc;
617 length = CGEN_EXTRACT_FN (cd, insn)
618 (cd, insn, &ex_info, full_insn_value, &fields, pc);
619 }
620 else
621 length = CGEN_EXTRACT_FN (cd, insn)
622 (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
623
624 /* length < 0 -> error */
625 if (length < 0)
626 return length;
627 if (length > 0)
628 {
629 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
630 /* length is in bits, result is in bytes */
631 return length / 8;
632 }
633 }
634
635 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
636 }
637
638 return 0;
639}
640
641/* Default value for CGEN_PRINT_INSN.
642 The result is the size of the insn in bytes or zero for an unknown insn
643 or -1 if an error occured fetching bytes. */
644
645#ifndef CGEN_PRINT_INSN
646#define CGEN_PRINT_INSN default_print_insn
647#endif
648
649static int
650default_print_insn (cd, pc, info)
651 CGEN_CPU_DESC cd;
652 bfd_vma pc;
653 disassemble_info *info;
654{
655 char buf[CGEN_MAX_INSN_SIZE];
656 int buflen;
657 int status;
658
659 /* Attempt to read the base part of the insn. */
660 buflen = cd->base_insn_bitsize / 8;
661 status = (*info->read_memory_func) (pc, buf, buflen, info);
662
663 /* Try again with the minimum part, if min < base. */
664 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
665 {
666 buflen = cd->min_insn_bitsize / 8;
667 status = (*info->read_memory_func) (pc, buf, buflen, info);
668 }
669
670 if (status != 0)
671 {
672 (*info->memory_error_func) (status, pc, info);
673 return -1;
674 }
675
676 return print_insn (cd, pc, info, buf, buflen);
677}
678
679/* Main entry point.
680 Print one instruction from PC on INFO->STREAM.
681 Return the size of the instruction (in bytes). */
682
683typedef struct cpu_desc_list {
684 struct cpu_desc_list *next;
685 int isa;
686 int mach;
687 int endian;
688 CGEN_CPU_DESC cd;
689} cpu_desc_list;
690
691int
692print_insn_frv (pc, info)
693 bfd_vma pc;
694 disassemble_info *info;
695{
696 static cpu_desc_list *cd_list = 0;
697 cpu_desc_list *cl = 0;
698 static CGEN_CPU_DESC cd = 0;
699 static int prev_isa;
700 static int prev_mach;
701 static int prev_endian;
702 int length;
703 int isa,mach;
704 int endian = (info->endian == BFD_ENDIAN_BIG
705 ? CGEN_ENDIAN_BIG
706 : CGEN_ENDIAN_LITTLE);
707 enum bfd_architecture arch;
708
709 /* ??? gdb will set mach but leave the architecture as "unknown" */
710#ifndef CGEN_BFD_ARCH
711#define CGEN_BFD_ARCH bfd_arch_frv
712#endif
713 arch = info->arch;
714 if (arch == bfd_arch_unknown)
715 arch = CGEN_BFD_ARCH;
716
717 /* There's no standard way to compute the machine or isa number
718 so we leave it to the target. */
719#ifdef CGEN_COMPUTE_MACH
720 mach = CGEN_COMPUTE_MACH (info);
721#else
722 mach = info->mach;
723#endif
724
725#ifdef CGEN_COMPUTE_ISA
726 isa = CGEN_COMPUTE_ISA (info);
727#else
728 isa = info->insn_sets;
729#endif
730
731 /* If we've switched cpu's, try to find a handle we've used before */
732 if (cd
733 && (isa != prev_isa
734 || mach != prev_mach
735 || endian != prev_endian))
736 {
737 cd = 0;
738 for (cl = cd_list; cl; cl = cl->next)
739 {
740 if (cl->isa == isa &&
741 cl->mach == mach &&
742 cl->endian == endian)
743 {
744 cd = cl->cd;
745 break;
746 }
747 }
748 }
749
750 /* If we haven't initialized yet, initialize the opcode table. */
751 if (! cd)
752 {
753 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
754 const char *mach_name;
755
756 if (!arch_type)
757 abort ();
758 mach_name = arch_type->printable_name;
759
760 prev_isa = isa;
761 prev_mach = mach;
762 prev_endian = endian;
763 cd = frv_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
764 CGEN_CPU_OPEN_BFDMACH, mach_name,
765 CGEN_CPU_OPEN_ENDIAN, prev_endian,
766 CGEN_CPU_OPEN_END);
767 if (!cd)
768 abort ();
769
770 /* save this away for future reference */
771 cl = xmalloc (sizeof (struct cpu_desc_list));
772 cl->cd = cd;
773 cl->isa = isa;
774 cl->mach = mach;
775 cl->endian = endian;
776 cl->next = cd_list;
777 cd_list = cl;
778
779 frv_cgen_init_dis (cd);
780 }
781
782 /* We try to have as much common code as possible.
783 But at this point some targets need to take over. */
784 /* ??? Some targets may need a hook elsewhere. Try to avoid this,
785 but if not possible try to move this hook elsewhere rather than
786 have two hooks. */
787 length = CGEN_PRINT_INSN (cd, pc, info);
788 if (length > 0)
789 return length;
790 if (length < 0)
791 return -1;
792
793 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
794 return cd->default_insn_bitsize / 8;
795}
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