| 1 | /* Opcode table for the TI MSP430 microcontrollers
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| 2 |
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| 3 | Copyright 2002 Free Software Foundation, Inc.
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| 4 | Contributed by Dmitry Diky <diwil@mail.ru>
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| 5 |
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| 6 | This program is free software; you can redistribute it and/or modify
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| 7 | it under the terms of the GNU General Public License as published by
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| 8 | the Free Software Foundation; either version 2, or (at your option)
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| 9 | any later version.
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| 10 |
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| 11 | This program is distributed in the hope that it will be useful,
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| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 14 | GNU General Public License for more details.
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| 15 |
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| 16 | You should have received a copy of the GNU General Public License
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| 17 | along with this program; if not, write to the Free Software
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| 18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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| 19 |
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| 20 | #ifndef __MSP430_H_
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| 21 | #define __MSP430_H_
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| 22 |
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| 23 | struct msp430_operand_s
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| 24 | {
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| 25 | int ol; /* Operand length words. */
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| 26 | int am; /* Addr mode. */
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| 27 | int reg; /* Register. */
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| 28 | int mode; /* Pperand mode. */
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| 29 | #define OP_REG 0
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| 30 | #define OP_EXP 1
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| 31 | #ifndef DASM_SECTION
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| 32 | expressionS exp;
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| 33 | #endif
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| 34 | };
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| 35 |
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| 36 | #define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */
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| 37 |
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| 38 | struct msp430_opcode_s
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| 39 | {
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| 40 | char *name;
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| 41 | int fmt;
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| 42 | int insn_opnumb;
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| 43 | int bin_opcode;
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| 44 | int bin_mask;
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| 45 | };
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| 46 |
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| 47 | #define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask }
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| 48 |
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| 49 | static struct msp430_opcode_s msp430_opcodes[] =
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| 50 | {
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| 51 | MSP_INSN (and, 1, 2, 0xf000, 0xf000),
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| 52 | MSP_INSN (inv, 0, 1, 0xe330, 0xfff0),
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| 53 | MSP_INSN (xor, 1, 2, 0xe000, 0xf000),
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| 54 | MSP_INSN (setz, 0, 0, 0xd322, 0xffff),
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| 55 | MSP_INSN (setc, 0, 0, 0xd312, 0xffff),
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| 56 | MSP_INSN (eint, 0, 0, 0xd232, 0xffff),
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| 57 | MSP_INSN (setn, 0, 0, 0xd222, 0xffff),
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| 58 | MSP_INSN (bis, 1, 2, 0xd000, 0xf000),
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| 59 | MSP_INSN (clrz, 0, 0, 0xc322, 0xffff),
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| 60 | MSP_INSN (clrc, 0, 0, 0xc312, 0xffff),
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| 61 | MSP_INSN (dint, 0, 0, 0xc232, 0xffff),
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| 62 | MSP_INSN (clrn, 0, 0, 0xc222, 0xffff),
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| 63 | MSP_INSN (bic, 1, 2, 0xc000, 0xf000),
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| 64 | MSP_INSN (bit, 1, 2, 0xb000, 0xf000),
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| 65 | MSP_INSN (dadc, 0, 1, 0xa300, 0xff30),
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| 66 | MSP_INSN (dadd, 1, 2, 0xa000, 0xf000),
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| 67 | MSP_INSN (tst, 0, 1, 0x9300, 0xff30),
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| 68 | MSP_INSN (cmp, 1, 2, 0x9000, 0xf000),
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| 69 | MSP_INSN (decd, 0, 1, 0x8320, 0xff30),
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| 70 | MSP_INSN (dec, 0, 1, 0x8310, 0xff30),
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| 71 | MSP_INSN (sub, 1, 2, 0x8000, 0xf000),
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| 72 | MSP_INSN (sbc, 0, 1, 0x7300, 0xff30),
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| 73 | MSP_INSN (subc, 1, 2, 0x7000, 0xf000),
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| 74 | MSP_INSN (adc, 0, 1, 0x6300, 0xff30),
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| 75 | MSP_INSN (rlc, 0, 2, 0x6000, 0xf000),
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| 76 | MSP_INSN (addc, 1, 2, 0x6000, 0xf000),
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| 77 | MSP_INSN (incd, 0, 1, 0x5320, 0xff30),
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| 78 | MSP_INSN (inc, 0, 1, 0x5310, 0xff30),
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| 79 | MSP_INSN (rla, 0, 2, 0x5000, 0xf000),
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| 80 | MSP_INSN (add, 1, 2, 0x5000, 0xf000),
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| 81 | MSP_INSN (nop, 0, 0, 0x4303, 0xffff),
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| 82 | MSP_INSN (clr, 0, 1, 0x4300, 0xff30),
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| 83 | MSP_INSN (ret, 0, 0, 0x4130, 0xff30),
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| 84 | MSP_INSN (pop, 0, 1, 0x4130, 0xff30),
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| 85 | MSP_INSN (br, 0, 3, 0x4000, 0xf000),
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| 86 | MSP_INSN (mov, 1, 2, 0x4000, 0xf000),
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| 87 | MSP_INSN (jmp, 3, 1, 0x3c00, 0xfc00),
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| 88 | MSP_INSN (jl, 3, 1, 0x3800, 0xfc00),
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| 89 | MSP_INSN (jge, 3, 1, 0x3400, 0xfc00),
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| 90 | MSP_INSN (jn, 3, 1, 0x3000, 0xfc00),
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| 91 | MSP_INSN (jc, 3, 1, 0x2c00, 0xfc00),
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| 92 | MSP_INSN (jhs, 3, 1, 0x2c00, 0xfc00),
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| 93 | MSP_INSN (jnc, 3, 1, 0x2800, 0xfc00),
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| 94 | MSP_INSN (jlo, 3, 1, 0x2800, 0xfc00),
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| 95 | MSP_INSN (jz, 3, 1, 0x2400, 0xfc00),
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| 96 | MSP_INSN (jeq, 3, 1, 0x2400, 0xfc00),
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| 97 | MSP_INSN (jnz, 3, 1, 0x2000, 0xfc00),
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| 98 | MSP_INSN (jne, 3, 1, 0x2000, 0xfc00),
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| 99 | MSP_INSN (reti, 2, 0, 0x1300, 0xffc0),
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| 100 | MSP_INSN (call, 2, 1, 0x1280, 0xffc0),
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| 101 | MSP_INSN (push, 2, 1, 0x1200, 0xff80),
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| 102 | MSP_INSN (sxt, 2, 1, 0x1180, 0xffc0),
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| 103 | MSP_INSN (rra, 2, 1, 0x1100, 0xff80),
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| 104 | MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0),
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| 105 | MSP_INSN (rrc, 2, 1, 0x1000, 0xff80),
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| 106 |
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| 107 | /* End of instruction set. */
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| 108 | { NULL, 0, 0, 0, 0 }
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| 109 | };
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| 110 |
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| 111 | #endif
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