Changeset 309 for trunk/openjdk/hotspot/src/cpu/sparc

trunk/openjdk

Property svn:mergeinfo changed
/branches/vendor/oracle/openjdk6/b24 (added) merged: 308
/branches/vendor/oracle/openjdk6/current merged: 307

trunk/openjdk/hotspot/src/cpu/sparc/vm/assembler_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "incls/_precompiled.incl"
+#include "incls/_assembler_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "asm/assembler.hpp"
+#include "assembler_sparc.inline.hpp"
+#include "gc_interface/collectedHeap.inline.hpp"
+#include "interpreter/interpreter.hpp"
+#include "memory/cardTableModRefBS.hpp"
+#include "memory/resourceArea.hpp"
+#include "prims/methodHandles.hpp"
+#include "runtime/biasedLocking.hpp"
+#include "runtime/interfaceSupport.hpp"
+#include "runtime/objectMonitor.hpp"
+#include "runtime/os.hpp"
+#include "runtime/sharedRuntime.hpp"
+#include "runtime/stubRoutines.hpp"
+#ifndef SERIALGC
+#include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
+#include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
+#include "gc_implementation/g1/heapRegion.hpp"
+#endif
 // Convert the raw encoding form into the form expected by the
 …
     // Save & restore possible 64-bit Long arguments in G-regs
     sllx(L0,32,G2);             // Move old high G1 bits high in G2
     sllx(G1, 0,G1);             // Clear current high G1 bits
+    srl(G1, 0,G1);              // Clear current high G1 bits
     or3 (G1,G2,G1);             // Recover 64-bit G1
     sllx(L6,32,G2);             // Move old high G4 bits high in G2
     sllx(G4, 0,G4);             // Clear current high G4 bits
+    srl(G4, 0,G4);              // Clear current high G4 bits
     or3 (G4,G2,G4);             // Recover 64-bit G4
 #endif
 …
 int MacroAssembler::size_of_sethi(address a, bool worst_case) {
+int MacroAssembler::insts_for_sethi(address a, bool worst_case) {
 #ifdef _LP64
   if (worst_case) return 7;
   intptr_t iaddr = (intptr_t)a;
   int hi32 = (int)(iaddr >> 32);
   int lo32 = (int)(iaddr);
   int inst_count;
   if (hi32 == 0 && lo32 >= 0)
     inst_count = 1;
   else if (hi32 == -1)
     inst_count = 2;
+  if (worst_case)  return 7;
+  intptr_t iaddr = (intptr_t) a;
+  int msb32 = (int) (iaddr >> 32);
+  int lsb32 = (int) (iaddr);
+  int count;
+  if (msb32 == 0 && lsb32 >= 0)
+    count = 1;
+  else if (msb32 == -1)
+    count = 2;
   else {
     inst_count = 2;
     if ( hi32 & 0x3ff )
       inst_count++;
     if ( lo32 & 0xFFFFFC00 ) {
       if( (lo32 >> 20) & 0xfff ) inst_count += 2;
       if( (lo32 >> 10) & 0x3ff ) inst_count += 2;
+    count = 2;
+    if (msb32 & 0x3ff)
+      count++;
+    if (lsb32 & 0xFFFFFC00 ) {
+      if ((lsb32 >> 20) & 0xfff)  count += 2;
+      if ((lsb32 >> 10) & 0x3ff)  count += 2;
+    }
+  }
   return BytesPerInstWord * inst_count;
+  return count;
 #else
   return BytesPerInstWord;
+  return 1;
 #endif
+}
+int MacroAssembler::worst_case_size_of_set() {
+  return size_of_sethi(NULL, true) + 1;
+}
+int MacroAssembler::worst_case_insts_for_set() {
+  return insts_for_sethi(NULL, true) + 1;
+}
+// Keep in sync with MacroAssembler::insts_for_internal_set
 void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
   intptr_t value = addrlit.value();
 …
+}
+// Keep in sync with MacroAssembler::internal_set
+int MacroAssembler::insts_for_internal_set(intptr_t value) {
+  // can optimize
+  if (-4096 <= value && value <= 4095) {
+    return 1;
+  }
+  if (inv_hi22(hi22(value)) == value) {
+    return insts_for_sethi((address) value);
+  }
+  int count = insts_for_sethi((address) value);
+  AddressLiteral al(value);
+  if (al.low10() != 0) {
+    count++;
+  }
+  return count;
+}
 void MacroAssembler::set(const AddressLiteral& al, Register d) {
   internal_set(al, d, false);
 …
     or3 (d, tmp, d);
+  }
+}
+int MacroAssembler::insts_for_set64(jlong value) {
+  v9_dep();
+  int hi = (int) (value >> 32);
+  int lo = (int) (value & ~0);
+  int count = 0;
+  // (Matcher::isSimpleConstant64 knows about the following optimizations.)
+  if (Assembler::is_simm13(lo) && value == lo) {
+    count++;
+  } else if (hi == 0) {
+    count++;
+    if (low10(lo) != 0)
+      count++;
+  }
+  else if (hi == -1) {
+    count += 2;
+  }
+  else if (lo == 0) {
+    if (Assembler::is_simm13(hi)) {
+      count++;
+    } else {
+      count++;
+      if (low10(hi) != 0)
+        count++;
+    }
+    count++;
+  }
+  else {
+    count += 2;
+    if (low10(hi) != 0)
+      count++;
+    if (low10(lo) != 0)
+      count++;
+    count += 2;
+  }
+  return count;
+}
 …
                                               Register temp_reg,
                                               Label& wrong_method_type) {
-  if (UseCompressedOops)  unimplemented("coop");  // field accesses must decode
   assert_different_registers(mtype_reg, mh_reg, temp_reg);
   // compare method type against that of the receiver
   RegisterOrConstant mhtype_offset = delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg);
   ld_ptr(mh_reg, mhtype_offset, temp_reg);
+  load_heap_oop(mh_reg, mhtype_offset, temp_reg);
   cmp(temp_reg, mtype_reg);
   br(Assembler::notEqual, false, Assembler::pn, wrong_method_type);
 …
                                                 Register temp_reg) {
   assert_different_registers(vmslots_reg, mh_reg, temp_reg);
-  if (UseCompressedOops)  unimplemented("coop");  // field accesses must decode
   // load mh.type.form.vmslots
   if (java_dyn_MethodHandle::vmslots_offset_in_bytes() != 0) {
     // hoist vmslots into every mh to avoid dependent load chain
     ld(    Address(mh_reg,    delayed_value(java_dyn_MethodHandle::vmslots_offset_in_bytes, temp_reg)),   vmslots_reg);
+    ld(           Address(mh_reg,    delayed_value(java_dyn_MethodHandle::vmslots_offset_in_bytes, temp_reg)),   vmslots_reg);
   } else {
     Register temp2_reg = vmslots_reg;
     ld_ptr(Address(mh_reg,    delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg)),      temp2_reg);
     ld_ptr(Address(temp2_reg, delayed_value(java_dyn_MethodType::form_offset_in_bytes, temp_reg)),        temp2_reg);
     ld(    Address(temp2_reg, delayed_value(java_dyn_MethodTypeForm::vmslots_offset_in_bytes, temp_reg)), vmslots_reg);
+    load_heap_oop(Address(mh_reg,    delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg)),      temp2_reg);
+    load_heap_oop(Address(temp2_reg, delayed_value(java_dyn_MethodType::form_offset_in_bytes, temp_reg)),        temp2_reg);
+    ld(           Address(temp2_reg, delayed_value(java_dyn_MethodTypeForm::vmslots_offset_in_bytes, temp_reg)), vmslots_reg);
+  }
+}
 …
   assert_different_registers(mh_reg, temp_reg);
-  if (UseCompressedOops)  unimplemented("coop");  // field accesses must decode
   // pick out the interpreted side of the handler
+  // NOTE: vmentry is not an oop!
   ld_ptr(mh_reg, delayed_value(java_dyn_MethodHandle::vmentry_offset_in_bytes, temp_reg), temp_reg);
 …
   verify_oop(top);
+  ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t1);
+  sub(top, t1, t1); // size of tlab's allocated portion
+  incr_allocated_bytes(t1, t2, t3);
   // refill the tlab with an eden allocation
   bind(do_refill);
   ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1);
   sll_ptr(t1, LogHeapWordSize, t1);
   // add object_size ??
+  // allocate new tlab, address returned in top
   eden_allocate(top, t1, 0, t2, t3, slow_case);
 …
   br(Assembler::always, false, Assembler::pt, retry);
   delayed()->nop();
+}
+void MacroAssembler::incr_allocated_bytes(RegisterOrConstant size_in_bytes,
+                                          Register t1, Register t2) {
+  // Bump total bytes allocated by this thread
+  assert(t1->is_global(), "must be global reg"); // so all 64 bits are saved on a context switch
+  assert_different_registers(size_in_bytes.register_or_noreg(), t1, t2);
+  // v8 support has gone the way of the dodo
+  ldx(G2_thread, in_bytes(JavaThread::allocated_bytes_offset()), t1);
+  add(t1, ensure_simm13_or_reg(size_in_bytes, t2), t1);
+  stx(t1, G2_thread, in_bytes(JavaThread::allocated_bytes_offset()));
+}
 …
 static void generate_satb_log_enqueue(bool with_frame) {
   BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize);
   CodeBuffer buf(bb->instructions_begin(), bb->instructions_size());
+  CodeBuffer buf(bb);
   MacroAssembler masm(&buf);
   address start = masm.pc();
 …
 static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) {
   BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2);
   CodeBuffer buf(bb->instructions_begin(), bb->instructions_size());
+  CodeBuffer buf(bb);
   MacroAssembler masm(&buf);
   address start = masm.pc();
 …
+}
+void MacroAssembler::load_heap_oop(Register s1, RegisterOrConstant s2, Register d) {
+  if (s2.is_constant())  load_heap_oop(s1, s2.as_constant(), d);
+  else                   load_heap_oop(s1, s2.as_register(), d);
+}
 void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) {
   if (UseCompressedOops) {

trunk/openjdk/hotspot/src/cpu/sparc/vm/assembler_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
+#define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
 class BiasedLockingCounters;
 …
   // test if x is within signed immediate range for nbits
   static bool is_simm(int x, int nbits) { return -( 1 << nbits-1 )  <= x   &&   x  <  ( 1 << nbits-1 ); }
+  static bool is_simm(intptr_t x, int nbits) { return -( intptr_t(1) << nbits-1 )  <= x   &&   x  <  ( intptr_t(1) << nbits-1 ); }
   // test if -4096 <= x <= 4095
+  static bool is_simm13(int x) { return is_simm(x, 13); }
+  static bool is_simm13(intptr_t x) { return is_simm(x, 13); }
+  static bool is_in_wdisp_range(address a, address b, int nbits) {
+    intptr_t d = intptr_t(b) - intptr_t(a);
+    return is_simm(d, nbits + 2);
+  }
+  // test if label is in simm16 range in words (wdisp16).
+  bool is_in_wdisp16_range(Label& L) {
+    return is_in_wdisp_range(target(L), pc(), 16);
+  }
+  // test if the distance between two addresses fits in simm30 range in words
+  static bool is_in_wdisp30_range(address a, address b) {
+    return is_in_wdisp_range(a, b, 30);
+  }
   enum ASIs { // page 72, v9
 …
   inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
   inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
   inline void add(const Address& a, Register d, int offset = 0) { add( a.base(), a.disp() + offset, d, a.rspec(offset)); }
+  inline void add(const Address& a, Register d, int offset = 0);
   void addcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 …
   void sub(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | rs2(s2) ); }
   void sub(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+  // Note: offset is added to s2.
+  inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
   void subcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
   void subcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 …
   inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
   inline void br( Condition c, bool a, Predict p, Label& L );
   inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
   inline void fb( Condition c, bool a, Predict p, Label& L );
 …
   inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
+  // Check if the call target is out of wdisp30 range (relative to the code cache)
+  static inline bool is_far_target(address d);
   inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
   inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
 …
   void patchable_sethi(const AddressLiteral& addrlit, Register d);
   // compute the size of a sethi/set
   static int  size_of_sethi( address a, bool worst_case = false );
   static int  worst_case_size_of_set();
+  // compute the number of instructions for a sethi/set
+  static int  insts_for_sethi( address a, bool worst_case = false );
+  static int  worst_case_insts_for_set();
   // set may be either setsw or setuw (high 32 bits may be zero or sign)
 private:
   void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable);
+  static int insts_for_internal_set(intptr_t value);
 public:
   void set(const AddressLiteral& addrlit, Register d);
   void set(intptr_t value, Register d);
   void set(address addr, Register d, RelocationHolder const& rspec);
+  static int insts_for_set(intptr_t value) { return insts_for_internal_set(value); }
   void patchable_set(const AddressLiteral& addrlit, Register d);
   void patchable_set(intptr_t value, Register d);
   void set64(jlong value, Register d, Register tmp);
+  static int insts_for_set64(jlong value);
   // sign-extend 32 to 64
 …
   void load_heap_oop(Register s1, Register s2, Register d);
   void load_heap_oop(Register s1, int simm13a, Register d);
+  void load_heap_oop(Register s1, RegisterOrConstant s2, Register d);
   void store_heap_oop(Register d, Register s1, Register s2);
   void store_heap_oop(Register d, Register s1, int simm13a);
 …
   void warn(const char* msg);                          // prints msg, but don't stop
   void untested(const char* what = "");
   void unimplemented(const char* what = "")              { char* b = new char[1024];  sprintf(b, "unimplemented: %s", what);  stop(b); }
+  void unimplemented(const char* what = "")      { char* b = new char[1024];  jio_snprintf(b, 1024, "unimplemented: %s", what);  stop(b); }
   void should_not_reach_here()                   { stop("should not reach here"); }
   void print_CPU_state();
 …
   );
   void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
+  void incr_allocated_bytes(RegisterOrConstant size_in_bytes,
+                            Register t1, Register t2);
   // interface method calling
 …
 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
 #endif
+#endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/assembler_sparc.inline.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2009, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP
+#define CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP
+#include "asm/assembler.inline.hpp"
+#include "asm/codeBuffer.hpp"
+#include "code/codeCache.hpp"
+#include "runtime/handles.inline.hpp"
 inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
   jint& stub_inst = *(jint*) branch;
 …
 // form effective addresses this way:
+inline void Assembler::add(const Address& a, Register d, int offset) {
+  if (a.has_index())   add(a.base(), a.index(),         d);
+  else               { add(a.base(), a.disp() + offset, d, a.rspec(offset)); offset = 0; }
+  if (offset != 0)     add(d,        offset,            d);
+}
 inline void Assembler::add(Register s1, RegisterOrConstant s2, Register d, int offset) {
   if (s2.is_register())  add(s1, s2.as_register(),          d);
 …
 inline void Assembler::stdcq(  int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
+inline void Assembler::sub(Register s1, RegisterOrConstant s2, Register d, int offset) {
+  if (s2.is_register())  sub(s1, s2.as_register(),          d);
+  else                 { sub(s1, s2.as_constant() + offset, d); offset = 0; }
+  if (offset != 0)       sub(d,  offset,                    d);
+}
 // pp 231
 …
 inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); }
+inline bool MacroAssembler::is_far_target(address d) {
+  return !is_in_wdisp30_range(d, CodeCache::low_bound()) || !is_in_wdisp30_range(d, CodeCache::high_bound());
+}
 // Call with a check to see if we need to deal with the added
 // expense of relocation and if we overflow the displacement
+// of the quick call instruction./
+// Check to see if we have to deal with relocations
+// of the quick call instruction.
 inline void MacroAssembler::call( address d, relocInfo::relocType rt ) {
 #ifdef _LP64
 …
   // Is this address within range of the call instruction?
   // If not, use the expensive instruction sequence
+  disp = (intptr_t)d - (intptr_t)pc();
+  if ( disp != (intptr_t)(int32_t)disp ) {
+  if (is_far_target(d)) {
     relocate(rt);
     AddressLiteral dest(d);
     jumpl_to(dest, O7, O7);
+  }
+  else {
+    Assembler::call( d, rt );
+  } else {
+    Assembler::call(d, rt);
+  }
 #else
 …
+  }
+}
+#endif // CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/bytecodeInterpreter_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 2007, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "precompiled.hpp"
+#include "asm/assembler.hpp"
+#include "interp_masm_sparc.hpp"
+#include "interpreter/bytecodeInterpreter.hpp"
+#include "interpreter/bytecodeInterpreter.inline.hpp"
+#include "interpreter/interpreter.hpp"
+#include "interpreter/interpreterRuntime.hpp"
+#include "oops/methodDataOop.hpp"
+#include "oops/methodOop.hpp"
+#include "oops/oop.inline.hpp"
+#include "prims/jvmtiExport.hpp"
+#include "prims/jvmtiThreadState.hpp"
+#include "runtime/deoptimization.hpp"
+#include "runtime/frame.inline.hpp"
+#include "runtime/sharedRuntime.hpp"
+#include "runtime/stubRoutines.hpp"
+#include "runtime/synchronizer.hpp"
+#include "runtime/vframeArray.hpp"
+#include "utilities/debug.hpp"
 // KILL THIS FILE

trunk/openjdk/hotspot/src/cpu/sparc/vm/bytecodeInterpreter_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2002, 2008, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_BYTECODEINTERPRETER_SPARC_HPP
+#define CPU_SPARC_VM_BYTECODEINTERPRETER_SPARC_HPP
 // Platform specific for C++ based Interpreter
 …
 #define SET_LOCALS_LONG_FROM_ADDR(addr, offset) (((VMJavaVal64*)&locals[-((offset)+1)])->l = \
                                                 ((VMJavaVal64*)(addr))->l)
+#endif // CPU_SPARC_VM_BYTECODEINTERPRETER_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/bytecodeInterpreter_sparc.inline.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_BYTECODEINTERPRETER_SPARC_INLINE_HPP
+#define CPU_SPARC_VM_BYTECODEINTERPRETER_SPARC_INLINE_HPP
 // Inline interpreter functions for sparc
 …
 };
 #endif /* ALIGN_CONVERTER */
+#endif // CPU_SPARC_VM_BYTECODEINTERPRETER_SPARC_INLINE_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/bytecodes_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 1998, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
 #include "incls/_precompiled.incl"
 #include "incls/_bytecodes_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "interpreter/bytecodes.hpp"

trunk/openjdk/hotspot/src/cpu/sparc/vm/bytecodes_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1998, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_BYTECODES_SPARC_HPP
+#define CPU_SPARC_VM_BYTECODES_SPARC_HPP
 #ifdef SPARC
 #define NLOCALS_IN_REGS 6
 …
 // (none)
+#endif // CPU_SPARC_VM_BYTECODES_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/bytes_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2002, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_BYTES_SPARC_HPP
+#define CPU_SPARC_VM_BYTES_SPARC_HPP
+#include "memory/allocation.hpp"
 class Bytes: AllStatic {
 …
 // 1.17 99/06/22 16:37:35 bytes_i486.hpp
 //End
+#endif // CPU_SPARC_VM_BYTES_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/c1_CodeStubs_sparc.cpp

-              r278
+              r309
  */
+#include "incls/_precompiled.incl"
+#include "incls/_c1_CodeStubs_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "c1/c1_CodeStubs.hpp"
+#include "c1/c1_FrameMap.hpp"
+#include "c1/c1_LIRAssembler.hpp"
+#include "c1/c1_MacroAssembler.hpp"
+#include "c1/c1_Runtime1.hpp"
+#include "nativeInst_sparc.hpp"
+#include "runtime/sharedRuntime.hpp"
+#include "vmreg_sparc.inline.hpp"
+#ifndef SERIALGC
+#include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
+#endif
 #define __ ce->masm()->
 …
   , _index(index)
+{
+  assert(info != NULL, "must have info");
   _info = new CodeEmitInfo(info);
+}
 …
+}
-#ifdef TIERED
 void CounterOverflowStub::emit_code(LIR_Assembler* ce) {
 …
   __ set(_bci, G4);
   __ call(Runtime1::entry_for(Runtime1::counter_overflow_id), relocInfo::runtime_call_type);
   __ delayed()->nop();
+  __ delayed()->mov_or_nop(_method->as_register(), G5);
   ce->add_call_info_here(_info);
   ce->verify_oop_map(_info);
 …
+}
-#endif // TIERED
 void DivByZeroStub::emit_code(LIR_Assembler* ce) {
 …
   Register pre_val_reg = pre_val()->as_register();
+  ce->mem2reg(addr(), pre_val(), T_OBJECT, patch_code(), info(), false);
+  __ br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pt,
+                    pre_val_reg, _continuation);
+  ce->mem2reg(addr(), pre_val(), T_OBJECT, patch_code(), info(), false /*wide*/, false /*unaligned*/);
+  if (__ is_in_wdisp16_range(_continuation)) {
+    __ br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pt,
+                      pre_val_reg, _continuation);
+  } else {
+    __ cmp(pre_val_reg, G0);
+    __ brx(Assembler::equal, false, Assembler::pn, _continuation);
+  }
   __ delayed()->nop();
 …
   Register addr_reg = addr()->as_pointer_register();
   Register new_val_reg = new_val()->as_register();
+  __ br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pt,
+                    new_val_reg, _continuation);
+  if (__ is_in_wdisp16_range(_continuation)) {
+    __ br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pt,
+                      new_val_reg, _continuation);
+  } else {
+    __ cmp(new_val_reg, G0);
+    __ brx(Assembler::equal, false, Assembler::pn, _continuation);
+  }
   __ delayed()->nop();

trunk/openjdk/hotspot/src/cpu/sparc/vm/c1_Defs_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2000, 2009, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_C1_DEFS_SPARC_HPP
+#define CPU_SPARC_VM_C1_DEFS_SPARC_HPP
 // native word offsets from memory address (big endian)
 …
   pd_float_saved_as_double = false
 };
+#endif // CPU_SPARC_VM_C1_DEFS_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/c1_FpuStackSim_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 2005, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "precompiled.hpp"
+#include "c1/c1_FpuStackSim.hpp"
+#include "c1/c1_FrameMap.hpp"
+#include "utilities/array.hpp"
+#include "utilities/ostream.hpp"
 // No FPU stack on SPARC

trunk/openjdk/hotspot/src/cpu/sparc/vm/c1_FpuStackSim_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2005, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_C1_FPUSTACKSIM_SPARC_HPP
+#define CPU_SPARC_VM_C1_FPUSTACKSIM_SPARC_HPP
 // No FPU stack on SPARC
 class FpuStackSim;
+#endif // CPU_SPARC_VM_C1_FPUSTACKSIM_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/c1_FrameMap_sparc.cpp

-              r278
+              r309
  */
+# include "incls/_precompiled.incl"
+# include "incls/_c1_FrameMap_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "c1/c1_FrameMap.hpp"
+#include "c1/c1_LIR.hpp"
+#include "runtime/sharedRuntime.hpp"
+#include "vmreg_sparc.inline.hpp"
 …
 LIR_Opr FrameMap::in_long_opr;
 LIR_Opr FrameMap::out_long_opr;
+LIR_Opr FrameMap::g1_long_single_opr;
 LIR_Opr FrameMap::F0_opr;
 …
   in_long_opr    = as_long_opr(I0);
   out_long_opr   = as_long_opr(O0);
+  g1_long_single_opr    = as_long_single_opr(G1);
   G0_opr = as_opr(G0);

trunk/openjdk/hotspot/src/cpu/sparc/vm/c1_FrameMap_sparc.hpp

-              r278
+              r309
+ *
  */
+#ifndef CPU_SPARC_VM_C1_FRAMEMAP_SPARC_HPP
+#define CPU_SPARC_VM_C1_FRAMEMAP_SPARC_HPP
  public:
 …
   static LIR_Opr in_long_opr;
   static LIR_Opr out_long_opr;
+  static LIR_Opr g1_long_single_opr;
   static LIR_Opr F0_opr;
 …
   static FloatRegister  _fpu_regs [nof_fpu_regs];
+  static LIR_Opr as_long_single_opr(Register r) {
+    return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
+  }
+  static LIR_Opr as_long_pair_opr(Register r) {
+    return LIR_OprFact::double_cpu(cpu_reg2rnr(r->successor()), cpu_reg2rnr(r));
+  }
  public:
 #ifdef _LP64
   static LIR_Opr as_long_opr(Register r) {
     return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
+    return as_long_single_opr(r);
+  }
   static LIR_Opr as_pointer_opr(Register r) {
     return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
+    return as_long_single_opr(r);
+  }
 #else
   static LIR_Opr as_long_opr(Register r) {
     return LIR_OprFact::double_cpu(cpu_reg2rnr(r->successor()), cpu_reg2rnr(r));
+    return as_long_pair_opr(r);
+  }
   static LIR_Opr as_pointer_opr(Register r) {
 …
   static bool is_caller_save_register (LIR_Opr  reg);
   static bool is_caller_save_register (Register r);
+  static int nof_caller_save_cpu_regs() { return pd_nof_caller_save_cpu_regs_frame_map; }
+  static int last_cpu_reg()             { return pd_last_cpu_reg;  }
+#endif // CPU_SPARC_VM_C1_FRAMEMAP_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+# include "incls/_precompiled.incl"
+# include "incls/_c1_LIRAssembler_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "c1/c1_Compilation.hpp"
+#include "c1/c1_LIRAssembler.hpp"
+#include "c1/c1_MacroAssembler.hpp"
+#include "c1/c1_Runtime1.hpp"
+#include "c1/c1_ValueStack.hpp"
+#include "ci/ciArrayKlass.hpp"
+#include "ci/ciInstance.hpp"
+#include "gc_interface/collectedHeap.hpp"
+#include "memory/barrierSet.hpp"
+#include "memory/cardTableModRefBS.hpp"
+#include "nativeInst_sparc.hpp"
+#include "oops/objArrayKlass.hpp"
+#include "runtime/sharedRuntime.hpp"
 #define __ _masm->
 …
           ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
         return false;
+      }
+      if (UseCompressedOops) {
+        if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;
+        if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
+      }
 …
     int  count_offset = java_lang_String:: count_offset_in_bytes();
     __ ld_ptr(str0, value_offset, tmp0);
+    __ load_heap_oop(str0, value_offset, tmp0);
     __ ld(str0, offset_offset, tmp2);
     __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
 …
     add_debug_info_for_null_check_here(info);
     __ ld_ptr(str1, value_offset, tmp1);
+    __ load_heap_oop(str1, value_offset, tmp1);
     __ add(tmp0, tmp2, tmp0);
 …
 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
   add_debug_info_for_null_check_here(op->info());
   __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
+  __ load_klass(O0, G3_scratch);
   if (__ is_simm13(op->vtable_offset())) {
     __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
 …
+}
+// load with 32-bit displacement
+int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
+  int load_offset = code_offset();
+  if (Assembler::is_simm13(disp)) {
+    if (info != NULL) add_debug_info_for_null_check_here(info);
+    switch(ld_type) {
+      case T_BOOLEAN: // fall through
+      case T_BYTE  : __ ldsb(s, disp, d); break;
+      case T_CHAR  : __ lduh(s, disp, d); break;
+      case T_SHORT : __ ldsh(s, disp, d); break;
+      case T_INT   : __ ld(s, disp, d); break;
+      case T_ADDRESS:// fall through
+      case T_ARRAY : // fall through
+      case T_OBJECT: __ ld_ptr(s, disp, d); break;
+      default      : ShouldNotReachHere();
+    }
+  } else {
+    __ set(disp, O7);
+    if (info != NULL) add_debug_info_for_null_check_here(info);
+    load_offset = code_offset();
+    switch(ld_type) {
+      case T_BOOLEAN: // fall through
+      case T_BYTE  : __ ldsb(s, O7, d); break;
+      case T_CHAR  : __ lduh(s, O7, d); break;
+      case T_SHORT : __ ldsh(s, O7, d); break;
+      case T_INT   : __ ld(s, O7, d); break;
+      case T_ADDRESS:// fall through
+      case T_ARRAY : // fall through
+      case T_OBJECT: __ ld_ptr(s, O7, d); break;
+      default      : ShouldNotReachHere();
+    }
+  }
+  if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d);
+  return load_offset;
+}
+// store with 32-bit displacement
+void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
+  if (Assembler::is_simm13(offset)) {
+    if (info != NULL)  add_debug_info_for_null_check_here(info);
+    switch (type) {
+      case T_BOOLEAN: // fall through
+      case T_BYTE  : __ stb(value, base, offset); break;
+      case T_CHAR  : __ sth(value, base, offset); break;
+      case T_SHORT : __ sth(value, base, offset); break;
+      case T_INT   : __ stw(value, base, offset); break;
+      case T_ADDRESS:// fall through
+      case T_ARRAY : // fall through
+      case T_OBJECT: __ st_ptr(value, base, offset); break;
+      default      : ShouldNotReachHere();
+    }
+  } else {
+    __ set(offset, O7);
+    if (info != NULL) add_debug_info_for_null_check_here(info);
+    switch (type) {
+      case T_BOOLEAN: // fall through
+      case T_BYTE  : __ stb(value, base, O7); break;
+      case T_CHAR  : __ sth(value, base, O7); break;
+      case T_SHORT : __ sth(value, base, O7); break;
+      case T_INT   : __ stw(value, base, O7); break;
+      case T_ADDRESS:// fall through
+      case T_ARRAY : //fall through
+      case T_OBJECT: __ st_ptr(value, base, O7); break;
+      default      : ShouldNotReachHere();
+    }
+  }
+  // Note: Do the store before verification as the code might be patched!
+  if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value);
+}
+// load float with 32-bit displacement
+void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
+  FloatRegisterImpl::Width w;
+  switch(ld_type) {
+    case T_FLOAT : w = FloatRegisterImpl::S; break;
+    case T_DOUBLE: w = FloatRegisterImpl::D; break;
+    default      : ShouldNotReachHere();
+  }
+  if (Assembler::is_simm13(disp)) {
+    if (info != NULL) add_debug_info_for_null_check_here(info);
+    if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) {
+      __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor());
+      __ ldf(FloatRegisterImpl::S, s, disp               , d);
+    } else {
+      __ ldf(w, s, disp, d);
+    }
+  } else {
+    __ set(disp, O7);
+    if (info != NULL) add_debug_info_for_null_check_here(info);
+    __ ldf(w, s, O7, d);
+  }
+}
+// store float with 32-bit displacement
+void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
+  FloatRegisterImpl::Width w;
+  switch(type) {
+    case T_FLOAT : w = FloatRegisterImpl::S; break;
+    case T_DOUBLE: w = FloatRegisterImpl::D; break;
+    default      : ShouldNotReachHere();
+  }
+  if (Assembler::is_simm13(offset)) {
+    if (info != NULL) add_debug_info_for_null_check_here(info);
+    if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) {
+      __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord);
+      __ stf(FloatRegisterImpl::S, value             , base, offset);
+    } else {
+      __ stf(w, value, base, offset);
+    }
+  } else {
+    __ set(offset, O7);
+    if (info != NULL) add_debug_info_for_null_check_here(info);
+    __ stf(w, value, O7, base);
+  }
+}
+int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) {
+int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
   int store_offset;
   if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
 …
     // for offsets larger than a simm13 we setup the offset in O7
     __ set(offset, O7);
+    store_offset = store(from_reg, base, O7, type);
+  } else {
+    if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
+    store_offset = store(from_reg, base, O7, type, wide);
+  } else {
+    if (type == T_ARRAY || type == T_OBJECT) {
+      __ verify_oop(from_reg->as_register());
+    }
     store_offset = code_offset();
     switch (type) {
 …
 #endif
         break;
+      case T_ADDRESS:// fall through
+      case T_ADDRESS:
+        __ st_ptr(from_reg->as_register(), base, offset);
+        break;
       case T_ARRAY : // fall through
+      case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break;
+      case T_OBJECT:
+        {
+          if (UseCompressedOops && !wide) {
+            __ encode_heap_oop(from_reg->as_register(), G3_scratch);
+            store_offset = code_offset();
+            __ stw(G3_scratch, base, offset);
+          } else {
+            __ st_ptr(from_reg->as_register(), base, offset);
+          }
+          break;
+        }
       case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
       case T_DOUBLE:
 …
+int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) {
+  if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
+int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
+  if (type == T_ARRAY || type == T_OBJECT) {
+    __ verify_oop(from_reg->as_register());
+  }
   int store_offset = code_offset();
   switch (type) {
 …
 #endif
       break;
+    case T_ADDRESS:// fall through
+    case T_ADDRESS:
+      __ st_ptr(from_reg->as_register(), base, disp);
+      break;
     case T_ARRAY : // fall through
+    case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break;
+    case T_OBJECT:
+      {
+        if (UseCompressedOops && !wide) {
+          __ encode_heap_oop(from_reg->as_register(), G3_scratch);
+          store_offset = code_offset();
+          __ stw(G3_scratch, base, disp);
+        } else {
+          __ st_ptr(from_reg->as_register(), base, disp);
+        }
+        break;
+      }
     case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
     case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
 …
 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) {
+int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
   int load_offset;
   if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
 …
     // for offsets larger than a simm13 we setup the offset in O7
     __ set(offset, O7);
     load_offset = load(base, O7, to_reg, type);
+    load_offset = load(base, O7, to_reg, type, wide);
   } else {
     load_offset = code_offset();
 …
+        }
         break;
       case T_ADDRESS:// fall through
+      case T_ADDRESS:  __ ld_ptr(base, offset, to_reg->as_register()); break;
       case T_ARRAY : // fall through
+      case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break;
+      case T_OBJECT:
+        {
+          if (UseCompressedOops && !wide) {
+            __ lduw(base, offset, to_reg->as_register());
+            __ decode_heap_oop(to_reg->as_register());
+          } else {
+            __ ld_ptr(base, offset, to_reg->as_register());
+          }
+          break;
+        }
       case T_FLOAT:  __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
       case T_DOUBLE:
 …
       default      : ShouldNotReachHere();
+    }
+    if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
+    if (type == T_ARRAY || type == T_OBJECT) {
+      __ verify_oop(to_reg->as_register());
+    }
+  }
   return load_offset;
 …
 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) {
+int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
   int load_offset = code_offset();
   switch(type) {
     case T_BOOLEAN: // fall through
     case T_BYTE  : __ ldsb(base, disp, to_reg->as_register()); break;
     case T_CHAR  : __ lduh(base, disp, to_reg->as_register()); break;
     case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
     case T_INT   : __ ld(base, disp, to_reg->as_register()); break;
     case T_ADDRESS:// fall through
+    case T_BYTE  :  __ ldsb(base, disp, to_reg->as_register()); break;
+    case T_CHAR  :  __ lduh(base, disp, to_reg->as_register()); break;
+    case T_SHORT :  __ ldsh(base, disp, to_reg->as_register()); break;
+    case T_INT   :  __ ld(base, disp, to_reg->as_register()); break;
+    case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
     case T_ARRAY : // fall through
+    case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break;
+    case T_OBJECT:
+      {
+          if (UseCompressedOops && !wide) {
+            __ lduw(base, disp, to_reg->as_register());
+            __ decode_heap_oop(to_reg->as_register());
+          } else {
+            __ ld_ptr(base, disp, to_reg->as_register());
+          }
+          break;
+      }
     case T_FLOAT:  __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
     case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
 …
     default      : ShouldNotReachHere();
+  }
+  if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
+  if (type == T_ARRAY || type == T_OBJECT) {
+    __ verify_oop(to_reg->as_register());
+  }
   return load_offset;
+}
-// load/store with an Address
-void LIR_Assembler::load(const Address& a, Register d,  BasicType ld_type, CodeEmitInfo *info, int offset) {
-  load(a.base(), a.disp() + offset, d, ld_type, info);
+}
-void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
-  store(value, dest.base(), dest.disp() + offset, type, info);
+}
-// loadf/storef with an Address
-void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) {
-  load(a.base(), a.disp() + offset, d, ld_type, info);
+}
-void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
-  store(value, dest.base(), dest.disp() + offset, type, info);
+}
-// load/store with an Address
-void LIR_Assembler::load(LIR_Address* a, Register d,  BasicType ld_type, CodeEmitInfo *info) {
-  load(as_Address(a), d, ld_type, info);
+}
-void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
-  store(value, as_Address(dest), type, info);
+}
-// loadf/storef with an Address
-void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
-  load(as_Address(a), d, ld_type, info);
+}
-void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
-  store(value, as_Address(dest), type, info);
+}
 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 …
   switch (c->type()) {
     case T_INT:
+    case T_FLOAT:
+    case T_FLOAT: {
+      Register src_reg = O7;
+      int value = c->as_jint_bits();
+      if (value == 0) {
+        src_reg = G0;
+      } else {
+        __ set(value, O7);
+      }
+      Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
+      __ stw(src_reg, addr.base(), addr.disp());
+      break;
+    }
     case T_ADDRESS: {
       Register src_reg = O7;
 …
+      }
       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
       __ stw(src_reg, addr.base(), addr.disp());
+      __ st_ptr(src_reg, addr.base(), addr.disp());
       break;
+    }
 …
 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
+void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
   LIR_Const* c = src->as_constant_ptr();
   LIR_Address* addr     = dest->as_address_ptr();
   Register base = addr->base()->as_pointer_register();
+  if (info != NULL) {
+    add_debug_info_for_null_check_here(info);
+  }
+  int offset = -1;
   switch (c->type()) {
     case T_INT:
 …
       if (addr->index()->is_valid()) {
         assert(addr->disp() == 0, "must be zero");
         store(tmp, base, addr->index()->as_pointer_register(), type);
+        offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
       } else {
         assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
         store(tmp, base, addr->disp(), type);
+        offset = store(tmp, base, addr->disp(), type, wide, false);
+      }
       break;
 …
              Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
       Register tmp = O7;
+      LIR_Opr tmp = FrameMap::O7_opr;
       int value_lo = c->as_jint_lo_bits();
       if (value_lo == 0) {
         tmp = G0;
+        tmp = FrameMap::G0_opr;
       } else {
         __ set(value_lo, O7);
+      }
       store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT);
+      offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);
       int value_hi = c->as_jint_hi_bits();
       if (value_hi == 0) {
         tmp = G0;
+        tmp = FrameMap::G0_opr;
       } else {
         __ set(value_hi, O7);
+      }
       store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT);
+      offset = store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);
       break;
+    }
 …
       if (addr->index()->is_valid()) {
         assert(addr->disp() == 0, "must be zero");
         store(tmp, base, addr->index()->as_pointer_register(), type);
+        offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
       } else {
         assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
         store(tmp, base, addr->disp(), type);
+        offset = store(tmp, base, addr->disp(), type, wide, false);
+      }
 …
     default:
       Unimplemented();
+  }
+  if (info != NULL) {
+    assert(offset != -1, "offset should've been set");
+    add_debug_info_for_null_check(offset, info);
+  }
+}
 …
           __ set(const_addrlit, O7);
           load(O7, 0, to_reg->as_register(), T_INT);
+          __ ld(O7, 0, to_reg->as_register());
+        }
+      }
 …
 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) {
+                            LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
   LIR_Address* addr = src_opr->as_address_ptr();
 …
   assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
   if (disp_reg == noreg) {
     offset = load(src, disp_value, to_reg, type, unaligned);
+    offset = load(src, disp_value, to_reg, type, wide, unaligned);
   } else {
     assert(!unaligned, "can't handle this");
     offset = load(src, disp_reg, to_reg, type);
+    offset = load(src, disp_reg, to_reg, type, wide);
+  }
 …
     patching_epilog(patch, patch_code, src, info);
+  }
   if (info != NULL) add_debug_info_for_null_check(offset, info);
+}
 …
   bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
   load(addr.base(), addr.disp(), dest, dest->type(), unaligned);
+  load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
+}
 …
+  }
   bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
   store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned);
+  store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
+}
 …
 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
                             bool unaligned) {
+                            bool wide, bool unaligned) {
   LIR_Address* addr = dest->as_address_ptr();
 …
   assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
   if (disp_reg == noreg) {
     offset = store(from_reg, src, disp_value, type, unaligned);
+    offset = store(from_reg, src, disp_value, type, wide, unaligned);
   } else {
     assert(!unaligned, "can't handle this");
     offset = store(from_reg, src, disp_reg, type);
+    offset = store(from_reg, src, disp_reg, type, wide);
+  }
 …
 void LIR_Assembler::return_op(LIR_Opr result) {
   // the poll may need a register so just pick one that isn't the return register
 #ifdef TIERED
+#if defined(TIERED) && !defined(_LP64)
   if (result->type_field() == LIR_OprDesc::long_type) {
     // Must move the result to G1
 …
     __ srl (I1, 0, I1);           // Zero extend O1 (harmless?)
     __ or3 (I1, G1, G1);          // OR 64 bits into G1
+#ifdef ASSERT
+    // mangle it so any problems will show up
+    __ set(0xdeadbeef, I0);
+    __ set(0xdeadbeef, I1);
+#endif
+  }
 #endif // TIERED
 …
+void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
+void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
   Assembler::Condition acond;
   switch (condition) {
 …
+  }
   Label skip;
+  __ br(acond, false, Assembler::pt, skip);
+#ifdef _LP64
+    if  (type == T_INT) {
+      __ br(acond, false, Assembler::pt, skip);
+    } else
+#endif
+      __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
   if (opr1->is_constant() && opr1->type() == T_INT) {
     Register dest = result->as_register();
 …
   if (flags & LIR_OpArrayCopy::src_null_check) {
     __ tst(src);
     __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
+    __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
     __ delayed()->nop();
+  }
 …
   if (flags & LIR_OpArrayCopy::dst_null_check) {
     __ tst(dst);
     __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
+    __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
     __ delayed()->nop();
+  }
 …
   if (flags & LIR_OpArrayCopy::type_check) {
+    __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
+    __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
+    __ cmp(tmp, tmp2);
+    __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
+    if (UseCompressedOops) {
+      // We don't need decode because we just need to compare
+      __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
+      __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
+      __ cmp(tmp, tmp2);
+      __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
+    } else {
+      __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
+      __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
+      __ cmp(tmp, tmp2);
+      __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry());
+    }
     __ delayed()->nop();
+  }
 …
     Label known_ok, halt;
     jobject2reg(op->expected_type()->constant_encoding(), tmp);
+    __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
+    if (basic_type != T_OBJECT) {
+      __ cmp(tmp, tmp2);
+      __ br(Assembler::notEqual, false, Assembler::pn, halt);
+      __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
+      __ cmp(tmp, tmp2);
+      __ br(Assembler::equal, false, Assembler::pn, known_ok);
+      __ delayed()->nop();
+    if (UseCompressedOops) {
+      // tmp holds the default type. It currently comes uncompressed after the
+      // load of a constant, so encode it.
+      __ encode_heap_oop(tmp);
+      // load the raw value of the dst klass, since we will be comparing
+      // uncompressed values directly.
+      __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
+      if (basic_type != T_OBJECT) {
+        __ cmp(tmp, tmp2);
+        __ br(Assembler::notEqual, false, Assembler::pn, halt);
+        // load the raw value of the src klass.
+        __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
+        __ cmp(tmp, tmp2);
+        __ br(Assembler::equal, false, Assembler::pn, known_ok);
+        __ delayed()->nop();
+      } else {
+        __ cmp(tmp, tmp2);
+        __ br(Assembler::equal, false, Assembler::pn, known_ok);
+        __ delayed()->cmp(src, dst);
+        __ brx(Assembler::equal, false, Assembler::pn, known_ok);
+        __ delayed()->nop();
+      }
     } else {
+      __ cmp(tmp, tmp2);
+      __ br(Assembler::equal, false, Assembler::pn, known_ok);
+      __ delayed()->cmp(src, dst);
+      __ br(Assembler::equal, false, Assembler::pn, known_ok);
+      __ delayed()->nop();
+      __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
+      if (basic_type != T_OBJECT) {
+        __ cmp(tmp, tmp2);
+        __ brx(Assembler::notEqual, false, Assembler::pn, halt);
+        __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
+        __ cmp(tmp, tmp2);
+        __ brx(Assembler::equal, false, Assembler::pn, known_ok);
+        __ delayed()->nop();
+      } else {
+        __ cmp(tmp, tmp2);
+        __ brx(Assembler::equal, false, Assembler::pn, known_ok);
+        __ delayed()->cmp(src, dst);
+        __ brx(Assembler::equal, false, Assembler::pn, known_ok);
+        __ delayed()->nop();
+      }
+    }
     __ bind(halt);
 …
          op->tmp4()->as_register()  == O1 &&
          op->klass()->as_register() == G5, "must be");
+  LP64_ONLY( __ signx(op->len()->as_register()); )
   if (UseSlowPath ||
       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
 …
+void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
+                                        ciMethodData *md, ciProfileData *data,
+                                        Register recv, Register tmp1, Label* update_done) {
+  uint i;
+  for (i = 0; i < VirtualCallData::row_limit(); i++) {
+    Label next_test;
+    // See if the receiver is receiver[n].
+    Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
+                          mdo_offset_bias);
+    __ ld_ptr(receiver_addr, tmp1);
+    __ verify_oop(tmp1);
+    __ cmp(recv, tmp1);
+    __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
+    __ delayed()->nop();
+    Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
+                      mdo_offset_bias);
+    __ ld_ptr(data_addr, tmp1);
+    __ add(tmp1, DataLayout::counter_increment, tmp1);
+    __ st_ptr(tmp1, data_addr);
+    __ ba(false, *update_done);
+    __ delayed()->nop();
+    __ bind(next_test);
+  }
+  // Didn't find receiver; find next empty slot and fill it in
+  for (i = 0; i < VirtualCallData::row_limit(); i++) {
+    Label next_test;
+    Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
+                      mdo_offset_bias);
+    __ ld_ptr(recv_addr, tmp1);
+    __ br_notnull(tmp1, false, Assembler::pt, next_test);
+    __ delayed()->nop();
+    __ st_ptr(recv, recv_addr);
+    __ set(DataLayout::counter_increment, tmp1);
+    __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
+              mdo_offset_bias);
+    __ ba(false, *update_done);
+    __ delayed()->nop();
+    __ bind(next_test);
+  }
+}
+void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
+                                    ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
+  md = method->method_data_or_null();
+  assert(md != NULL, "Sanity");
+  data = md->bci_to_data(bci);
+  assert(data != NULL,       "need data for checkcast");
+  assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
+  if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
+    // The offset is large so bias the mdo by the base of the slot so
+    // that the ld can use simm13s to reference the slots of the data
+    mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
+  }
+}
+void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
+  // we always need a stub for the failure case.
+  CodeStub* stub = op->stub();
+  Register obj = op->object()->as_register();
+  Register k_RInfo = op->tmp1()->as_register();
+  Register klass_RInfo = op->tmp2()->as_register();
+  Register dst = op->result_opr()->as_register();
+  Register Rtmp1 = op->tmp3()->as_register();
+  ciKlass* k = op->klass();
+  if (obj == k_RInfo) {
+    k_RInfo = klass_RInfo;
+    klass_RInfo = obj;
+  }
+  ciMethodData* md;
+  ciProfileData* data;
+  int mdo_offset_bias = 0;
+  if (op->should_profile()) {
+    ciMethod* method = op->profiled_method();
+    assert(method != NULL, "Should have method");
+    setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
+    Label not_null;
+    __ br_notnull(obj, false, Assembler::pn, not_null);
+    __ delayed()->nop();
+    Register mdo      = k_RInfo;
+    Register data_val = Rtmp1;
+    jobject2reg(md->constant_encoding(), mdo);
+    if (mdo_offset_bias > 0) {
+      __ set(mdo_offset_bias, data_val);
+      __ add(mdo, data_val, mdo);
+    }
+    Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
+    __ ldub(flags_addr, data_val);
+    __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
+    __ stb(data_val, flags_addr);
+    __ ba(false, *obj_is_null);
+    __ delayed()->nop();
+    __ bind(not_null);
+  } else {
+    __ br_null(obj, false, Assembler::pn, *obj_is_null);
+    __ delayed()->nop();
+  }
+  Label profile_cast_failure, profile_cast_success;
+  Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
+  Label *success_target = op->should_profile() ? &profile_cast_success : success;
+  // patching may screw with our temporaries on sparc,
+  // so let's do it before loading the class
+  if (k->is_loaded()) {
+    jobject2reg(k->constant_encoding(), k_RInfo);
+  } else {
+    jobject2reg_with_patching(k_RInfo, op->info_for_patch());
+  }
+  assert(obj != k_RInfo, "must be different");
+  // get object class
+  // not a safepoint as obj null check happens earlier
+  __ load_klass(obj, klass_RInfo);
+  if (op->fast_check()) {
+    assert_different_registers(klass_RInfo, k_RInfo);
+    __ cmp(k_RInfo, klass_RInfo);
+    __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
+    __ delayed()->nop();
+  } else {
+    bool need_slow_path = true;
+    if (k->is_loaded()) {
+      if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
+        need_slow_path = false;
+      // perform the fast part of the checking logic
+      __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
+                                       (need_slow_path ? success_target : NULL),
+                                       failure_target, NULL,
+                                       RegisterOrConstant(k->super_check_offset()));
+    } else {
+      // perform the fast part of the checking logic
+      __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
+                                       failure_target, NULL);
+    }
+    if (need_slow_path) {
+      // call out-of-line instance of __ check_klass_subtype_slow_path(...):
+      assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
+      __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
+      __ delayed()->nop();
+      __ cmp(G3, 0);
+      __ br(Assembler::equal, false, Assembler::pn, *failure_target);
+      __ delayed()->nop();
+      // Fall through to success case
+    }
+  }
+  if (op->should_profile()) {
+    Register mdo  = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
+    assert_different_registers(obj, mdo, recv, tmp1);
+    __ bind(profile_cast_success);
+    jobject2reg(md->constant_encoding(), mdo);
+    if (mdo_offset_bias > 0) {
+      __ set(mdo_offset_bias, tmp1);
+      __ add(mdo, tmp1, mdo);
+    }
+    __ load_klass(obj, recv);
+    type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
+    // Jump over the failure case
+    __ ba(false, *success);
+    __ delayed()->nop();
+    // Cast failure case
+    __ bind(profile_cast_failure);
+    jobject2reg(md->constant_encoding(), mdo);
+    if (mdo_offset_bias > 0) {
+      __ set(mdo_offset_bias, tmp1);
+      __ add(mdo, tmp1, mdo);
+    }
+    Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
+    __ ld_ptr(data_addr, tmp1);
+    __ sub(tmp1, DataLayout::counter_increment, tmp1);
+    __ st_ptr(tmp1, data_addr);
+    __ ba(false, *failure);
+    __ delayed()->nop();
+  }
+  __ ba(false, *success);
+  __ delayed()->nop();
+}
 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
   LIR_Code code = op->code();
 …
     __ verify_oop(value);
     CodeStub* stub = op->stub();
+    Label done;
+    __ cmp(value, 0);
+    __ br(Assembler::equal, false, Assembler::pn, done);
+    __ delayed()->nop();
+    load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception());
+    load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
+    // check if it needs to be profiled
+    ciMethodData* md;
+    ciProfileData* data;
+    int mdo_offset_bias = 0;
+    if (op->should_profile()) {
+      ciMethod* method = op->profiled_method();
+      assert(method != NULL, "Should have method");
+      setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
+    }
+    Label profile_cast_success, profile_cast_failure, done;
+    Label *success_target = op->should_profile() ? &profile_cast_success : &done;
+    Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
+    if (op->should_profile()) {
+      Label not_null;
+      __ br_notnull(value, false, Assembler::pn, not_null);
+      __ delayed()->nop();
+      Register mdo      = k_RInfo;
+      Register data_val = Rtmp1;
+      jobject2reg(md->constant_encoding(), mdo);
+      if (mdo_offset_bias > 0) {
+        __ set(mdo_offset_bias, data_val);
+        __ add(mdo, data_val, mdo);
+      }
+      Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
+      __ ldub(flags_addr, data_val);
+      __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
+      __ stb(data_val, flags_addr);
+      __ ba(false, done);
+      __ delayed()->nop();
+      __ bind(not_null);
+    } else {
+      __ br_null(value, false, Assembler::pn, done);
+      __ delayed()->nop();
+    }
+    add_debug_info_for_null_check_here(op->info_for_exception());
+    __ load_klass(array, k_RInfo);
+    __ load_klass(value, klass_RInfo);
     // get instance klass
     load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL);
+    __ ld_ptr(Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)), k_RInfo);
     // perform the fast part of the checking logic
     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, &done, stub->entry(), NULL);
+    __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
 …
     __ delayed()->nop();
     __ cmp(G3, 0);
     __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
+    __ br(Assembler::equal, false, Assembler::pn, *failure_target);
     __ delayed()->nop();
+    // fall through to the success case
+    if (op->should_profile()) {
+      Register mdo  = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
+      assert_different_registers(value, mdo, recv, tmp1);
+      __ bind(profile_cast_success);
+      jobject2reg(md->constant_encoding(), mdo);
+      if (mdo_offset_bias > 0) {
+        __ set(mdo_offset_bias, tmp1);
+        __ add(mdo, tmp1, mdo);
+      }
+      __ load_klass(value, recv);
+      type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
+      __ ba(false, done);
+      __ delayed()->nop();
+      // Cast failure case
+      __ bind(profile_cast_failure);
+      jobject2reg(md->constant_encoding(), mdo);
+      if (mdo_offset_bias > 0) {
+        __ set(mdo_offset_bias, tmp1);
+        __ add(mdo, tmp1, mdo);
+      }
+      Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
+      __ ld_ptr(data_addr, tmp1);
+      __ sub(tmp1, DataLayout::counter_increment, tmp1);
+      __ st_ptr(tmp1, data_addr);
+      __ ba(false, *stub->entry());
+      __ delayed()->nop();
+    }
     __ bind(done);
+  } else if (op->code() == lir_checkcast) {
+    // we always need a stub for the failure case.
+    CodeStub* stub = op->stub();
+  } else if (code == lir_checkcast) {
     Register obj = op->object()->as_register();
-    Register k_RInfo = op->tmp1()->as_register();
-    Register klass_RInfo = op->tmp2()->as_register();
     Register dst = op->result_opr()->as_register();
+    Register Rtmp1 = op->tmp3()->as_register();
+    ciKlass* k = op->klass();
+    if (obj == k_RInfo) {
+      k_RInfo = klass_RInfo;
+      klass_RInfo = obj;
+    }
+    if (op->profiled_method() != NULL) {
+      ciMethod* method = op->profiled_method();
+      int bci          = op->profiled_bci();
+      // We need two temporaries to perform this operation on SPARC,
+      // so to keep things simple we perform a redundant test here
+      Label profile_done;
+      __ cmp(obj, 0);
+      __ br(Assembler::notEqual, false, Assembler::pn, profile_done);
+      __ delayed()->nop();
+      // Object is null; update methodDataOop
+      ciMethodData* md = method->method_data();
+      if (md == NULL) {
+        bailout("out of memory building methodDataOop");
+        return;
+      }
+      ciProfileData* data = md->bci_to_data(bci);
+      assert(data != NULL,       "need data for checkcast");
+      assert(data->is_BitData(), "need BitData for checkcast");
+      Register mdo      = k_RInfo;
+      Register data_val = Rtmp1;
+      jobject2reg(md->constant_encoding(), mdo);
+      int mdo_offset_bias = 0;
+      if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
+        // The offset is large so bias the mdo by the base of the slot so
+        // that the ld can use simm13s to reference the slots of the data
+        mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
+        __ set(mdo_offset_bias, data_val);
+        __ add(mdo, data_val, mdo);
+      }
+      Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
+      __ ldub(flags_addr, data_val);
+      __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
+      __ stb(data_val, flags_addr);
+      __ bind(profile_done);
+    }
+    Label done;
+    // patching may screw with our temporaries on sparc,
+    // so let's do it before loading the class
+    if (k->is_loaded()) {
+      jobject2reg(k->constant_encoding(), k_RInfo);
+    } else {
+      jobject2reg_with_patching(k_RInfo, op->info_for_patch());
+    }
+    assert(obj != k_RInfo, "must be different");
+    __ cmp(obj, 0);
+    __ br(Assembler::equal, false, Assembler::pn, done);
+    __ delayed()->nop();
+    // get object class
+    // not a safepoint as obj null check happens earlier
+    load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
+    if (op->fast_check()) {
+      assert_different_registers(klass_RInfo, k_RInfo);
+      __ cmp(k_RInfo, klass_RInfo);
+      __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
+      __ delayed()->nop();
+      __ bind(done);
+    } else {
+      bool need_slow_path = true;
+      if (k->is_loaded()) {
+        if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
+          need_slow_path = false;
+        // perform the fast part of the checking logic
+        __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
+                                         (need_slow_path ? &done : NULL),
+                                         stub->entry(), NULL,
+                                         RegisterOrConstant(k->super_check_offset()));
+      } else {
+        // perform the fast part of the checking logic
+        __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7,
+                                         &done, stub->entry(), NULL);
+      }
+      if (need_slow_path) {
+        // call out-of-line instance of __ check_klass_subtype_slow_path(...):
+        assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
+        __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
+        __ delayed()->nop();
+        __ cmp(G3, 0);
+        __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
+        __ delayed()->nop();
+      }
+      __ bind(done);
+    }
+    Label success;
+    emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
+    __ bind(success);
     __ mov(obj, dst);
   } else if (code == lir_instanceof) {
     Register obj = op->object()->as_register();
-    Register k_RInfo = op->tmp1()->as_register();
-    Register klass_RInfo = op->tmp2()->as_register();
     Register dst = op->result_opr()->as_register();
+    Register Rtmp1 = op->tmp3()->as_register();
+    ciKlass* k = op->klass();
+    Label done;
+    if (obj == k_RInfo) {
+      k_RInfo = klass_RInfo;
+      klass_RInfo = obj;
+    }
+    // patching may screw with our temporaries on sparc,
+    // so let's do it before loading the class
+    if (k->is_loaded()) {
+      jobject2reg(k->constant_encoding(), k_RInfo);
+    } else {
+      jobject2reg_with_patching(k_RInfo, op->info_for_patch());
+    }
+    assert(obj != k_RInfo, "must be different");
+    __ cmp(obj, 0);
+    __ br(Assembler::equal, true, Assembler::pn, done);
+    __ delayed()->set(0, dst);
+    // get object class
+    // not a safepoint as obj null check happens earlier
+    load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
+    if (op->fast_check()) {
+      __ cmp(k_RInfo, klass_RInfo);
+      __ br(Assembler::equal, true, Assembler::pt, done);
+      __ delayed()->set(1, dst);
+      __ set(0, dst);
+      __ bind(done);
+    } else {
+      bool need_slow_path = true;
+      if (k->is_loaded()) {
+        if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
+          need_slow_path = false;
+        // perform the fast part of the checking logic
+        __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, noreg,
+                                         (need_slow_path ? &done : NULL),
+                                         (need_slow_path ? &done : NULL), NULL,
+                                         RegisterOrConstant(k->super_check_offset()),
+                                         dst);
+      } else {
+        assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers");
+        // perform the fast part of the checking logic
+        __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, dst,
+                                         &done, &done, NULL,
+                                         RegisterOrConstant(-1),
+                                         dst);
+      }
+      if (need_slow_path) {
+        // call out-of-line instance of __ check_klass_subtype_slow_path(...):
+        assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
+        __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
+        __ delayed()->nop();
+        __ mov(G3, dst);
+      }
+      __ bind(done);
+    }
+    Label success, failure, done;
+    emit_typecheck_helper(op, &success, &failure, &failure);
+    __ bind(failure);
+    __ set(0, dst);
+    __ ba(false, done);
+    __ delayed()->nop();
+    __ bind(success);
+    __ set(1, dst);
+    __ bind(done);
   } else {
     ShouldNotReachHere();
 …
     __ mov(cmp_value_lo, t1);
     __ mov(new_value_lo, t2);
+    // perform the compare and swap operation
+    __ casx(addr, t1, t2);
+    // generate condition code - if the swap succeeded, t2 ("new value" reg) was
+    // overwritten with the original value in "addr" and will be equal to t1.
+    __ cmp(t1, t2);
 #else
     // move high and low halves of long values into single registers
 …
     __ srl(new_value_lo, 0, new_value_lo);
     __ or3(t2, new_value_lo, t2);          // t2 holds 64-bit value to swap
-#endif
     // perform the compare and swap operation
     __ casx(addr, t1, t2);
     // generate condition code - if the swap succeeded, t2 ("new value" reg) was
     // overwritten with the original value in "addr" and will be equal to t1.
+    __ cmp(t1, t2);
+    // Produce icc flag for 32bit.
+    __ sub(t1, t2, t2);
+    __ srlx(t2, 32, t1);
+    __ orcc(t2, t1, G0);
+#endif
   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
     Register addr = op->addr()->as_pointer_register();
 …
     __ mov(cmp_value, t1);
     __ mov(new_value, t2);
-#ifdef _LP64
     if (op->code() == lir_cas_obj) {
+      __ casx(addr, t1, t2);
+    } else
+#endif
+      {
+      if (UseCompressedOops) {
+        __ encode_heap_oop(t1);
+        __ encode_heap_oop(t2);
         __ cas(addr, t1, t2);
+      }
+      } else {
+        __ cas_ptr(addr, t1, t2);
+      }
+    } else {
+      __ cas(addr, t1, t2);
+    }
     __ cmp(t1, t2);
   } else {
 …
   // Update counter for all call types
+  ciMethodData* md = method->method_data();
+  if (md == NULL) {
+    bailout("out of memory building methodDataOop");
+    return;
+  }
+  ciMethodData* md = method->method_data_or_null();
+  assert(md != NULL, "Sanity");
   ciProfileData* data = md->bci_to_data(bci);
   assert(data->is_CounterData(), "need CounterData for calls");
   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
+  Register mdo  = op->mdo()->as_register();
+#ifdef _LP64
+  assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
+  Register tmp1 = op->tmp1()->as_register_lo();
+#else
   assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
-  Register mdo  = op->mdo()->as_register();
   Register tmp1 = op->tmp1()->as_register();
+#endif
   jobject2reg(md->constant_encoding(), mdo);
   int mdo_offset_bias = 0;
 …
   // invokeinterface bytecodes
   if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
       Tier1ProfileVirtualCalls) {
+      C1ProfileVirtualCalls) {
     assert(op->recv()->is_single_cpu(), "recv must be allocated");
     Register recv = op->recv()->as_register();
 …
     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
     ciKlass* known_klass = op->known_holder();
     if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) {
+    if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
       // We know the type that will be seen at this call site; we can
       // statically update the methodDataOop rather than needing to do
 …
                                                          VirtualCallData::receiver_count_offset(i)) -
                             mdo_offset_bias);
           __ lduw(data_addr, tmp1);
+          __ ld_ptr(data_addr, tmp1);
           __ add(tmp1, DataLayout::counter_increment, tmp1);
           __ stw(tmp1, data_addr);
+          __ st_ptr(tmp1, data_addr);
           return;
+        }
 …
           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
                             mdo_offset_bias);
           __ lduw(data_addr, tmp1);
+          __ ld_ptr(data_addr, tmp1);
           __ add(tmp1, DataLayout::counter_increment, tmp1);
           __ stw(tmp1, data_addr);
+          __ st_ptr(tmp1, data_addr);
           return;
+        }
+      }
     } else {
       load(Address(recv, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
+      __ load_klass(recv, recv);
       Label update_done;
+      uint i;
+      for (i = 0; i < VirtualCallData::row_limit(); i++) {
+        Label next_test;
+        // See if the receiver is receiver[n].
+        Address receiver_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
+                              mdo_offset_bias);
+        __ ld_ptr(receiver_addr, tmp1);
+        __ verify_oop(tmp1);
+        __ cmp(recv, tmp1);
+        __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
+        __ delayed()->nop();
+        Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
+                          mdo_offset_bias);
+        __ lduw(data_addr, tmp1);
+        __ add(tmp1, DataLayout::counter_increment, tmp1);
+        __ stw(tmp1, data_addr);
+        __ br(Assembler::always, false, Assembler::pt, update_done);
+        __ delayed()->nop();
+        __ bind(next_test);
+      }
+      // Didn't find receiver; find next empty slot and fill it in
+      for (i = 0; i < VirtualCallData::row_limit(); i++) {
+        Label next_test;
+        Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
+                          mdo_offset_bias);
+        load(recv_addr, tmp1, T_OBJECT);
+        __ tst(tmp1);
+        __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
+        __ delayed()->nop();
+        __ st_ptr(recv, recv_addr);
+        __ set(DataLayout::counter_increment, tmp1);
+        __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
+                  mdo_offset_bias);
+        __ br(Assembler::always, false, Assembler::pt, update_done);
+        __ delayed()->nop();
+        __ bind(next_test);
+      }
+      type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
       // Receiver did not match any saved receiver and there is no empty row for it.
       // Increment total counter to indicate polymorphic case.
       __ lduw(counter_addr, tmp1);
+      __ ld_ptr(counter_addr, tmp1);
       __ add(tmp1, DataLayout::counter_increment, tmp1);
       __ stw(tmp1, counter_addr);
+      __ st_ptr(tmp1, counter_addr);
       __ bind(update_done);
 …
   } else {
     // Static call
     __ lduw(counter_addr, tmp1);
+    __ ld_ptr(counter_addr, tmp1);
     __ add(tmp1, DataLayout::counter_increment, tmp1);
+    __ stw(tmp1, counter_addr);
+  }
+}
+    __ st_ptr(tmp1, counter_addr);
+  }
+}
 void LIR_Assembler::align_backward_branch_target() {
 …
     // use normal move for all other volatiles since they don't need
     // special handling to remain atomic.
     move_op(src, dest, type, lir_patch_none, info, false, false);
+    move_op(src, dest, type, lir_patch_none, info, false, false, false);
+  }
+}
 …
+}
 // Macro to Pack two sequential registers containing 32 bit values
+// Pack two sequential registers containing 32 bit values
 // into a single 64 bit register.
+// rs and rs->successor() are packed into rd
+// rd and rs may be the same register.
+// Note: rs and rs->successor() are destroyed.
+void LIR_Assembler::pack64( Register rs, Register rd ) {
+// src and src->successor() are packed into dst
+// src and dst may be the same register.
+// Note: src is destroyed
+void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
+  Register rs = src->as_register();
+  Register rd = dst->as_register_lo();
   __ sllx(rs, 32, rs);
   __ srl(rs->successor(), 0, rs->successor());
 …
+}
 // Macro to unpack a 64 bit value in a register into
+// Unpack a 64 bit value in a register into
 // two sequential registers.
+// rd is unpacked into rd and rd->successor()
+void LIR_Assembler::unpack64( Register rd ) {
+  __ mov(rd, rd->successor());
+  __ srax(rd, 32, rd);
+  __ sra(rd->successor(), 0, rd->successor());
+// src is unpacked into dst and dst->successor()
+void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
+  Register rs = src->as_register_lo();
+  Register rd = dst->as_register_hi();
+  assert_different_registers(rs, rd, rd->successor());
+  __ srlx(rs, 32, rd);
+  __ srl (rs,  0, rd->successor());
+}
 …
   LIR_Address* addr = addr_opr->as_address_ptr();
   assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet");
+  __ add(addr->base()->as_register(), addr->disp(), dest->as_register());
+  __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
+}
 …
+          }
 #endif
+          continue;
+        } else {
+          LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
+          inst->insert_before(i + 1, delay_op);
+          i++;
+        }
+        LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
+        inst->insert_before(i + 1, delay_op);
+#if defined(TIERED) && !defined(_LP64)
+        // fixup the return value from G1 to O0/O1 for long returns.
+        // It's done here instead of in LIRGenerator because there's
+        // such a mismatch between the single reg and double reg
+        // calling convention.
+        LIR_OpJavaCall* callop = op->as_OpJavaCall();
+        if (callop->result_opr() == FrameMap::out_long_opr) {
+          LIR_OpJavaCall* call;
+          LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length());
+          for (int a = 0; a < arguments->length(); a++) {
+            arguments[a] = callop->arguments()[a];
+          }
+          if (op->code() == lir_virtual_call) {
+            call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
+                                      callop->vtable_offset(), arguments, callop->info());
+          } else {
+            call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
+                                      callop->addr(), arguments, callop->info());
+          }
+          inst->at_put(i - 1, call);
+          inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(),
+                                                 T_LONG, lir_patch_none, NULL));
+        }
+#endif
         break;
+      }

trunk/openjdk/hotspot/src/cpu/sparc/vm/c1_LIRAssembler_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2000, 2006, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP
+#define CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP
  private:
 …
   //
+  // some load/store variants return the code_offset for proper positioning of debug info for null checks
+  int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned);
+  int store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide);
+  // load/store with 32 bit displacement
+  int load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo* info = NULL);
+  void store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info = NULL);
+  // loadf/storef with 32 bit displacement
+  void load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL);
+  void store(FloatRegister d, Register s1, int disp, BasicType st_type, CodeEmitInfo* info = NULL);
+  // convienence methods for calling load/store with an Address
+  void load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0);
+  void store(Register d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0);
+  void load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0);
+  void store(FloatRegister d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0);
+  // convienence methods for calling load/store with an LIR_Address
+  void load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL);
+  void store(Register d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL);
+  void load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL);
+  void store(FloatRegister d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL);
+  int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned = false);
+  int store(LIR_Opr from_reg, Register base, Register disp, BasicType type);
+  int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned = false);
+  int load(Register base, Register disp, LIR_Opr to_reg, BasicType type);
+  int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned);
+  int load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide);
   void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no);
 …
   static bool is_single_instruction(LIR_Op* op);
+  // Record the type of the receiver in ReceiverTypeData
+  void type_profile_helper(Register mdo, int mdo_offset_bias,
+                           ciMethodData *md, ciProfileData *data,
+                           Register recv, Register tmp1, Label* update_done);
+  // Setup pointers to MDO, MDO slot, also compute offset bias to access the slot.
+  void setup_md_access(ciMethod* method, int bci,
+                       ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias);
  public:
   void pack64( Register rs, Register rd );
   void unpack64( Register rd );
+  void   pack64(LIR_Opr src, LIR_Opr dst);
+  void unpack64(LIR_Opr src, LIR_Opr dst);
 enum {
 …
          exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(10*4),
          deopt_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(10*4) };
+#endif // CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/c1_LIRGenerator_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 2005, 2009, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+# include "incls/_precompiled.incl"
+# include "incls/_c1_LIRGenerator_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "c1/c1_Compilation.hpp"
+#include "c1/c1_FrameMap.hpp"
+#include "c1/c1_Instruction.hpp"
+#include "c1/c1_LIRAssembler.hpp"
+#include "c1/c1_LIRGenerator.hpp"
+#include "c1/c1_Runtime1.hpp"
+#include "c1/c1_ValueStack.hpp"
+#include "ci/ciArray.hpp"
+#include "ci/ciObjArrayKlass.hpp"
+#include "ci/ciTypeArrayKlass.hpp"
+#include "runtime/sharedRuntime.hpp"
+#include "runtime/stubRoutines.hpp"
+#include "vmreg_sparc.inline.hpp"
 #ifdef ASSERT
 …
+}
+void LIRGenerator::increment_counter(address counter, int step) {
+LIR_Opr LIRGenerator::load_immediate(int x, BasicType type) {
+  LIR_Opr r;
+  if (type == T_LONG) {
+    r = LIR_OprFact::longConst(x);
+  } else if (type == T_INT) {
+    r = LIR_OprFact::intConst(x);
+  } else {
+    ShouldNotReachHere();
+  }
+  if (!Assembler::is_simm13(x)) {
+    LIR_Opr tmp = new_register(type);
+    __ move(r, tmp);
+    return tmp;
+  }
+  return r;
+}
+void LIRGenerator::increment_counter(address counter, BasicType type, int step) {
   LIR_Opr pointer = new_pointer_register();
   __ move(LIR_OprFact::intptrConst(counter), pointer);
   LIR_Address* addr = new LIR_Address(pointer, T_INT);
+  LIR_Address* addr = new LIR_Address(pointer, type);
   increment_counter(addr, step);
+}
 void LIRGenerator::increment_counter(LIR_Address* addr, int step) {
   LIR_Opr temp = new_register(T_INT);
+  LIR_Opr temp = new_register(addr->type());
   __ move(addr, temp);
+  LIR_Opr c = LIR_OprFact::intConst(step);
+  if (Assembler::is_simm13(step)) {
+    __ add(temp, c, temp);
+  } else {
+    LIR_Opr temp2 = new_register(T_INT);
+    __ move(c, temp2);
+    __ add(temp, temp2, temp);
+  }
+  __ add(temp, load_immediate(step, addr->type()), temp);
   __ move(temp, addr);
+}
 void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
 …
 void LIRGenerator::do_StoreIndexed(StoreIndexed* x) {
   assert(x->is_root(),"");
+  assert(x->is_pinned(),"");
   bool needs_range_check = true;
   bool use_length = x->length() != NULL;
 …
 void LIRGenerator::do_MonitorEnter(MonitorEnter* x) {
   assert(x->is_root(),"");
+  assert(x->is_pinned(),"");
   LIRItem obj(x->obj(), this);
   obj.load_item();
 …
   CodeEmitInfo* info_for_exception = NULL;
   if (x->needs_null_check()) {
     info_for_exception = state_for(x, x->lock_stack_before());
+    info_for_exception = state_for(x);
+  }
 …
 void LIRGenerator::do_MonitorExit(MonitorExit* x) {
   assert(x->is_root(),"");
+  assert(x->is_pinned(),"");
   LIRItem obj(x->obj(), this);
   obj.dont_load_item();
 …
   right.load_item();
   LIR_Opr reg = rlock_result(x);
   if (x->x()->type()->is_float_kind()) {
     Bytecodes::Code code = x->op();
 …
   // generate conditional move of boolean result
   LIR_Opr result = rlock_result(x);
   __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0), result);
+  __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0), result, T_LONG);
+}
 …
     ShouldNotReachHere();
+  }
   // generate conditional move of boolean result
   LIR_Opr result = rlock_result(x);
+  __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0), result);
+  __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0),
+           result, as_BasicType(type));
   if (type == objectType) {  // Write-barrier needed for Object fields.
     // Precise card mark since could either be object or array
 …
   // O0 as result register.
   const LIR_Opr reg = result_register_for(x->type());
+#ifndef PRODUCT
   if (PrintNotLoaded && !x->klass()->is_loaded()) {
+    tty->print_cr("   ###class not loaded at new bci %d", x->bci());
+  }
+    tty->print_cr("   ###class not loaded at new bci %d", x->printable_bci());
+  }
+#endif
   CodeEmitInfo* info = state_for(x, x->state());
   LIR_Opr tmp1 = FrameMap::G1_oop_opr;
 …
   LIR_Opr out_reg = rlock_result(x);
   CodeStub* stub;
   CodeEmitInfo* info_for_exception = state_for(x, x->state()->copy_locks());
+  CodeEmitInfo* info_for_exception = state_for(x);
   if (x->is_incompatible_class_change_check()) {
 …
   LIR_Opr tmp2 = FrameMap::G3_oop_opr;
   LIR_Opr tmp3 = FrameMap::G4_oop_opr;
+  __ instanceof(out_reg, obj.result(), x->klass(), tmp1, tmp2, tmp3,  x->direct_compare(), patching_info);
+  __ instanceof(out_reg, obj.result(), x->klass(), tmp1, tmp2, tmp3,
+                x->direct_compare(), patching_info,
+                x->profiled_method(), x->profiled_bci());
+}
 …
   if (x->is_safepoint()) {
     // increment backedge counter if needed
+    increment_backedge_counter(state_for(x, x->state_before()));
+    increment_backedge_counter(state_for(x, x->state_before()), x->profiled_bci());
     __ safepoint(new_register(T_INT), state_for(x, x->state_before()));
+  }
   __ cmp(lir_cond(cond), left, right);
+  // Generate branch profiling. Profiling code doesn't kill flags.
   profile_branch(x, cond);
   move_to_phi(x->state());

trunk/openjdk/hotspot/src/cpu/sparc/vm/c1_LinearScan_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 2005, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "incls/_precompiled.incl"
+#include "incls/_c1_LinearScan_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "c1/c1_Instruction.hpp"
+#include "c1/c1_LinearScan.hpp"
+#include "utilities/bitMap.inline.hpp"
 void LinearScan::allocate_fpu_stack() {

trunk/openjdk/hotspot/src/cpu/sparc/vm/c1_LinearScan_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2005, 2006, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_C1_LINEARSCAN_SPARC_HPP
+#define CPU_SPARC_VM_C1_LINEARSCAN_SPARC_HPP
 inline bool LinearScan::is_processed_reg_num(int reg_num) {
 …
     _last_reg = pd_last_callee_saved_reg;
     return true;
   } else if (cur->type() == T_INT || cur->type() == T_LONG || cur->type() == T_OBJECT) {
+  } else if (cur->type() == T_INT || cur->type() == T_LONG || cur->type() == T_OBJECT || cur->type() == T_ADDRESS) {
     _first_reg = pd_first_cpu_reg;
     _last_reg = pd_last_allocatable_cpu_reg;
 …
   return false;
+}
+#endif // CPU_SPARC_VM_C1_LINEARSCAN_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/c1_MacroAssembler_sparc.cpp

-              r278
+              r309
  */
+#include "incls/_precompiled.incl"
+#include "incls/_c1_MacroAssembler_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "c1/c1_MacroAssembler.hpp"
+#include "c1/c1_Runtime1.hpp"
+#include "classfile/systemDictionary.hpp"
+#include "gc_interface/collectedHeap.hpp"
+#include "interpreter/interpreter.hpp"
+#include "oops/arrayOop.hpp"
+#include "oops/markOop.hpp"
+#include "runtime/basicLock.hpp"
+#include "runtime/biasedLocking.hpp"
+#include "runtime/os.hpp"
+#include "runtime/stubRoutines.hpp"
 void C1_MacroAssembler::inline_cache_check(Register receiver, Register iCache) {
 …
   // Note: needs more testing of out-of-line vs. inline slow case
   verify_oop(receiver);
   ld_ptr(receiver, oopDesc::klass_offset_in_bytes(), temp_reg);
+  load_klass(receiver, temp_reg);
   cmp(temp_reg, iCache);
   brx(Assembler::equal, true, Assembler::pt, L);
 …
   Register var_size_in_bytes,          // object size in bytes if unknown at compile time; invalid otherwise
   int      con_size_in_bytes,          // object size in bytes if   known at compile time
   Register t1,                         // temp register
+  Register t1,                         // temp register, must be global register for incr_allocated_bytes
   Register t2,                         // temp register
   Label&   slow_case                   // continuation point if fast allocation fails
 ) {
+  RegisterOrConstant size_in_bytes = var_size_in_bytes->is_valid()
+    ? RegisterOrConstant(var_size_in_bytes) : RegisterOrConstant(con_size_in_bytes);
   if (UseTLAB) {
     tlab_allocate(obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
   } else {
     eden_allocate(obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
+    incr_allocated_bytes(size_in_bytes, t1, t2);
+  }
+}
 …
     set((intx)markOopDesc::prototype(), t1);
+  }
+  st_ptr(t1  , obj, oopDesc::mark_offset_in_bytes       ());
+  st_ptr(klass, obj, oopDesc::klass_offset_in_bytes      ());
+  if (len->is_valid()) st(len  , obj, arrayOopDesc::length_offset_in_bytes());
+  st_ptr(t1, obj, oopDesc::mark_offset_in_bytes());
+  if (UseCompressedOops) {
+    // Save klass
+    mov(klass, t1);
+    encode_heap_oop_not_null(t1);
+    stw(t1, obj, oopDesc::klass_offset_in_bytes());
+  } else {
+    st_ptr(klass, obj, oopDesc::klass_offset_in_bytes());
+  }
+  if (len->is_valid()) st(len, obj, arrayOopDesc::length_offset_in_bytes());
+  else if (UseCompressedOops) {
+    store_klass_gap(G0, obj);
+  }
+}
 …
   Register obj,                        // result: pointer to object after successful allocation
   Register t1,                         // temp register
   Register t2,                         // temp register
+  Register t2,                         // temp register, must be a global register for try_allocate
   Register t3,                         // temp register
   int      hdr_size,                   // object header size in words
 …
   Register t2                          // temp register
   ) {
   const int hdr_size_in_bytes = instanceOopDesc::base_offset_in_bytes();
+  const int hdr_size_in_bytes = instanceOopDesc::header_size() * HeapWordSize;
   initialize_header(obj, klass, noreg, t1, t2);

trunk/openjdk/hotspot/src/cpu/sparc/vm/c1_MacroAssembler_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1999, 2005, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1999, 2011, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_C1_MACROASSEMBLER_SPARC_HPP
+#define CPU_SPARC_VM_C1_MACROASSEMBLER_SPARC_HPP
   void pd_init() { /* nothing to do */ }
 …
   void invalidate_registers(bool iregisters, bool lregisters, bool oregisters,
                             Register preserve1 = noreg, Register preserve2 = noreg);
+#endif // CPU_SPARC_VM_C1_MACROASSEMBLER_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/c1_Runtime1_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1999, 2011, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "incls/_precompiled.incl"
+#include "incls/_c1_Runtime1_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "c1/c1_Defs.hpp"
+#include "c1/c1_MacroAssembler.hpp"
+#include "c1/c1_Runtime1.hpp"
+#include "interpreter/interpreter.hpp"
+#include "nativeInst_sparc.hpp"
+#include "oops/compiledICHolderOop.hpp"
+#include "oops/oop.inline.hpp"
+#include "prims/jvmtiExport.hpp"
+#include "register_sparc.hpp"
+#include "runtime/sharedRuntime.hpp"
+#include "runtime/signature.hpp"
+#include "runtime/vframeArray.hpp"
+#include "vmreg_sparc.inline.hpp"
 // Implementation of StubAssembler
 …
   restore_live_registers(sasm);
+  __ restore();
+  __ br(Assembler::always, false, Assembler::pt, deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type);
+  __ delayed()->nop();
+  AddressLiteral dest(deopt_blob->unpack_with_reexecution());
+  __ jump_to(dest, O0);
+  __ delayed()->restore();
   __ bind(no_deopt);
 …
           // get the instance size
           __ ld(G5_klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes(), G1_obj_size);
           __ tlab_allocate(O0_obj, G1_obj_size, 0, G3_t1, slow_path);
           __ initialize_object(O0_obj, G5_klass, G1_obj_size, 0, G3_t1, G4_t2);
           __ verify_oop(O0_obj);
 …
           __ ld(G5_klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes(), G1_obj_size);
           __ eden_allocate(O0_obj, G1_obj_size, 0, G3_t1, G4_t2, slow_path);
+          __ incr_allocated_bytes(G1_obj_size, G3_t1, G4_t2);
           __ initialize_object(O0_obj, G5_klass, G1_obj_size, 0, G3_t1, G4_t2);
           __ verify_oop(O0_obj);
 …
       break;
-#ifdef TIERED
     case counter_overflow_id:
+        // G4 contains bci
+      oop_maps = generate_stub_call(sasm, noreg, CAST_FROM_FN_PTR(address, counter_overflow), G4);
+      break;
+#endif // TIERED
+        // G4 contains bci, G5 contains method
+      oop_maps = generate_stub_call(sasm, noreg, CAST_FROM_FN_PTR(address, counter_overflow), G4, G5);
+      break;
     case new_type_array_id:
 …
           __ eden_allocate(O0_obj, G1_arr_size, 0, G3_t1, O1_t2, slow_path);  // preserves G1_arr_size
+          __ incr_allocated_bytes(G1_arr_size, G3_t1, O1_t2);
           __ initialize_header(O0_obj, G5_klass, G4_length, G3_t1, O1_t2);
 …
         Label register_finalizer;
         Register t = O1;
         __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), t);
+        __ load_klass(O0, t);
         __ ld(t, Klass::access_flags_offset_in_bytes() + sizeof(oopDesc), t);
         __ set(JVM_ACC_HAS_FINALIZER, G3);

trunk/openjdk/hotspot/src/cpu/sparc/vm/c1_globals_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2000, 2007, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_C1_GLOBALS_SPARC_HPP
+#define CPU_SPARC_VM_C1_GLOBALS_SPARC_HPP
+#include "utilities/globalDefinitions.hpp"
+#include "utilities/macros.hpp"
 // Sets the default values for platform dependent flags used by the client compiler.
 // (see c1_globals.hpp)
 …
 define_pd_global(bool, TieredCompilation,            false);
 define_pd_global(intx, CompileThreshold,             1000 ); // Design center runs on 1.3.1
-define_pd_global(intx, Tier2CompileThreshold,        1500 );
-define_pd_global(intx, Tier3CompileThreshold,        2000 );
-define_pd_global(intx, Tier4CompileThreshold,        2500 );
 define_pd_global(intx, BackEdgeThreshold,            100000);
-define_pd_global(intx, Tier2BackEdgeThreshold,       100000);
-define_pd_global(intx, Tier3BackEdgeThreshold,       100000);
-define_pd_global(intx, Tier4BackEdgeThreshold,       100000);
 define_pd_global(intx, OnStackReplacePercentage,     1400 );
 …
 define_pd_global(intx, SafepointPollOffset,          0    );
+#endif // CPU_SPARC_VM_C1_GLOBALS_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/c2_globals_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2000, 2007, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_C2_GLOBALS_SPARC_HPP
+#define CPU_SPARC_VM_C2_GLOBALS_SPARC_HPP
+#include "utilities/globalDefinitions.hpp"
+#include "utilities/macros.hpp"
 // Sets the default values for platform dependent flags used by the server compiler.
 // (see c2_globals.hpp).  Alpha-sorted.
 …
 #endif // CC_INTERP
 define_pd_global(bool, TieredCompilation,            false);
-#ifdef TIERED
-define_pd_global(intx, CompileThreshold,             1000);
-define_pd_global(intx, BackEdgeThreshold,            14000);
-#else
 define_pd_global(intx, CompileThreshold,             10000);
 define_pd_global(intx, BackEdgeThreshold,            140000);
-#endif // TIERED
-define_pd_global(intx, Tier2CompileThreshold,        10000); // unused level
-define_pd_global(intx, Tier3CompileThreshold,        10000);
-define_pd_global(intx, Tier4CompileThreshold,        40000);
-define_pd_global(intx, Tier2BackEdgeThreshold,       100000);
-define_pd_global(intx, Tier3BackEdgeThreshold,       100000);
-define_pd_global(intx, Tier4BackEdgeThreshold,       100000);
 define_pd_global(intx, OnStackReplacePercentage,     140);
 …
 // Ergonomics related flags
 define_pd_global(bool, NeverActAsServerClassMachine, false);
+#endif // CPU_SPARC_VM_C2_GLOBALS_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/c2_init_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 2000, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+# include "incls/_precompiled.incl"
+# include "incls/_c2_init_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "opto/compile.hpp"
+#include "opto/node.hpp"
 // processor dependent initialization for sparc

trunk/openjdk/hotspot/src/cpu/sparc/vm/codeBuffer_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2002, 2005, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_CODEBUFFER_SPARC_HPP
+#define CPU_SPARC_VM_CODEBUFFER_SPARC_HPP
 private:
   void pd_initialize() {}
 …
   // Heuristic for pre-packing the pt/pn bit of a predicted branch.
   bool is_backward_branch(Label& L) {
     return L.is_bound() && code_end() <= locator_address(L.loc());
+    return L.is_bound() && insts_end() <= locator_address(L.loc());
+  }
+#endif // CPU_SPARC_VM_CODEBUFFER_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/copy_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2003, 2008, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_COPY_SPARC_HPP
+#define CPU_SPARC_VM_COPY_SPARC_HPP
 // Inline functions for memory copy and fill.
 …
   (void)memset(to, 0, count);
+}
+#endif // CPU_SPARC_VM_COPY_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/cppInterpreterGenerator_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_CPPINTERPRETERGENERATOR_SPARC_HPP
+#define CPU_SPARC_VM_CPPINTERPRETERGENERATOR_SPARC_HPP
   static address frame_manager_return;
   static address frame_manager_sync_return;
 …
                                           const Register prev_state,
                                           bool native);
+#endif // CPU_SPARC_VM_CPPINTERPRETERGENERATOR_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/cppInterpreter_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 2007, 2009, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "incls/_precompiled.incl"
+#include "incls/_cppInterpreter_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "asm/assembler.hpp"
+#include "interpreter/bytecodeHistogram.hpp"
+#include "interpreter/cppInterpreter.hpp"
+#include "interpreter/interpreter.hpp"
+#include "interpreter/interpreterGenerator.hpp"
+#include "interpreter/interpreterRuntime.hpp"
+#include "oops/arrayOop.hpp"
+#include "oops/methodDataOop.hpp"
+#include "oops/methodOop.hpp"
+#include "oops/oop.inline.hpp"
+#include "prims/jvmtiExport.hpp"
+#include "prims/jvmtiThreadState.hpp"
+#include "runtime/arguments.hpp"
+#include "runtime/deoptimization.hpp"
+#include "runtime/frame.inline.hpp"
+#include "runtime/interfaceSupport.hpp"
+#include "runtime/sharedRuntime.hpp"
+#include "runtime/stubRoutines.hpp"
+#include "runtime/synchronizer.hpp"
+#include "runtime/timer.hpp"
+#include "runtime/vframeArray.hpp"
+#include "utilities/debug.hpp"
+#ifdef SHARK
+#include "shark/shark_globals.hpp"
+#endif
 #ifdef CC_INTERP

trunk/openjdk/hotspot/src/cpu/sparc/vm/cppInterpreter_sparc.hpp

-              r278
+              r309
  */
+#ifndef CPU_SPARC_VM_CPPINTERPRETER_SPARC_HPP
+#define CPU_SPARC_VM_CPPINTERPRETER_SPARC_HPP
   // Size of interpreter code.  Increase if too small.  Interpreter will
   // fail with a guarantee ("not enough space for interpreter generation");
 …
   const static int InterpreterCodeSize = 180 * K;
 #endif
+#endif // CPU_SPARC_VM_CPPINTERPRETER_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/debug_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 1999, 2007, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "incls/_precompiled.incl"
+#include "incls/_debug_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "code/codeCache.hpp"
+#include "code/nmethod.hpp"
+#include "runtime/frame.hpp"
+#include "runtime/init.hpp"
+#include "runtime/os.hpp"
+#include "utilities/debug.hpp"
+#include "utilities/top.hpp"
 #ifndef PRODUCT

trunk/openjdk/hotspot/src/cpu/sparc/vm/depChecker_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+# include "incls/_precompiled.incl"
+# include "incls/_depChecker_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "compiler/disassembler.hpp"
+#include "depChecker_sparc.hpp"
 // Nothing to do on Sparc

trunk/openjdk/hotspot/src/cpu/sparc/vm/depChecker_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_DEPCHECKER_SPARC_HPP
+#define CPU_SPARC_VM_DEPCHECKER_SPARC_HPP
 // Nothing to do on Sparc
+#endif // CPU_SPARC_VM_DEPCHECKER_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/disassembler_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2008, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_DISASSEMBLER_SPARC_HPP
+#define CPU_SPARC_VM_DISASSEMBLER_SPARC_HPP
   static int pd_instruction_alignment() {
     return sizeof(int);
 …
             (VM_Version::v8_instructions_work()? "" : "v9only") : "v8only");
+  }
+#endif // CPU_SPARC_VM_DISASSEMBLER_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/dump_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 2004, 2009, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+# include "incls/_precompiled.incl"
+# include "incls/_dump_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "assembler_sparc.inline.hpp"
+#include "memory/compactingPermGenGen.hpp"
+#include "memory/generation.inline.hpp"
+#include "memory/space.inline.hpp"

trunk/openjdk/hotspot/src/cpu/sparc/vm/frame_sparc.cpp

-              r278
+              r309
  */
+# include "incls/_precompiled.incl"
+# include "incls/_frame_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "interpreter/interpreter.hpp"
+#include "memory/resourceArea.hpp"
+#include "oops/markOop.hpp"
+#include "oops/methodOop.hpp"
+#include "oops/oop.inline.hpp"
+#include "runtime/frame.inline.hpp"
+#include "runtime/handles.inline.hpp"
+#include "runtime/javaCalls.hpp"
+#include "runtime/monitorChunk.hpp"
+#include "runtime/signature.hpp"
+#include "runtime/stubCodeGenerator.hpp"
+#include "runtime/stubRoutines.hpp"
+#include "vmreg_sparc.inline.hpp"
+#ifdef COMPILER1
+#include "c1/c1_Runtime1.hpp"
+#include "runtime/vframeArray.hpp"
+#endif
 void RegisterMap::pd_clear() {
 …
     // Could just be some random pointer within the codeBlob
+    if (!sender.cb()->instructions_contains(sender_pc)) return false;
+    if (!sender.cb()->code_contains(sender_pc)) {
+      return false;
+    }
     // We should never be able to see an adapter if the current frame is something from code cache
+    if ( sender_blob->is_adapter_blob()) {
+    if (sender_blob->is_adapter_blob()) {
       return false;
+    }

trunk/openjdk/hotspot/src/cpu/sparc/vm/frame_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2006, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_FRAME_SPARC_HPP
+#define CPU_SPARC_VM_FRAME_SPARC_HPP
+#include "runtime/synchronizer.hpp"
+#include "utilities/top.hpp"
 // A frame represents a physical stack frame (an activation).  Frames can be
 …
  private:
+  constantPoolCacheOop* frame::interpreter_frame_cpoolcache_addr() const;
+  constantPoolCacheOop* interpreter_frame_cpoolcache_addr() const;
 #ifndef CC_INTERP
 …
 #endif
+  }
+#endif // CPU_SPARC_VM_FRAME_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/frame_sparc.inline.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2009, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_FRAME_SPARC_INLINE_HPP
+#define CPU_SPARC_VM_FRAME_SPARC_INLINE_HPP
 // Inline functions for SPARC frames:
 …
   *((oop*) map->location(O0->as_VMReg())) = obj;
+}
+#endif // CPU_SPARC_VM_FRAME_SPARC_INLINE_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/globalDefinitions_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1999, 2004, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_GLOBALDEFINITIONS_SPARC_HPP
+#define CPU_SPARC_VM_GLOBALDEFINITIONS_SPARC_HPP
 // Size of Sparc Instructions
 const int BytesPerInstWord = 4;
 const int StackAlignmentInBytes = (2*wordSize);
+#endif // CPU_SPARC_VM_GLOBALDEFINITIONS_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/globals_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2000, 2009, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_GLOBALS_SPARC_HPP
+#define CPU_SPARC_VM_GLOBALS_SPARC_HPP
+#include "utilities/globalDefinitions.hpp"
+#include "utilities/macros.hpp"
 // Sets the default values for platform dependent flags used by the runtime system.
 …
 define_pd_global(bool, RewriteBytecodes,     true);
 define_pd_global(bool, RewriteFrequentPairs, true);
+define_pd_global(bool, UseMembar,            false);
+#endif // CPU_SPARC_VM_GLOBALS_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/icBuffer_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2009, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "incls/_precompiled.incl"
+#include "incls/_icBuffer_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "asm/assembler.hpp"
+#include "assembler_sparc.inline.hpp"
+#include "code/icBuffer.hpp"
+#include "gc_interface/collectedHeap.inline.hpp"
+#include "interpreter/bytecodes.hpp"
+#include "memory/resourceArea.hpp"
+#include "nativeInst_sparc.hpp"
+#include "oops/oop.inline.hpp"
+#include "oops/oop.inline2.hpp"
 int InlineCacheBuffer::ic_stub_code_size() {

trunk/openjdk/hotspot/src/cpu/sparc/vm/icache_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2004, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "incls/_precompiled.incl"
+#include "incls/_icache_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "assembler_sparc.inline.hpp"
+#include "runtime/icache.hpp"
 #define __ _masm->

trunk/openjdk/hotspot/src/cpu/sparc/vm/icache_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2004, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_ICACHE_SPARC_HPP
+#define CPU_SPARC_VM_ICACHE_SPARC_HPP
 // Interface for updating the instruction cache.  Whenever the VM modifies
 // code, part of the processor instruction cache potentially has to be flushed.
 …
   // Use default implementation
 };
+#endif // CPU_SPARC_VM_ICACHE_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/interp_masm_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "incls/_precompiled.incl"
+#include "incls/_interp_masm_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "interp_masm_sparc.hpp"
+#include "interpreter/interpreter.hpp"
+#include "interpreter/interpreterRuntime.hpp"
+#include "oops/arrayOop.hpp"
+#include "oops/markOop.hpp"
+#include "oops/methodDataOop.hpp"
+#include "oops/methodOop.hpp"
+#include "prims/jvmtiExport.hpp"
+#include "prims/jvmtiRedefineClassesTrace.hpp"
+#include "prims/jvmtiThreadState.hpp"
+#include "runtime/basicLock.hpp"
+#include "runtime/biasedLocking.hpp"
+#include "runtime/sharedRuntime.hpp"
+#ifdef TARGET_OS_FAMILY_linux
+# include "thread_linux.inline.hpp"
+#endif
+#ifdef TARGET_OS_FAMILY_solaris
+# include "thread_solaris.inline.hpp"
+#endif
 #ifndef CC_INTERP
 …
 // specified register to its value.
 void InterpreterMacroAssembler::set_method_data_pointer_offset(Register Roff) {
+void InterpreterMacroAssembler::set_method_data_pointer() {
   assert(ProfileInterpreter, "must be profiling interpreter");
   Label get_continue;
 …
   test_method_data_pointer(get_continue);
   add(ImethodDataPtr, in_bytes(methodDataOopDesc::data_offset()), ImethodDataPtr);
-  if (Roff != noreg)
-    // Roff contains a method data index ("mdi").  It defaults to zero.
-    add(ImethodDataPtr, Roff, ImethodDataPtr);
   bind(get_continue);
+}
 …
   // Test MDO to avoid the call if it is NULL.
   ld_ptr(Lmethod, methodOopDesc::method_data_offset(), ImethodDataPtr);
+  ld_ptr(Lmethod, in_bytes(methodOopDesc::method_data_offset()), ImethodDataPtr);
   test_method_data_pointer(zero_continue);
   call_VM_leaf(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::bcp_to_di), Lmethod, Lbcp);
+  set_method_data_pointer_offset(O0);
+  add(ImethodDataPtr, in_bytes(methodDataOopDesc::data_offset()), ImethodDataPtr);
+  add(ImethodDataPtr, O0, ImethodDataPtr);
   bind(zero_continue);
+}
 …
 void InterpreterMacroAssembler::test_invocation_counter_for_mdp(Register invocation_count,
-                                                                Register cur_bcp,
                                                                 Register Rtmp,
                                                                 Label &profile_continue) {
 …
   // Build it now.
   call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::profile_method), cur_bcp);
   set_method_data_pointer_offset(O0);
+  call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::profile_method));
+  set_method_data_pointer_for_bcp();
   ba(false, profile_continue);
   delayed()->nop();
 …
 #endif // CC_INTERP
+}
+// Jump if ((*counter_addr += increment) & mask) satisfies the condition.
+void InterpreterMacroAssembler::increment_mask_and_jump(Address counter_addr,
+                                                        int increment, int mask,
+                                                        Register scratch1, Register scratch2,
+                                                        Condition cond, Label *where) {
+  ld(counter_addr, scratch1);
+  add(scratch1, increment, scratch1);
+  if (is_simm13(mask)) {
+    andcc(scratch1, mask, G0);
+  } else {
+    set(mask, scratch2);
+    andcc(scratch1, scratch2,  G0);
+  }
+  br(cond, false, Assembler::pn, *where);
+  delayed()->st(scratch1, counter_addr);
+}

trunk/openjdk/hotspot/src/cpu/sparc/vm/interp_masm_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_INTERP_MASM_SPARC_HPP
+#define CPU_SPARC_VM_INTERP_MASM_SPARC_HPP
+#include "assembler_sparc.inline.hpp"
+#include "interpreter/invocationCounter.hpp"
 // This file specializes the assember with interpreter-specific macros
 …
 #ifndef CC_INTERP
   // Interpreter profiling operations
   void set_method_data_pointer() { set_method_data_pointer_offset(noreg); }
+  void set_method_data_pointer();
   void set_method_data_pointer_for_bcp();
-  void set_method_data_pointer_offset(Register mdi_reg);
   void test_method_data_pointer(Label& zero_continue);
   void verify_method_data_pointer();
   void test_invocation_counter_for_mdp(Register invocation_count, Register cur_bcp, Register Rtmp, Label &profile_continue);
+  void test_invocation_counter_for_mdp(Register invocation_count, Register Rtmp, Label &profile_continue);
   void set_mdp_data_at(int constant, Register value);
 …
                              Register bumped_count, Register scratch2,
                              bool decrement = false);
+  void increment_mask_and_jump(Address counter_addr,
+                               int increment, int mask,
+                               Register scratch1, Register scratch2,
+                               Condition cond, Label *where);
   void set_mdp_flag_at(int flag_constant, Register scratch);
   void test_mdp_data_at(int offset, Register value, Label& not_equal_continue,
 …
   void save_return_value(TosState state, bool is_native_call);
   void restore_return_value(TosState state, bool is_native_call);
 };
+#endif // CPU_SPARC_VM_INTERP_MASM_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/interpreterGenerator_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2009, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_INTERPRETERGENERATOR_SPARC_HPP
+#define CPU_SPARC_VM_INTERPRETERGENERATOR_SPARC_HPP
  friend class AbstractInterpreterGenerator;
 …
   void generate_counter_incr(Label* overflow, Label* profile_method, Label* profile_method_continue);
   void generate_counter_overflow(Label& Lcontinue);
+#endif // CPU_SPARC_VM_INTERPRETERGENERATOR_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/interpreterRT_sparc.cpp

-              r278
+              r309
  */
+#include "incls/_precompiled.incl"
+#include "incls/_interpreterRT_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "interpreter/interpreter.hpp"
+#include "interpreter/interpreterRuntime.hpp"
+#include "memory/allocation.inline.hpp"
+#include "memory/universe.inline.hpp"
+#include "oops/methodOop.hpp"
+#include "oops/oop.inline.hpp"
+#include "runtime/handles.inline.hpp"
+#include "runtime/icache.hpp"
+#include "runtime/interfaceSupport.hpp"
+#include "runtime/signature.hpp"

trunk/openjdk/hotspot/src/cpu/sparc/vm/interpreterRT_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1998, 2005, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_INTERPRETERRT_SPARC_HPP
+#define CPU_SPARC_VM_INTERPRETERRT_SPARC_HPP
+#include "memory/allocation.hpp"
 static int binary_search(int key, LookupswitchPair* array, int n);
 …
   void generate( uint64_t fingerprint );
 };
+#endif // CPU_SPARC_VM_INTERPRETERRT_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/interpreter_sparc.cpp

-              r278
+              r309
  */
+#include "incls/_precompiled.incl"
+#include "incls/_interpreter_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "asm/assembler.hpp"
+#include "interpreter/bytecodeHistogram.hpp"
+#include "interpreter/interpreter.hpp"
+#include "interpreter/interpreterGenerator.hpp"
+#include "interpreter/interpreterRuntime.hpp"
+#include "interpreter/templateTable.hpp"
+#include "oops/arrayOop.hpp"
+#include "oops/methodDataOop.hpp"
+#include "oops/methodOop.hpp"
+#include "oops/oop.inline.hpp"
+#include "prims/jvmtiExport.hpp"
+#include "prims/jvmtiThreadState.hpp"
+#include "prims/methodHandles.hpp"
+#include "runtime/arguments.hpp"
+#include "runtime/deoptimization.hpp"
+#include "runtime/frame.inline.hpp"
+#include "runtime/sharedRuntime.hpp"
+#include "runtime/stubRoutines.hpp"
+#include "runtime/synchronizer.hpp"
+#include "runtime/timer.hpp"
+#include "runtime/vframeArray.hpp"
+#include "utilities/debug.hpp"
+#ifdef COMPILER1
+#include "c1/c1_Runtime1.hpp"
+#endif

trunk/openjdk/hotspot/src/cpu/sparc/vm/interpreter_sparc.hpp

-              r278
+              r309
  */
+#ifndef CPU_SPARC_VM_INTERPRETER_SPARC_HPP
+#define CPU_SPARC_VM_INTERPRETER_SPARC_HPP
  public:
 …
     return stackElementWords * i;
+  }
+#endif // CPU_SPARC_VM_INTERPRETER_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/javaFrameAnchor_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2002, 2005, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_JAVAFRAMEANCHOR_SPARC_HPP
+#define CPU_SPARC_VM_JAVAFRAMEANCHOR_SPARC_HPP
 private:
 …
     OrderAccess::fence();
+  }
+#endif // CPU_SPARC_VM_JAVAFRAMEANCHOR_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/jniFastGetField_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 2004, 2009, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+# include "incls/_precompiled.incl"
+# include "incls/_jniFastGetField_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "assembler_sparc.inline.hpp"
+#include "memory/resourceArea.hpp"
+#include "prims/jniFastGetField.hpp"
+#include "prims/jvm_misc.hpp"
+#include "runtime/safepoint.hpp"
 // TSO ensures that loads are blocking and ordered with respect to
 …
+  }
   ResourceMark rm;
+  BufferBlob* b = BufferBlob::create(name, BUFFER_SIZE*wordSize);
+  address fast_entry = b->instructions_begin();
+  CodeBuffer cbuf(fast_entry, b->instructions_size());
+  BufferBlob* blob = BufferBlob::create(name, BUFFER_SIZE*wordSize);
+  CodeBuffer cbuf(blob);
   MacroAssembler* masm = new MacroAssembler(&cbuf);
+  address fast_entry = __ pc();
   Label label1, label2;
 …
   const char *name = "jni_fast_GetLongField";
   ResourceMark rm;
+  BufferBlob* b = BufferBlob::create(name, BUFFER_SIZE*wordSize);
+  address fast_entry = b->instructions_begin();
+  CodeBuffer cbuf(fast_entry, b->instructions_size());
+  BufferBlob* blob = BufferBlob::create(name, BUFFER_SIZE*wordSize);
+  CodeBuffer cbuf(blob);
   MacroAssembler* masm = new MacroAssembler(&cbuf);
+  address fast_entry = __ pc();
   Label label1, label2;
 …
+  }
   ResourceMark rm;
+  BufferBlob* b = BufferBlob::create(name, BUFFER_SIZE*wordSize);
+  address fast_entry = b->instructions_begin();
+  CodeBuffer cbuf(fast_entry, b->instructions_size());
+  BufferBlob* blob = BufferBlob::create(name, BUFFER_SIZE*wordSize);
+  CodeBuffer cbuf(blob);
   MacroAssembler* masm = new MacroAssembler(&cbuf);
+  address fast_entry = __ pc();
   Label label1, label2;

trunk/openjdk/hotspot/src/cpu/sparc/vm/jniTypes_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1998, 2002, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_JNITYPES_SPARC_HPP
+#define CPU_SPARC_VM_JNITYPES_SPARC_HPP
+#include "memory/allocation.hpp"
+#include "oops/oop.hpp"
+#include "prims/jni.h"
 // This file holds platform-dependent routines used to write primitive jni
 …
 };
+#endif // CPU_SPARC_VM_JNITYPES_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/jni_sparc.h

r278	r309
1	1	/*
2		* Copyright (c) 1997, 2009, Oracle and/or its affiliates. All rights reserved.
	2	* Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4	4	*

trunk/openjdk/hotspot/src/cpu/sparc/vm/methodHandles_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2008, 2011, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "incls/_precompiled.incl"
+#include "incls/_methodHandles_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "interpreter/interpreter.hpp"
+#include "memory/allocation.inline.hpp"
+#include "prims/methodHandles.hpp"
 #define __ _masm->
+#ifdef PRODUCT
+#define BLOCK_COMMENT(str) /* nothing */
+#else
+#define BLOCK_COMMENT(str) __ block_comment(str)
+#endif
+#define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
 address MethodHandleEntry::start_compiled_entry(MacroAssembler* _masm,
 …
 // Code generation
 address MethodHandles::generate_method_handle_interpreter_entry(MacroAssembler* _masm) {
   // I5_savedSP: sender SP (must preserve)
+  // I5_savedSP/O5_savedSP: sender SP (must preserve)
   // G4 (Gargs): incoming argument list (must preserve)
   // G5_method:  invoke methodOop; becomes method type.
+  // G5_method:  invoke methodOop
   // G3_method_handle: receiver method handle (must load from sp[MethodTypeForm.vmslots])
   // O0, O1: garbage temps, blown away
   Register O0_argslot = O0;
+  // O0, O1, O2, O3, O4: garbage temps, blown away
+  Register O0_mtype   = O0;
   Register O1_scratch = O1;
+  Register O2_scratch = O2;
+  Register O3_scratch = O3;
+  Register O4_argslot = O4;
+  Register O4_argbase = O4;
   // emit WrongMethodType path first, to enable back-branch from main path
   Label wrong_method_type;
   __ bind(wrong_method_type);
+  Label invoke_generic_slow_path;
+  assert(methodOopDesc::intrinsic_id_size_in_bytes() == sizeof(u1), "");;
+  __ ldub(Address(G5_method, methodOopDesc::intrinsic_id_offset_in_bytes()), O1_scratch);
+  __ cmp(O1_scratch, (int) vmIntrinsics::_invokeExact);
+  __ brx(Assembler::notEqual, false, Assembler::pt, invoke_generic_slow_path);
+  __ delayed()->nop();
+  __ mov(O0_mtype, G5_method_type);  // required by throw_WrongMethodType
+  // mov(G3_method_handle, G3_method_handle);  // already in this register
   __ jump_to(AddressLiteral(Interpreter::throw_WrongMethodType_entry()), O1_scratch);
   __ delayed()->nop();
 …
   address entry_point = __ pc();
   // fetch the MethodType from the method handle into G5_method_type
+  // fetch the MethodType from the method handle
+  {
     Register tem = G5_method;
-    assert(tem == G5_method_type, "yes, it's the same register");
     for (jint* pchase = methodOopDesc::method_type_offsets_chain(); (*pchase) != -1; pchase++) {
+      __ ld_ptr(Address(tem, *pchase), G5_method_type);
+      __ ld_ptr(Address(tem, *pchase), O0_mtype);
+      tem = O0_mtype;          // in case there is another indirection
+    }
+  }
   // given the MethodType, find out where the MH argument is buried
+  __ ld_ptr(Address(G5_method_type, __ delayed_value(java_dyn_MethodType::form_offset_in_bytes, O1_scratch)),        O0_argslot);
+  __ ldsw(  Address(O0_argslot,     __ delayed_value(java_dyn_MethodTypeForm::vmslots_offset_in_bytes, O1_scratch)), O0_argslot);
+  __ ld_ptr(__ argument_address(O0_argslot), G3_method_handle);
+  __ check_method_handle_type(G5_method_type, G3_method_handle, O1_scratch, wrong_method_type);
+  __ load_heap_oop(Address(O0_mtype,   __ delayed_value(java_dyn_MethodType::form_offset_in_bytes,        O1_scratch)), O4_argslot);
+  __ ldsw(         Address(O4_argslot, __ delayed_value(java_dyn_MethodTypeForm::vmslots_offset_in_bytes, O1_scratch)), O4_argslot);
+  __ add(Gargs, __ argument_offset(O4_argslot, 1), O4_argbase);
+  // Note: argument_address uses its input as a scratch register!
+  __ ld_ptr(Address(O4_argbase, -Interpreter::stackElementSize), G3_method_handle);
+  trace_method_handle(_masm, "invokeExact");
+  __ check_method_handle_type(O0_mtype, G3_method_handle, O1_scratch, wrong_method_type);
   __ jump_to_method_handle_entry(G3_method_handle, O1_scratch);
+  // for invokeGeneric (only), apply argument and result conversions on the fly
+  __ bind(invoke_generic_slow_path);
+#ifdef ASSERT
+  { Label L;
+    __ ldub(Address(G5_method, methodOopDesc::intrinsic_id_offset_in_bytes()), O1_scratch);
+    __ cmp(O1_scratch, (int) vmIntrinsics::_invokeGeneric);
+    __ brx(Assembler::equal, false, Assembler::pt, L);
+    __ delayed()->nop();
+    __ stop("bad methodOop::intrinsic_id");
+    __ bind(L);
+  }
+#endif //ASSERT
+  // make room on the stack for another pointer:
+  insert_arg_slots(_masm, 2 * stack_move_unit(), _INSERT_REF_MASK, O4_argbase, O1_scratch, O2_scratch, O3_scratch);
+  // load up an adapter from the calling type (Java weaves this)
+  Register O2_form    = O2_scratch;
+  Register O3_adapter = O3_scratch;
+  __ load_heap_oop(Address(O0_mtype, __ delayed_value(java_dyn_MethodType::form_offset_in_bytes,               O1_scratch)), O2_form);
+  // load_heap_oop(Address(O2_form,  __ delayed_value(java_dyn_MethodTypeForm::genericInvoker_offset_in_bytes, O1_scratch)), O3_adapter);
+  // deal with old JDK versions:
+  __ add(          Address(O2_form,  __ delayed_value(java_dyn_MethodTypeForm::genericInvoker_offset_in_bytes, O1_scratch)), O3_adapter);
+  __ cmp(O3_adapter, O2_form);
+  Label sorry_no_invoke_generic;
+  __ brx(Assembler::lessUnsigned, false, Assembler::pn, sorry_no_invoke_generic);
+  __ delayed()->nop();
+  __ load_heap_oop(Address(O3_adapter, 0), O3_adapter);
+  __ tst(O3_adapter);
+  __ brx(Assembler::zero, false, Assembler::pn, sorry_no_invoke_generic);
+  __ delayed()->nop();
+  __ st_ptr(O3_adapter, Address(O4_argbase, 1 * Interpreter::stackElementSize));
+  // As a trusted first argument, pass the type being called, so the adapter knows
+  // the actual types of the arguments and return values.
+  // (Generic invokers are shared among form-families of method-type.)
+  __ st_ptr(O0_mtype,   Address(O4_argbase, 0 * Interpreter::stackElementSize));
+  // FIXME: assert that O3_adapter is of the right method-type.
+  __ mov(O3_adapter, G3_method_handle);
+  trace_method_handle(_masm, "invokeGeneric");
+  __ jump_to_method_handle_entry(G3_method_handle, O1_scratch);
+  __ bind(sorry_no_invoke_generic); // no invokeGeneric implementation available!
+  __ mov(O0_mtype, G5_method_type);  // required by throw_WrongMethodType
+  // mov(G3_method_handle, G3_method_handle);  // already in this register
+  __ jump_to(AddressLiteral(Interpreter::throw_WrongMethodType_entry()), O1_scratch);
+  __ delayed()->nop();
   return entry_point;
 …
   // Verify that argslot lies within (Gargs, FP].
   Label L_ok, L_bad;
+  BLOCK_COMMENT("{ verify_argslot");
 #ifdef _LP64
   __ add(FP, STACK_BIAS, temp_reg);
 …
   __ stop(error_message);
   __ bind(L_ok);
+  BLOCK_COMMENT("} verify_argslot");
+}
 #endif
 …
   //     temp[-size] = temp[0]
   //   argslot -= size;
+  BLOCK_COMMENT("insert_arg_slots {");
   RegisterOrConstant offset = __ regcon_sll_ptr(arg_slots, LogBytesPerWord, temp3_reg);
 …
+  {
     Label loop;
     __ bind(loop);
+    __ BIND(loop);
     // pull one word down each time through the loop
     __ ld_ptr(Address(temp_reg, 0), temp2_reg);
 …
   // Now move the argslot down, to point to the opened-up space.
   __ add(argslot_reg, offset, argslot_reg);
+  BLOCK_COMMENT("} insert_arg_slots");
+}
 …
 #endif // ASSERT
+  BLOCK_COMMENT("remove_arg_slots {");
   // Pull up everything shallower than argslot.
   // Then remove the excess space on the stack.
 …
+  {
     Label loop;
     __ bind(loop);
+    __ BIND(loop);
     // pull one word up each time through the loop
     __ ld_ptr(Address(temp_reg, 0), temp2_reg);
 …
   RegisterOrConstant masked_offset = __ regcon_andn_ptr(offset, TwoWordAlignmentMask, temp_reg);
   __ add(SP, masked_offset, SP);
+  BLOCK_COMMENT("} remove_arg_slots");
+}
 …
 extern "C" void print_method_handle(oop mh);
 void trace_method_handle_stub(const char* adaptername,
+                              oop mh) {
+#if 0
+                              intptr_t* entry_sp,
+                              intptr_t* saved_sp,
+                              intptr_t* saved_bp) {
+  // called as a leaf from native code: do not block the JVM!
+  intptr_t* last_sp = (intptr_t*) saved_bp[frame::interpreter_frame_last_sp_offset];
+  intptr_t* base_sp = (intptr_t*) saved_bp[frame::interpreter_frame_monitor_block_top_offset];
+  printf("MH %s mh="INTPTR_FORMAT" sp=("INTPTR_FORMAT"+"INTX_FORMAT") stack_size="INTX_FORMAT" bp="INTPTR_FORMAT"\n",
+         adaptername, (intptr_t)mh, (intptr_t)entry_sp, (intptr_t)(saved_sp - entry_sp), (intptr_t)(base_sp - last_sp), (intptr_t)saved_bp);
+  if (last_sp != saved_sp)
+    printf("*** last_sp="INTPTR_FORMAT"\n", (intptr_t)last_sp);
+#endif
+                              oopDesc* mh) {
   printf("MH %s mh="INTPTR_FORMAT"\n", adaptername, (intptr_t) mh);
   print_method_handle(mh);
+}
+void MethodHandles::trace_method_handle(MacroAssembler* _masm, const char* adaptername) {
+  if (!TraceMethodHandles)  return;
+  BLOCK_COMMENT("trace_method_handle {");
+  // save: Gargs, O5_savedSP
+  __ save_frame(16);
+  __ set((intptr_t) adaptername, O0);
+  __ mov(G3_method_handle, O1);
+  __ mov(G3_method_handle, L3);
+  __ mov(Gargs, L4);
+  __ mov(G5_method_type, L5);
+  __ call_VM_leaf(L7, CAST_FROM_FN_PTR(address, trace_method_handle_stub));
+  __ mov(L3, G3_method_handle);
+  __ mov(L4, Gargs);
+  __ mov(L5, G5_method_type);
+  __ restore();
+  BLOCK_COMMENT("} trace_method_handle");
+}
 #endif // PRODUCT
 …
   // - O5_savedSP: sender SP (must preserve)
+  Register O0_argslot = O0;
+  Register O1_scratch = O1;
+  Register O2_scratch = O2;
+  Register O3_scratch = O3;
+  Register G5_index   = G5;
+  const Register O0_argslot = O0;
+  const Register O1_scratch = O1;
+  const Register O2_scratch = O2;
+  const Register O3_scratch = O3;
+  const Register G5_index   = G5;
+  // Argument registers for _raise_exception.
+  const Register O0_code     = O0;
+  const Register O1_actual   = O1;
+  const Register O2_required = O2;
   guarantee(java_dyn_MethodHandle::vmentry_offset_in_bytes() != 0, "must have offsets");
 …
   address interp_entry = __ pc();
+  if (UseCompressedOops)  __ unimplemented("UseCompressedOops");
+#ifndef PRODUCT
+  if (TraceMethodHandles) {
+    // save: Gargs, O5_savedSP
+    __ save(SP, -16*wordSize, SP);
+    __ set((intptr_t) entry_name(ek), O0);
+    __ mov(G3_method_handle, O1);
+    __ call_VM_leaf(Lscratch, CAST_FROM_FN_PTR(address, trace_method_handle_stub));
+    __ restore(SP, 16*wordSize, SP);
+  }
+#endif // PRODUCT
+  trace_method_handle(_masm, entry_name(ek));
   switch ((int) ek) {
 …
+    {
       // Not a real MH entry, but rather shared code for raising an
+      // exception.  Extra local arguments are passed in scratch
+      // registers, as required type in O3, failing object (or NULL)
+      // in O2, failing bytecode type in O1.
+      // exception.  Since we use a C2I adapter to set up the
+      // interpreter state, arguments are expected in compiler
+      // argument registers.
+      assert(raise_exception_method(), "must be set");
+      address c2i_entry = raise_exception_method()->get_c2i_entry();
+      assert(c2i_entry, "method must be linked");
       __ mov(O5_savedSP, SP);  // Cut the stack back to where the caller started.
+      // Push arguments as if coming from the interpreter.
+      Register O0_scratch = O0_argslot;
+      int stackElementSize = Interpreter::stackElementSize;
+      // Make space on the stack for the arguments and set Gargs
+      // correctly.
+      __ sub(SP, 4*stackElementSize, SP);  // Keep stack aligned.
+      __ add(SP, (frame::varargs_offset)*wordSize - 1*Interpreter::stackElementSize + STACK_BIAS + BytesPerWord, Gargs);
+      // void raiseException(int code, Object actual, Object required)
+      __ st(    O1_scratch, Address(Gargs, 2*stackElementSize));  // code
+      __ st_ptr(O2_scratch, Address(Gargs, 1*stackElementSize));  // actual
+      __ st_ptr(O3_scratch, Address(Gargs, 0*stackElementSize));  // required
+      Label no_method;
+      Label L_no_method;
       // FIXME: fill in _raise_exception_method with a suitable sun.dyn method
       __ set(AddressLiteral((address) &_raise_exception_method), G5_method);
       __ ld_ptr(Address(G5_method, 0), G5_method);
       __ tst(G5_method);
       __ brx(Assembler::zero, false, Assembler::pn, no_method);
+      __ brx(Assembler::zero, false, Assembler::pn, L_no_method);
       __ delayed()->nop();
       int jobject_oop_offset = 0;
+      const int jobject_oop_offset = 0;
       __ ld_ptr(Address(G5_method, jobject_oop_offset), G5_method);
       __ tst(G5_method);
       __ brx(Assembler::zero, false, Assembler::pn, no_method);
+      __ brx(Assembler::zero, false, Assembler::pn, L_no_method);
       __ delayed()->nop();
       __ verify_oop(G5_method);
       __ jump_indirect_to(G5_method_fie, O1_scratch);
+      __ jump_to(AddressLiteral(c2i_entry), O3_scratch);
       __ delayed()->nop();
       // If we get here, the Java runtime did not do its job of creating the exception.
       // Do something that is at least causes a valid throw from the interpreter.
       __ bind(no_method);
       __ unimplemented("_raise_exception no method");
+      __ bind(L_no_method);
+      __ unimplemented("call throw_WrongMethodType_entry");
+    }
     break;
 …
   case _invokespecial_mh:
+    {
       __ ld_ptr(G3_mh_vmtarget, G5_method);  // target is a methodOop
+      __ load_heap_oop(G3_mh_vmtarget, G5_method);  // target is a methodOop
       __ verify_oop(G5_method);
       // Same as TemplateTable::invokestatic or invokespecial,
 …
       __ load_method_handle_vmslots(O0_argslot, G3_method_handle, O1_scratch);
       Register O1_intf  = O1_scratch;
       __ ld_ptr(G3_mh_vmtarget, O1_intf);
+      __ load_heap_oop(G3_mh_vmtarget, O1_intf);
       __ ldsw(G3_dmh_vmindex, G5_index);
       __ ld_ptr(__ argument_address(O0_argslot, -1), G3_method_handle);
 …
       // For historical reasons, it will be IncompatibleClassChangeError.
       __ unimplemented("not tested yet");
       __ ld_ptr(Address(O1_intf, java_mirror_offset), O3_scratch);  // required interface
       __ mov(O0_klass, O2_scratch);  // bad receiver
       __ jump_to(AddressLiteral(from_interpreted_entry(_raise_exception)), O0_argslot);
       __ delayed()->mov(Bytecodes::_invokeinterface, O1_scratch);  // who is complaining?
+      __ ld_ptr(Address(O1_intf, java_mirror_offset), O2_required);  // required interface
+      __ mov(   O0_klass,                             O1_actual);    // bad receiver
+      __ jump_to(AddressLiteral(from_interpreted_entry(_raise_exception)), O3_scratch);
+      __ delayed()->mov(Bytecodes::_invokeinterface,  O0_code);      // who is complaining?
+    }
     break;
 …
       // Store bound argument into the new stack slot:
       __ ld_ptr(G3_bmh_argument, O1_scratch);
+      __ load_heap_oop(G3_bmh_argument, O1_scratch);
       if (arg_type == T_OBJECT) {
         __ st_ptr(O1_scratch, Address(O0_argslot, 0));
 …
       if (direct_to_method) {
         __ ld_ptr(G3_mh_vmtarget, G5_method);  // target is a methodOop
+        __ load_heap_oop(G3_mh_vmtarget, G5_method);  // target is a methodOop
         __ verify_oop(G5_method);
         __ jump_indirect_to(G5_method_fie, O1_scratch);
         __ delayed()->nop();
       } else {
         __ ld_ptr(G3_mh_vmtarget, G3_method_handle);  // target is a methodOop
+        __ load_heap_oop(G3_mh_vmtarget, G3_method_handle);  // target is a methodOop
         __ verify_oop(G3_method_handle);
         __ jump_to_method_handle_entry(G3_method_handle, O1_scratch);
 …
   case _adapter_retype_raw:
     // Immediately jump to the next MH layer:
     __ ld_ptr(G3_mh_vmtarget, G3_method_handle);
+    __ load_heap_oop(G3_mh_vmtarget, G3_method_handle);
     __ jump_to_method_handle_entry(G3_method_handle, O1_scratch);
     // This is OK when all parameter types widen.
 …
       // What class are we casting to?
       __ ld_ptr(G3_amh_argument, G5_klass);  // This is a Class object!
       __ ld_ptr(Address(G5_klass, java_lang_Class::klass_offset_in_bytes()), G5_klass);
+      __ load_heap_oop(G3_amh_argument, G5_klass);  // This is a Class object!
+      __ load_heap_oop(Address(G5_klass, java_lang_Class::klass_offset_in_bytes()), G5_klass);
       Label done;
 …
       // If we get here, the type check failed!
+      __ ldsw(G3_amh_vmargslot, O0_argslot);  // reload argslot field
+      __ ld_ptr(G3_amh_argument, O3_scratch);  // required class
+      __ ld_ptr(vmarg, O2_scratch);  // bad object
+      __ jump_to(AddressLiteral(from_interpreted_entry(_raise_exception)), O0_argslot);
+      __ delayed()->mov(Bytecodes::_checkcast, O1_scratch);  // who is complaining?
+      __ load_heap_oop(G3_amh_argument,        O2_required);  // required class
+      __ ld_ptr(       vmarg,                  O1_actual);    // bad object
+      __ jump_to(AddressLiteral(from_interpreted_entry(_raise_exception)), O3_scratch);
+      __ delayed()->mov(Bytecodes::_checkcast, O0_code);      // who is complaining?
       __ bind(done);
       // Get the new MH:
       __ ld_ptr(G3_mh_vmtarget, G3_method_handle);
+      __ load_heap_oop(G3_mh_vmtarget, G3_method_handle);
       __ jump_to_method_handle_entry(G3_method_handle, O1_scratch);
+    }
 …
       // Perform an in-place conversion to int or an int subword.
       __ ldsw(G3_amh_vmargslot, O0_argslot);
+      Address value;
       Address vmarg = __ argument_address(O0_argslot);
-      Address value;
       bool value_left_justified = false;
       switch (ek) {
       case _adapter_opt_i2i:
+        value = vmarg;
+        break;
       case _adapter_opt_l2i:
+        __ unimplemented(entry_name(ek));
+        value = vmarg;
+        {
+          // just delete the extra slot
+#ifdef _LP64
+          // In V9, longs are given 2 64-bit slots in the interpreter, but the
+          // data is passed in only 1 slot.
+          // Keep the second slot.
+          __ add(Gargs, __ argument_offset(O0_argslot, -1), O0_argslot);
+          remove_arg_slots(_masm, -stack_move_unit(), O0_argslot, O1_scratch, O2_scratch, O3_scratch);
+          value = Address(O0_argslot, 4);  // Get least-significant 32-bit of 64-bit value.
+          vmarg = Address(O0_argslot, Interpreter::stackElementSize);
+#else
+          // Keep the first slot.
+          __ add(Gargs, __ argument_offset(O0_argslot), O0_argslot);
+          remove_arg_slots(_masm, -stack_move_unit(), O0_argslot, O1_scratch, O2_scratch, O3_scratch);
+          value = Address(O0_argslot, 0);
+          vmarg = value;
+#endif
+        }
         break;
       case _adapter_opt_unboxi:
 …
       // Get the new MH:
       __ ld_ptr(G3_mh_vmtarget, G3_method_handle);
+      __ load_heap_oop(G3_mh_vmtarget, G3_method_handle);
       __ jump_to_method_handle_entry(G3_method_handle, O1_scratch);
+    }
 …
+      }
       __ ld_ptr(G3_mh_vmtarget, G3_method_handle);
+      __ load_heap_oop(G3_mh_vmtarget, G3_method_handle);
       __ jump_to_method_handle_entry(G3_method_handle, O1_scratch);
+    }
 …
+      }
       __ ld_ptr(G3_mh_vmtarget, G3_method_handle);
+      __ load_heap_oop(G3_mh_vmtarget, G3_method_handle);
       __ jump_to_method_handle_entry(G3_method_handle, O1_scratch);
+    }
 …
       __ delayed()->nop();  // FILLME
       __ ld_ptr(G3_mh_vmtarget, G3_method_handle);
+      __ load_heap_oop(G3_mh_vmtarget, G3_method_handle);
       __ jump_to_method_handle_entry(G3_method_handle, O1_scratch);
+    }
 …
       remove_arg_slots(_masm, G5_stack_move, O0_argslot, O1_scratch, O2_scratch, O3_scratch);
       __ ld_ptr(G3_mh_vmtarget, G3_method_handle);
+      __ load_heap_oop(G3_mh_vmtarget, G3_method_handle);
       __ jump_to_method_handle_entry(G3_method_handle, O1_scratch);
+    }

trunk/openjdk/hotspot/src/cpu/sparc/vm/nativeInst_sparc.cpp

-              r278
+              r309
  */
+# include "incls/_precompiled.incl"
+# include "incls/_nativeInst_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "assembler_sparc.inline.hpp"
+#include "memory/resourceArea.hpp"
+#include "nativeInst_sparc.hpp"
+#include "oops/oop.inline.hpp"
+#include "runtime/handles.hpp"
+#include "runtime/sharedRuntime.hpp"
+#include "runtime/stubRoutines.hpp"
+#include "utilities/ostream.hpp"
+#ifdef COMPILER1
+#include "c1/c1_Runtime1.hpp"
+#endif
 …
   a->call( a->pc(), relocInfo::none );
   a->delayed()->nop();
   nc = nativeCall_at( cb.code_begin() );
+  nc = nativeCall_at( cb.insts_begin() );
   nc->print();
   nc = nativeCall_overwriting_at( nc->next_instruction_address() );
   for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
     nc->set_destination( cb.code_begin() + offsets[idx] );
     assert(nc->destination() == (cb.code_begin() + offsets[idx]), "check unit test");
+    nc->set_destination( cb.insts_begin() + offsets[idx] );
+    assert(nc->destination() == (cb.insts_begin() + offsets[idx]), "check unit test");
     nc->print();
+  }
   nc = nativeCall_before( cb.code_begin() + 8 );
+  nc = nativeCall_before( cb.insts_begin() + 8 );
   nc->print();
 …
   a->add(O2, al2.low10(), O2);
   nm = nativeMovConstReg_at( cb.code_begin() );
+  nm = nativeMovConstReg_at( cb.insts_begin() );
   nm->print();
 …
   a->add(O2, al2.low10(), O2);
   nm = nativeMovConstRegPatching_at( cb.code_begin() );
+  nm = nativeMovConstRegPatching_at( cb.insts_begin() );
   nm->print();
 …
   a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++;
   nm = nativeMovRegMem_at( cb.code_begin() );
+  nm = nativeMovRegMem_at( cb.insts_begin() );
   nm->print();
   nm->set_offset( low10(0) );
 …
   a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++;
   nm = nativeMovRegMemPatching_at( cb.code_begin() );
+  nm = nativeMovRegMemPatching_at( cb.insts_begin() );
   nm->print();
   nm->set_offset( low10(0) );
 …
   a->delayed()->nop();
   nj = nativeJump_at( cb.code_begin() );
+  nj = nativeJump_at( cb.insts_begin() );
   nj->print();

trunk/openjdk/hotspot/src/cpu/sparc/vm/nativeInst_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2008, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_NATIVEINST_SPARC_HPP
+#define CPU_SPARC_VM_NATIVEINST_SPARC_HPP
+#include "asm/assembler.hpp"
+#include "memory/allocation.hpp"
+#include "runtime/icache.hpp"
+#include "runtime/os.hpp"
+#include "utilities/top.hpp"
 // We have interface for the following instructions:
 …
   static void insert(address code_pos);
 };
+#endif // CPU_SPARC_VM_NATIVEINST_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/registerMap_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1998, 2007, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_REGISTERMAP_SPARC_HPP
+#define CPU_SPARC_VM_REGISTERMAP_SPARC_HPP
 // machine-dependent implemention for register maps
 …
   // When popping out of compiled frames, we make all IRegs disappear.
   void make_integer_regs_unsaved() { _location_valid[0] = 0; }
+#endif // CPU_SPARC_VM_REGISTERMAP_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/register_definitions_sparc.cpp

-              r278
+              r309
 #define DONT_USE_REGISTER_DEFINES
+#include "incls/_precompiled.incl"
+#include "incls/_register_definitions_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "asm/assembler.hpp"
+#include "asm/register.hpp"
+#include "interp_masm_sparc.hpp"
+#include "register_sparc.hpp"
 REGISTER_DEFINITION(Register, noreg);

trunk/openjdk/hotspot/src/cpu/sparc/vm/register_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 2000, 2007, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
 #include "incls/_precompiled.incl"
 #include "incls/_register_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "register_sparc.hpp"
 const int ConcreteRegisterImpl::max_gpr = RegisterImpl::number_of_registers << 1;

trunk/openjdk/hotspot/src/cpu/sparc/vm/register_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2000, 2007, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_REGISTER_SPARC_HPP
+#define CPU_SPARC_VM_REGISTER_SPARC_HPP
+#include "asm/register.hpp"
+#include "vm_version_sparc.hpp"
 // forward declaration
 …
+  }
 };
+#endif // CPU_SPARC_VM_REGISTER_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/relocInfo_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 1998, 2009, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+# include "incls/_precompiled.incl"
+# include "incls/_relocInfo_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "asm/assembler.inline.hpp"
+#include "assembler_sparc.inline.hpp"
+#include "code/relocInfo.hpp"
+#include "nativeInst_sparc.hpp"
+#include "oops/oop.inline.hpp"
+#include "runtime/safepoint.hpp"
 void Relocation::pd_set_data_value(address x, intptr_t o) {

trunk/openjdk/hotspot/src/cpu/sparc/vm/relocInfo_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2008, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_RELOCINFO_SPARC_HPP
+#define CPU_SPARC_VM_RELOCINFO_SPARC_HPP
   // machine-dependent parts of class relocInfo
 …
 // 1.9 99/07/16 11:12:11 relocInfo_i486.hpp
 //End
+#endif // CPU_SPARC_VM_RELOCINFO_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/runtime_sparc.cpp

-              r278
+              r309
  */
+#include "incls/_precompiled.incl"
+#include "incls/_runtime_sparc.cpp.incl"
+#include "precompiled.hpp"
+#ifdef COMPILER2
+#include "asm/assembler.hpp"
+#include "assembler_sparc.inline.hpp"
+#include "classfile/systemDictionary.hpp"
+#include "code/vmreg.hpp"
+#include "interpreter/interpreter.hpp"
+#include "nativeInst_sparc.hpp"
+#include "opto/runtime.hpp"
+#include "runtime/interfaceSupport.hpp"
+#include "runtime/sharedRuntime.hpp"
+#include "runtime/stubRoutines.hpp"
+#include "runtime/vframeArray.hpp"
+#include "utilities/globalDefinitions.hpp"
+#include "vmreg_sparc.inline.hpp"
+#endif

trunk/openjdk/hotspot/src/cpu/sparc/vm/sharedRuntime_sparc.cpp

-              r278
+              r309
  */
+#include "incls/_precompiled.incl"
+#include "incls/_sharedRuntime_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "asm/assembler.hpp"
+#include "assembler_sparc.inline.hpp"
+#include "code/debugInfoRec.hpp"
+#include "code/icBuffer.hpp"
+#include "code/vtableStubs.hpp"
+#include "interpreter/interpreter.hpp"
+#include "oops/compiledICHolderOop.hpp"
+#include "prims/jvmtiRedefineClassesTrace.hpp"
+#include "runtime/sharedRuntime.hpp"
+#include "runtime/vframeArray.hpp"
+#include "vmreg_sparc.inline.hpp"
+#ifdef COMPILER1
+#include "c1/c1_Runtime1.hpp"
+#endif
+#ifdef COMPILER2
+#include "opto/runtime.hpp"
+#endif
+#ifdef SHARK
+#include "compiler/compileBroker.hpp"
+#include "shark/sharkCompiler.hpp"
+#endif
 #define __ masm->
 …
 #if !defined(_LP64)
 #if defined(COMPILER2)
+  if (!TieredCompilation) {
+    // 32-bit 1-register longs return longs in G1
+    __ stx(Greturn1, saved_Greturn1_addr);
+  }
+  // 32-bit 1-register longs return longs in G1
+  __ stx(Greturn1, saved_Greturn1_addr);
 #endif
   __ set_last_Java_frame(SP, noreg);
 …
   __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0);
-  // In tiered we never use C2 to compile methods returning longs so
-  // the result is where we expect it already.
 #if !defined(_LP64) && defined(COMPILER2)
   // In 32 bit, C2 returns longs in G1 so restore the saved G1 into
+  // I0/I1 if the return value is long.  In the tiered world there is
+  // a mismatch between how C1 and C2 return longs compiles and so
+  // currently compilation of methods which return longs is disabled
+  // for C2 and so is this code.  Eventually C1 and C2 will do the
+  // same thing for longs in the tiered world.
+  if (!TieredCompilation) {
+    Label not_long;
+    __ cmp(O0,T_LONG);
+    __ br(Assembler::notEqual, false, Assembler::pt, not_long);
+    __ delayed()->nop();
+    __ ldd(saved_Greturn1_addr,I0);
+    __ bind(not_long);
+  }
+  // I0/I1 if the return value is long.
+  Label not_long;
+  __ cmp(O0,T_LONG);
+  __ br(Assembler::notEqual, false, Assembler::pt, not_long);
+  __ delayed()->nop();
+  __ ldd(saved_Greturn1_addr,I0);
+  __ bind(not_long);
 #endif
   __ ret();

trunk/openjdk/hotspot/src/cpu/sparc/vm/sparc.ad

-              r278
+              r309
 //
 // Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved.
+// Copyright (c) 1998, 2011, Oracle and/or its affiliates. All rights reserved.
 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 //
 …
 int MachCallRuntimeNode::ret_addr_offset() {
 #ifdef _LP64
+  return NativeFarCall::instruction_size;  // farcall; delay slot
+  if (MacroAssembler::is_far_target(entry_point())) {
+    return NativeFarCall::instruction_size;
+  } else {
+    return NativeCall::instruction_size;
+  }
 #else
   return NativeCall::instruction_size;  // call; delay slot
 …
+}
+static inline jdouble replicate_immI(int con, int count, int width) {
+  // Load a constant replicated "count" times with width "width"
+  int bit_width = width * 8;
+  jlong elt_val = con;
+  elt_val &= (((jlong) 1) << bit_width) - 1;  // mask off sign bits
+  jlong val = elt_val;
+  for (int i = 0; i < count - 1; i++) {
+    val <<= bit_width;
+    val |= elt_val;
+  }
+  jdouble dval = *((jdouble*) &val);  // coerce to double type
+  return dval;
+}
 // Standard Sparc opcode form2 field breakdown
 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
 …
            (f19 << 19) |
            (f0  <<  0);
+  *((int*)(cbuf.code_end())) = op;
+  cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+  cbuf.insts()->emit_int32(op);
+}
 …
            (f22 << 22) |
            (f0  <<  0);
+  *((int*)(cbuf.code_end())) = op;
+  cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+  cbuf.insts()->emit_int32(op);
+}
 …
            (f5  <<  5) |
            (f0  <<  0);
+  *((int*)(cbuf.code_end())) = op;
+  cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+  cbuf.insts()->emit_int32(op);
+}
 …
            (1   << 13) | // bit to indicate immediate-mode
            (simm13<<0);
+  *((int*)(cbuf.code_end())) = op;
+  cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+  cbuf.insts()->emit_int32(op);
+}
 …
+  }
+  uint *code = (uint*)cbuf.code_end();
+  *code = instr;
+  cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+  cbuf.insts()->emit_int32(instr);
 #ifdef ASSERT
 …
+}
 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
+void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
   // The method which records debug information at every safepoint
   // expects the call to be the first instruction in the snippet as
 …
 #endif /* ASSERT */
+#ifdef _LP64
+  // Calls to the runtime or native may not be reachable from compiled code,
+  // so we generate the far call sequence on 64 bit sparc.
+  // This code sequence is relocatable to any address, even on LP64.
+  if ( force_far_call ) {
+    __ relocate(rtype);
+    AddressLiteral dest(entry_point);
+    __ jumpl_to(dest, O7, O7);
+  }
+  else
+#endif
+  {
+     __ call((address)entry_point, rtype);
+  }
+  __ call((address)entry_point, rtype);
   if (preserve_g2)   __ delayed()->mov(G2, L7);
 …
 //=============================================================================
+const bool Matcher::constant_table_absolute_addressing = false;
+const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask;
+void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
+  Compile* C = ra_->C;
+  Compile::ConstantTable& constant_table = C->constant_table();
+  MacroAssembler _masm(&cbuf);
+  Register r = as_Register(ra_->get_encode(this));
+  CodeSection* cs = __ code()->consts();
+  int consts_size = cs->align_at_start(cs->size());
+  if (UseRDPCForConstantTableBase) {
+    // For the following RDPC logic to work correctly the consts
+    // section must be allocated right before the insts section.  This
+    // assert checks for that.  The layout and the SECT_* constants
+    // are defined in src/share/vm/asm/codeBuffer.hpp.
+    assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
+    int offset = __ offset();
+    int disp;
+    // If the displacement from the current PC to the constant table
+    // base fits into simm13 we set the constant table base to the
+    // current PC.
+    if (__ is_simm13(-(consts_size + offset))) {
+      constant_table.set_table_base_offset(-(consts_size + offset));
+      disp = 0;
+    } else {
+      // If the offset of the top constant (last entry in the table)
+      // fits into simm13 we set the constant table base to the actual
+      // table base.
+      if (__ is_simm13(constant_table.top_offset())) {
+        constant_table.set_table_base_offset(0);
+        disp = consts_size + offset;
+      } else {
+        // Otherwise we set the constant table base in the middle of the
+        // constant table.
+        int half_consts_size = consts_size / 2;
+        assert(half_consts_size * 2 == consts_size, "sanity");
+        constant_table.set_table_base_offset(-half_consts_size);  // table base offset gets added to the load displacement.
+        disp = half_consts_size + offset;
+      }
+    }
+    __ rdpc(r);
+    if (disp != 0) {
+      assert(r != O7, "need temporary");
+      __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
+    }
+  }
+  else {
+    // Materialize the constant table base.
+    assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
+    address baseaddr = cs->start() + -(constant_table.table_base_offset());
+    RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
+    AddressLiteral base(baseaddr, rspec);
+    __ set(base, r);
+  }
+}
+uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
+  if (UseRDPCForConstantTableBase) {
+    // This is really the worst case but generally it's only 1 instruction.
+    return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
+  } else {
+    return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
+  }
+}
+#ifndef PRODUCT
+void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
+  char reg[128];
+  ra_->dump_register(this, reg);
+  if (UseRDPCForConstantTableBase) {
+    st->print("RDPC   %s\t! constant table base", reg);
+  } else {
+    st->print("SET    &constanttable,%s\t! constant table base", reg);
+  }
+}
+#endif
+//=============================================================================
 #ifndef PRODUCT
 …
 int MachEpilogNode::safepoint_offset() const {
   assert( do_polling(), "no return for this epilog node");
   return MacroAssembler::size_of_sethi(os::get_polling_page());
+  return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
+}
 …
   // jmp -1
   address mark = cbuf.inst_mark();  // get mark within main instrs section
+  address mark = cbuf.insts_mark();  // get mark within main instrs section
   MacroAssembler _masm(&cbuf);
 …
 int emit_exception_handler(CodeBuffer& cbuf) {
   Register temp_reg = G3;
   AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin());
+  AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
   MacroAssembler _masm(&cbuf);
 …
 bool Matcher::is_spillable_arg( int reg ) {
   return can_be_java_arg(reg);
+}
+bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
+  // Use hardware SDIVX instruction when it is
+  // faster than a code which use multiply.
+  return VM_Version::has_fast_idiv();
+}
 …
   %}
-  enc_class jump_enc( iRegX switch_val, o7RegI table) %{
-    MacroAssembler _masm(&cbuf);
-    Register switch_reg       = as_Register($switch_val$$reg);
-    Register table_reg        = O7;
-    address table_base = __ address_table_constant(_index2label);
-    RelocationHolder rspec = internal_word_Relocation::spec(table_base);
-    // Move table address into a register.
-    __ set(table_base, table_reg, rspec);
-    // Jump to base address + switch value
-    __ ld_ptr(table_reg, switch_reg, table_reg);
-    __ jmp(table_reg, G0);
-    __ delayed()->nop();
-  %}
   enc_class enc_ba( Label labl ) %{
     MacroAssembler _masm(&cbuf);
 …
              ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc' or 'xcc'
              ($src$$reg << 0);
+    *((int*)(cbuf.code_end())) = op;
+    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+    cbuf.insts()->emit_int32(op);
   %}
 …
              ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc'
              (simm11 << 0);
+    *((int*)(cbuf.code_end())) = op;
+    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+    cbuf.insts()->emit_int32(op);
   %}
 …
              ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
              ($src$$reg << 0);
+    *((int*)(cbuf.code_end())) = op;
+    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+    cbuf.insts()->emit_int32(op);
   %}
 …
              ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
              (simm11 << 0);
+    *((int*)(cbuf.code_end())) = op;
+    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+    cbuf.insts()->emit_int32(op);
   %}
 …
              ($primary << 5) |              // select single, double or quad
              ($src$$reg << 0);
+    *((int*)(cbuf.code_end())) = op;
+    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+    cbuf.insts()->emit_int32(op);
   %}
 …
              ($primary << 5) |              // select single, double or quad
              ($src$$reg << 0);
+    *((int*)(cbuf.code_end())) = op;
+    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+    cbuf.insts()->emit_int32(op);
   %}
 …
              (0 << 11) |                    // cc1, cc0 bits for 'icc'
              ($src$$reg << 0);
+    *((int*)(cbuf.code_end())) = op;
+    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+    cbuf.insts()->emit_int32(op);
   %}
 …
              (0 << 11) |                    // cc1, cc0 bits for 'icc'
              ($src$$reg << 0);
+    *((int*)(cbuf.code_end())) = op;
+    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+  %}
+  // Utility encoding for loading a 64 bit Pointer into a register
+  // The 64 bit pointer is stored in the generated code stream
+  enc_class SetPtr( immP src, iRegP rd ) %{
+    Register dest = reg_to_register_object($rd$$reg);
+    MacroAssembler _masm(&cbuf);
+    // [RGV] This next line should be generated from ADLC
+    if ( _opnds[1]->constant_is_oop() ) {
+      intptr_t val = $src$$constant;
+      __ set_oop_constant((jobject)val, dest);
+    } else {          // non-oop pointers, e.g. card mark base, heap top
+      __ set($src$$constant, dest);
+    }
+    cbuf.insts()->emit_int32(op);
   %}
 …
     MacroAssembler _masm(&cbuf);
     __ set($src$$constant, reg_to_register_object($rd$$reg));
-  %}
-  enc_class SetNull( iRegI rd ) %{
-    emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
   %}
 …
     // The user of this is responsible for ensuring that R_L7 is empty (killed).
     emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
                     /*preserve_g2=*/true, /*force far call*/true);
+                    /*preserve_g2=*/true);
   %}
 …
   %}
-  enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{   // Load Immediate
-    MacroAssembler _masm(&cbuf);
-    Register dest = reg_to_register_object($dst$$reg);
-    Register temp = reg_to_register_object($tmp$$reg);
-    __ set64( $src$$constant, dest, temp );
-  %}
-  enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
-    // Load a constant replicated "count" times with width "width"
-    int bit_width = $width$$constant * 8;
-    jlong elt_val = $src$$constant;
-    elt_val  &= (((jlong)1) << bit_width) - 1; // mask off sign bits
-    jlong val = elt_val;
-    for (int i = 0; i < $count$$constant - 1; i++) {
-        val <<= bit_width;
-        val |= elt_val;
+    }
-    jdouble dval = *(jdouble*)&val; // coerce to double type
-    MacroAssembler _masm(&cbuf);
-    address double_address = __ double_constant(dval);
-    RelocationHolder rspec = internal_word_Relocation::spec(double_address);
-    AddressLiteral addrlit(double_address, rspec);
-    __ sethi(addrlit, $tmp$$Register);
-    // XXX This is a quick fix for 6833573.
-    //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
-    __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
-  %}
   // Compiler ensures base is doubleword aligned and cnt is count of doublewords
   enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
 …
   enc_class enc_rethrow() %{
     cbuf.set_inst_mark();
+    cbuf.set_insts_mark();
     Register temp_reg = G3;
     AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
 …
   enc_class emit_mem_nop() %{
     // Generates the instruction LDUXA [o6,g0],#0x82,g0
+    unsigned int *code = (unsigned int*)cbuf.code_end();
+    *code = (unsigned int)0xc0839040;
+    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+    cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
   %}
   enc_class emit_fadd_nop() %{
     // Generates the instruction FMOVS f31,f31
+    unsigned int *code = (unsigned int*)cbuf.code_end();
+    *code = (unsigned int)0xbfa0003f;
+    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+    cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
   %}
   enc_class emit_br_nop() %{
     // Generates the instruction BPN,PN .
+    unsigned int *code = (unsigned int*)cbuf.code_end();
+    *code = (unsigned int)0x00400000;
+    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
+    cbuf.insts()->emit_int32((unsigned int) 0x00400000);
   %}
 …
 %}
+#ifdef _LP64
+// Pointer Immediate: 64-bit
+operand immP_set() %{
+  predicate(!VM_Version::is_niagara_plus());
+  match(ConP);
+  op_cost(5);
+  // formats are generated automatically for constants and base registers
+  format %{ %}
+  interface(CONST_INTER);
+%}
+// Pointer Immediate: 64-bit
+// From Niagara2 processors on a load should be better than materializing.
+operand immP_load() %{
+  predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
+  match(ConP);
+  op_cost(5);
+  // formats are generated automatically for constants and base registers
+  format %{ %}
+  interface(CONST_INTER);
+%}
+// Pointer Immediate: 64-bit
+operand immP_no_oop_cheap() %{
+  predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
+  match(ConP);
+  op_cost(5);
+  // formats are generated automatically for constants and base registers
+  format %{ %}
+  interface(CONST_INTER);
+%}
+#endif
 operand immP13() %{
   predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
 …
 operand immL_32bits() %{
   predicate(n->get_long() == 0xFFFFFFFFL);
+  match(ConL);
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+// Long Immediate: cheap (materialize in <= 3 instructions)
+operand immL_cheap() %{
+  predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
+  match(ConL);
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+// Long Immediate: expensive (materialize in > 3 instructions)
+operand immL_expensive() %{
+  predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
   match(ConL);
   op_cost(0);
 …
 %}
+instruct loadConP(iRegP dst, immP src) %{
+  match(Set dst src);
+#ifndef _LP64
+instruct loadConP(iRegP dst, immP con) %{
+  match(Set dst con);
   ins_cost(DEFAULT_COST * 3/2);
+  format %{ "SET    $src,$dst\t!ptr" %}
+  // This rule does not use "expand" unlike loadConI because then
+  // the result type is not known to be an Oop.  An ADLC
+  // enhancement will be needed to make that work - not worth it!
+  ins_encode( SetPtr( src, dst ) );
+  format %{ "SET    $con,$dst\t!ptr" %}
+  ins_encode %{
+    // [RGV] This next line should be generated from ADLC
+    if (_opnds[1]->constant_is_oop()) {
+      intptr_t val = $con$$constant;
+      __ set_oop_constant((jobject) val, $dst$$Register);
+    } else {          // non-oop pointers, e.g. card mark base, heap top
+      __ set($con$$constant, $dst$$Register);
+    }
+  %}
   ins_pipe(loadConP);
+%}
+%}
+#else
+instruct loadConP_set(iRegP dst, immP_set con) %{
+  match(Set dst con);
+  ins_cost(DEFAULT_COST * 3/2);
+  format %{ "SET    $con,$dst\t! ptr" %}
+  ins_encode %{
+    // [RGV] This next line should be generated from ADLC
+    if (_opnds[1]->constant_is_oop()) {
+      intptr_t val = $con$$constant;
+      __ set_oop_constant((jobject) val, $dst$$Register);
+    } else {          // non-oop pointers, e.g. card mark base, heap top
+      __ set($con$$constant, $dst$$Register);
+    }
+  %}
+  ins_pipe(loadConP);
+%}
+instruct loadConP_load(iRegP dst, immP_load con) %{
+  match(Set dst con);
+  ins_cost(MEMORY_REF_COST);
+  format %{ "LD     [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
+  ins_encode %{
+    RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
+    __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
+  %}
+  ins_pipe(loadConP);
+%}
+instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
+  match(Set dst con);
+  ins_cost(DEFAULT_COST * 3/2);
+  format %{ "SET    $con,$dst\t! non-oop ptr" %}
+  ins_encode %{
+    __ set($con$$constant, $dst$$Register);
+  %}
+  ins_pipe(loadConP);
+%}
+#endif // _LP64
 instruct loadConP0(iRegP dst, immP0 src) %{
 …
   size(4);
   format %{ "CLR    $dst\t!ptr" %}
+  ins_encode( SetNull( dst ) );
+  ins_encode %{
+    __ clr($dst$$Register);
+  %}
   ins_pipe(ialu_imm);
 %}
 …
   size(4);
   format %{ "CLR    $dst\t! compressed NULL ptr" %}
+  ins_encode( SetNull( dst ) );
+  ins_encode %{
+    __ clr($dst$$Register);
+  %}
   ins_pipe(ialu_imm);
 %}
 …
 %}
+instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
+  // %%% maybe this should work like loadConD
   match(Set dst src);
+// Materialize long value (predicated by immL_cheap).
+instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
+  match(Set dst con);
   effect(KILL tmp);
+  ins_cost(DEFAULT_COST * 4);
+  format %{ "SET64   $src,$dst KILL $tmp\t! long" %}
+  ins_encode( LdImmL(src, dst, tmp) );
+  ins_cost(DEFAULT_COST * 3);
+  format %{ "SET64   $con,$dst KILL $tmp\t! cheap long" %}
+  ins_encode %{
+    __ set64($con$$constant, $dst$$Register, $tmp$$Register);
+  %}
+  ins_pipe(loadConL);
+%}
+// Load long value from constant table (predicated by immL_expensive).
+instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
+  match(Set dst con);
+  ins_cost(MEMORY_REF_COST);
+  format %{ "LDX     [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
+  ins_encode %{
+      RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
+    __ ldx($constanttablebase, con_offset, $dst$$Register);
+  %}
   ins_pipe(loadConL);
 %}
 …
 %}
 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
   match(Set dst src);
+instruct loadConF(regF dst, immF con, o7RegI tmp) %{
+  match(Set dst con);
   effect(KILL tmp);
+#ifdef _LP64
+  size(8*4);
+#else
+  size(2*4);
+#endif
+  format %{ "SETHI  hi(&$src),$tmp\t!get float $src from table\n\t"
+            "LDF    [$tmp+lo(&$src)],$dst" %}
+  format %{ "LDF    [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
   ins_encode %{
+    address float_address = __ float_constant($src$$constant);
+    RelocationHolder rspec = internal_word_Relocation::spec(float_address);
+    AddressLiteral addrlit(float_address, rspec);
+    __ sethi(addrlit, $tmp$$Register);
+    __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
+      RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
+    __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
   %}
   ins_pipe(loadConFD);
 %}
 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
   match(Set dst src);
+instruct loadConD(regD dst, immD con, o7RegI tmp) %{
+  match(Set dst con);
   effect(KILL tmp);
+#ifdef _LP64
+  size(8*4);
+#else
+  size(2*4);
+#endif
+  format %{ "SETHI  hi(&$src),$tmp\t!get double $src from table\n\t"
+            "LDDF   [$tmp+lo(&$src)],$dst" %}
+  format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
   ins_encode %{
-    address double_address = __ double_constant($src$$constant);
-    RelocationHolder rspec = internal_word_Relocation::spec(double_address);
-    AddressLiteral addrlit(double_address, rspec);
-    __ sethi(addrlit, $tmp$$Register);
     // XXX This is a quick fix for 6833573.
+    //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
+    __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
+    //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
+    RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
+    __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
   %}
   ins_pipe(loadConFD);
 …
 #endif
+instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
+  match(Set dst (CmpLTMask src zero));
+  effect(KILL ccr);
+  size(4);
+  format %{ "SRA    $src,#31,$dst\t# cmpLTMask0" %}
+  ins_encode %{
+    __ sra($src$$Register, 31, $dst$$Register);
+  %}
+  ins_pipe(ialu_reg_imm);
+%}
 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
   match(Set dst (CmpLTMask p q));
 …
   format %{ "SUBcc  $p,$q,$p\t! p' = p-q\n\t"
             "ADD    $p,$y,$tmp\t! g3=p-q+y\n\t"
+            "MOVl   $tmp,$p\t! p' < 0 ? p'+y : p'" %}
+  ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
+  ins_pipe( cadd_cmpltmask );
+%}
+instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
+  match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y)));
+  effect( KILL ccr, TEMP tmp);
+  ins_cost(DEFAULT_COST*3);
+  format %{ "SUBcc  $p,$q,$p\t! p' = p-q\n\t"
+            "ADD    $p,$y,$tmp\t! g3=p-q+y\n\t"
+            "MOVl   $tmp,$p\t! p' < 0 ? p'+y : p'" %}
+            "MOVlt  $tmp,$p\t! p' < 0 ? p'+y : p'" %}
   ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
   ins_pipe( cadd_cmpltmask );
 …
 // Replicate scalar constant to packed byte values in Double register
 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
   match(Set dst (Replicate8B src));
+#ifdef _LP64
   size(36);
+#else
   size(8);
+#endif
   format %{ "SETHI  hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
             "LDDF   [$tmp+lo(&Repl8($src))],$dst" %}
   ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
+instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
+  match(Set dst (Replicate8B con));
+  effect(KILL tmp);
+  format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
+  ins_encode %{
+    // XXX This is a quick fix for 6833573.
+    //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
+    RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
+    __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
+  %}
   ins_pipe(loadConFD);
 %}
 …
 // Replicate scalar constant to packed char values in Double register
 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
   match(Set dst (Replicate4C src));
+#ifdef _LP64
   size(36);
+#else
   size(8);
+#endif
   format %{ "SETHI  hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
             "LDDF   [$tmp+lo(&Repl4($src))],$dst" %}
   ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
+instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{
+  match(Set dst (Replicate4C con));
+  effect(KILL tmp);
+  format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %}
+  ins_encode %{
+    // XXX This is a quick fix for 6833573.
+    //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
+    RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
+    __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
+  %}
   ins_pipe(loadConFD);
 %}
 …
 // Replicate scalar constant to packed short values in Double register
 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
   match(Set dst (Replicate4S src));
+#ifdef _LP64
   size(36);
+#else
   size(8);
+#endif
   format %{ "SETHI  hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
             "LDDF   [$tmp+lo(&Repl4($src))],$dst" %}
   ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
+instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
+  match(Set dst (Replicate4S con));
+  effect(KILL tmp);
+  format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
+  ins_encode %{
+    // XXX This is a quick fix for 6833573.
+    //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
+    RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
+    __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
+  %}
   ins_pipe(loadConFD);
 %}
 …
 // Replicate scalar zero constant to packed int values in Double register
 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
   match(Set dst (Replicate2I src));
+#ifdef _LP64
   size(36);
+#else
   size(8);
+#endif
   format %{ "SETHI  hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
             "LDDF   [$tmp+lo(&Repl2($src))],$dst" %}
   ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
+instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
+  match(Set dst (Replicate2I con));
+  effect(KILL tmp);
+  format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
+  ins_encode %{
+    // XXX This is a quick fix for 6833573.
+    //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
+    RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
+    __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
+  %}
   ins_pipe(loadConFD);
 %}
 …
   ins_cost(350);
+  format %{  "SETHI  [hi(table_base)],O7\n\t"
+             "ADD    O7, lo(table_base), O7\n\t"
+             "LD     [O7+$switch_val], O7\n\t"
+  format %{  "ADD    $constanttablebase, $constantoffset, O7\n\t"
+             "LD     [O7 + $switch_val], O7\n\t"
              "JUMP   O7"
          %}
+  ins_encode( jump_enc( switch_val, table) );
+  ins_encode %{
+    // Calculate table address into a register.
+    Register table_reg;
+    Register label_reg = O7;
+    if (constant_offset() == 0) {
+      table_reg = $constanttablebase;
+    } else {
+      table_reg = O7;
+      RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
+      __ add($constanttablebase, con_offset, table_reg);
+    }
+    // Jump to base address + switch value
+    __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
+    __ jmp(label_reg, G0);
+    __ delayed()->nop();
+  %}
   ins_pc_relative(1);
   ins_pipe(ialu_reg_reg);
 …
     Register Rsrc = $src$$Register;
     Register Rtmp = $tmp$$Register;
     __ srl(Rsrc, 1, Rtmp);
     __ srl(Rsrc, 0, Rdst);
+    __ srl(Rsrc, 1,    Rtmp);
+    __ srl(Rsrc, 0,    Rdst);
     __ or3(Rdst, Rtmp, Rdst);
     __ srl(Rdst, 2, Rtmp);
+    __ srl(Rdst, 2,    Rtmp);
     __ or3(Rdst, Rtmp, Rdst);
     __ srl(Rdst, 4, Rtmp);
+    __ srl(Rdst, 4,    Rtmp);
     __ or3(Rdst, Rtmp, Rdst);
     __ srl(Rdst, 8, Rtmp);
+    __ srl(Rdst, 8,    Rtmp);
     __ or3(Rdst, Rtmp, Rdst);
     __ srl(Rdst, 16, Rtmp);
+    __ srl(Rdst, 16,   Rtmp);
     __ or3(Rdst, Rtmp, Rdst);
     __ popc(Rdst, Rdst);
 …
 %}
 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
+instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
   match(Set dst (CountLeadingZerosL src));
 …
     Register Rsrc = $src$$Register;
     Register Rtmp = $tmp$$Register;
     __ srlx(Rsrc, 1, Rtmp);
     __ or3(Rsrc, Rtmp, Rdst);
     __ srlx(Rdst, 2, Rtmp);
     __ or3(Rdst, Rtmp, Rdst);
     __ srlx(Rdst, 4, Rtmp);
     __ or3(Rdst, Rtmp, Rdst);
     __ srlx(Rdst, 8, Rtmp);
     __ or3(Rdst, Rtmp, Rdst);
     __ srlx(Rdst, 16, Rtmp);
     __ or3(Rdst, Rtmp, Rdst);
     __ srlx(Rdst, 32, Rtmp);
     __ or3(Rdst, Rtmp, Rdst);
+    __ srlx(Rsrc, 1,    Rtmp);
+    __ or3( Rsrc, Rtmp, Rdst);
+    __ srlx(Rdst, 2,    Rtmp);
+    __ or3( Rdst, Rtmp, Rdst);
+    __ srlx(Rdst, 4,    Rtmp);
+    __ or3( Rdst, Rtmp, Rdst);
+    __ srlx(Rdst, 8,    Rtmp);
+    __ or3( Rdst, Rtmp, Rdst);
+    __ srlx(Rdst, 16,   Rtmp);
+    __ or3( Rdst, Rtmp, Rdst);
+    __ srlx(Rdst, 32,   Rtmp);
+    __ or3( Rdst, Rtmp, Rdst);
     __ popc(Rdst, Rdst);
     __ mov(BitsPerLong, Rtmp);

trunk/openjdk/hotspot/src/cpu/sparc/vm/stubGenerator_sparc.cpp

-              r278
+              r309
  */
+#include "incls/_precompiled.incl"
+#include "incls/_stubGenerator_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "asm/assembler.hpp"
+#include "assembler_sparc.inline.hpp"
+#include "interpreter/interpreter.hpp"
+#include "nativeInst_sparc.hpp"
+#include "oops/instanceOop.hpp"
+#include "oops/methodOop.hpp"
+#include "oops/objArrayKlass.hpp"
+#include "oops/oop.inline.hpp"
+#include "prims/methodHandles.hpp"
+#include "runtime/frame.inline.hpp"
+#include "runtime/handles.inline.hpp"
+#include "runtime/sharedRuntime.hpp"
+#include "runtime/stubCodeGenerator.hpp"
+#include "runtime/stubRoutines.hpp"
+#include "utilities/top.hpp"
+#ifdef TARGET_OS_FAMILY_linux
+# include "thread_linux.inline.hpp"
+#endif
+#ifdef TARGET_OS_FAMILY_solaris
+# include "thread_solaris.inline.hpp"
+#endif
+#ifdef COMPILER2
+#include "opto/runtime.hpp"
+#endif
 // Declaration and definition of StubGenerator (no .hpp file).

trunk/openjdk/hotspot/src/cpu/sparc/vm/stubRoutines_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2007, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "incls/_precompiled.incl"
+#include "incls/_stubRoutines_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "runtime/deoptimization.hpp"
+#include "runtime/frame.inline.hpp"
+#include "runtime/stubRoutines.hpp"
+#ifdef TARGET_OS_FAMILY_linux
+# include "thread_linux.inline.hpp"
+#endif
+#ifdef TARGET_OS_FAMILY_solaris
+# include "thread_solaris.inline.hpp"
+#endif
 // Implementation of the platform-specific part of StubRoutines - for

trunk/openjdk/hotspot/src/cpu/sparc/vm/stubRoutines_sparc.hpp

-              r278
+              r309
  */
+#ifndef CPU_SPARC_VM_STUBROUTINES_SPARC_HPP
+#define CPU_SPARC_VM_STUBROUTINES_SPARC_HPP
 // This file holds the platform specific parts of the StubRoutines
 // definition. See stubRoutines.hpp for a description on how to
 …
 // MethodHandles adapters
 enum method_handles_platform_dependent_constants {
   method_handles_adapters_code_size = 6000
+  method_handles_adapters_code_size = 15000
 };
 …
   static address partial_subtype_check()                  { return _partial_subtype_check; }
 };
+#endif // CPU_SPARC_VM_STUBROUTINES_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/templateInterpreterGenerator_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2007, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_TEMPLATEINTERPRETERGENERATOR_SPARC_HPP
+#define CPU_SPARC_VM_TEMPLATEINTERPRETERGENERATOR_SPARC_HPP
   protected:
 …
   void generate_stack_overflow_check(Register Rframe_size, Register Rscratch,
                                      Register Rscratch2);
+#endif // CPU_SPARC_VM_TEMPLATEINTERPRETERGENERATOR_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/templateInterpreter_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "incls/_precompiled.incl"
+#include "incls/_templateInterpreter_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "asm/assembler.hpp"
+#include "interpreter/bytecodeHistogram.hpp"
+#include "interpreter/interpreter.hpp"
+#include "interpreter/interpreterGenerator.hpp"
+#include "interpreter/interpreterRuntime.hpp"
+#include "interpreter/templateTable.hpp"
+#include "oops/arrayOop.hpp"
+#include "oops/methodDataOop.hpp"
+#include "oops/methodOop.hpp"
+#include "oops/oop.inline.hpp"
+#include "prims/jvmtiExport.hpp"
+#include "prims/jvmtiThreadState.hpp"
+#include "runtime/arguments.hpp"
+#include "runtime/deoptimization.hpp"
+#include "runtime/frame.inline.hpp"
+#include "runtime/sharedRuntime.hpp"
+#include "runtime/stubRoutines.hpp"
+#include "runtime/synchronizer.hpp"
+#include "runtime/timer.hpp"
+#include "runtime/vframeArray.hpp"
+#include "utilities/debug.hpp"
 #ifndef CC_INTERP
 …
 //
 void InterpreterGenerator::generate_counter_incr(Label* overflow, Label* profile_method, Label* profile_method_continue) {
+  // Update standard invocation counters
+  __ increment_invocation_counter(O0, G3_scratch);
+  if (ProfileInterpreter) {  // %%% Merge this into methodDataOop
+    Address interpreter_invocation_counter(Lmethod, methodOopDesc::interpreter_invocation_counter_offset());
+    __ ld(interpreter_invocation_counter, G3_scratch);
+    __ inc(G3_scratch);
+    __ st(G3_scratch, interpreter_invocation_counter);
+  }
+  if (ProfileInterpreter && profile_method != NULL) {
+    // Test to see if we should create a method data oop
+    AddressLiteral profile_limit(&InvocationCounter::InterpreterProfileLimit);
+    __ sethi(profile_limit, G3_scratch);
+    __ ld(G3_scratch, profile_limit.low10(), G3_scratch);
+  // Note: In tiered we increment either counters in methodOop or in MDO depending if we're profiling or not.
+  if (TieredCompilation) {
+    const int increment = InvocationCounter::count_increment;
+    const int mask = ((1 << Tier0InvokeNotifyFreqLog) - 1) << InvocationCounter::count_shift;
+    Label no_mdo, done;
+    if (ProfileInterpreter) {
+      // If no method data exists, go to profile_continue.
+      __ ld_ptr(Lmethod, methodOopDesc::method_data_offset(), G4_scratch);
+      __ br_null(G4_scratch, false, Assembler::pn, no_mdo);
+      __ delayed()->nop();
+      // Increment counter
+      Address mdo_invocation_counter(G4_scratch,
+                                     in_bytes(methodDataOopDesc::invocation_counter_offset()) +
+                                     in_bytes(InvocationCounter::counter_offset()));
+      __ increment_mask_and_jump(mdo_invocation_counter, increment, mask,
+                                 G3_scratch, Lscratch,
+                                 Assembler::zero, overflow);
+      __ ba(false, done);
+      __ delayed()->nop();
+    }
+    // Increment counter in methodOop
+    __ bind(no_mdo);
+    Address invocation_counter(Lmethod,
+                               in_bytes(methodOopDesc::invocation_counter_offset()) +
+                               in_bytes(InvocationCounter::counter_offset()));
+    __ increment_mask_and_jump(invocation_counter, increment, mask,
+                               G3_scratch, Lscratch,
+                               Assembler::zero, overflow);
+    __ bind(done);
+  } else {
+    // Update standard invocation counters
+    __ increment_invocation_counter(O0, G3_scratch);
+    if (ProfileInterpreter) {  // %%% Merge this into methodDataOop
+      Address interpreter_invocation_counter(Lmethod,in_bytes(methodOopDesc::interpreter_invocation_counter_offset()));
+      __ ld(interpreter_invocation_counter, G3_scratch);
+      __ inc(G3_scratch);
+      __ st(G3_scratch, interpreter_invocation_counter);
+    }
+    if (ProfileInterpreter && profile_method != NULL) {
+      // Test to see if we should create a method data oop
+      AddressLiteral profile_limit((address)&InvocationCounter::InterpreterProfileLimit);
+      __ load_contents(profile_limit, G3_scratch);
+      __ cmp(O0, G3_scratch);
+      __ br(Assembler::lessUnsigned, false, Assembler::pn, *profile_method_continue);
+      __ delayed()->nop();
+      // if no method data exists, go to profile_method
+      __ test_method_data_pointer(*profile_method);
+    }
+    AddressLiteral invocation_limit((address)&InvocationCounter::InterpreterInvocationLimit);
+    __ load_contents(invocation_limit, G3_scratch);
     __ cmp(O0, G3_scratch);
     __ br(Assembler::lessUnsigned, false, Assembler::pn, *profile_method_continue);
+    __ br(Assembler::greaterEqualUnsigned, false, Assembler::pn, *overflow);
     __ delayed()->nop();
+    // if no method data exists, go to profile_method
+    __ test_method_data_pointer(*profile_method);
+  }
+  AddressLiteral invocation_limit(&InvocationCounter::InterpreterInvocationLimit);
+  __ sethi(invocation_limit, G3_scratch);
+  __ ld(G3_scratch, invocation_limit.low10(), G3_scratch);
+  __ cmp(O0, G3_scratch);
+  __ br(Assembler::greaterEqualUnsigned, false, Assembler::pn, *overflow);
+  __ delayed()->nop();
+  }
+}
 …
       __ bind(profile_method);
+      __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::profile_method), Lbcp, true);
+#ifdef ASSERT
+      __ tst(O0);
+      __ breakpoint_trap(Assembler::notEqual);
+#endif
+      __ set_method_data_pointer();
+      __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::profile_method));
+      __ set_method_data_pointer_for_bcp();
       __ ba(false, profile_method_continue);
       __ delayed()->nop();

trunk/openjdk/hotspot/src/cpu/sparc/vm/templateInterpreter_sparc.hpp

-              r278
+              r309
  */
+#ifndef CPU_SPARC_VM_TEMPLATEINTERPRETER_SPARC_HPP
+#define CPU_SPARC_VM_TEMPLATEINTERPRETER_SPARC_HPP
   protected:
 …
   const static int InterpreterCodeSize = 180 * K;
 #endif
+#endif // CPU_SPARC_VM_TEMPLATEINTERPRETER_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/templateTable_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "incls/_precompiled.incl"
+#include "incls/_templateTable_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "interpreter/interpreter.hpp"
+#include "interpreter/interpreterRuntime.hpp"
+#include "interpreter/templateTable.hpp"
+#include "memory/universe.inline.hpp"
+#include "oops/methodDataOop.hpp"
+#include "oops/objArrayKlass.hpp"
+#include "oops/oop.inline.hpp"
+#include "prims/methodHandles.hpp"
+#include "runtime/sharedRuntime.hpp"
+#include "runtime/stubRoutines.hpp"
+#include "runtime/synchronizer.hpp"
 #ifndef CC_INTERP
 …
   __ verify_oop(Otos_i);
+  Label L_done;
+  const Register Rcon_klass = G3_scratch;  // same as Rcache
+  const Register Rarray_klass = G4_scratch;  // same as Rscratch
+  __ load_klass(Otos_i, Rcon_klass);
+  AddressLiteral array_klass_addr((address)Universe::systemObjArrayKlassObj_addr());
+  __ load_contents(array_klass_addr, Rarray_klass);
+  __ cmp(Rarray_klass, Rcon_klass);
+  __ brx(Assembler::notEqual, false, Assembler::pt, L_done);
+  __ delayed()->nop();
+  __ ld(Address(Otos_i, arrayOopDesc::length_offset_in_bytes()), Rcon_klass);
+  __ tst(Rcon_klass);
+  __ brx(Assembler::zero, true, Assembler::pt, L_done);
+  __ delayed()->clr(Otos_i);    // executed only if branch is taken
+  // Load the exception from the system-array which wraps it:
+  __ load_heap_oop(Otos_i, arrayOopDesc::base_offset_in_bytes(T_OBJECT), Otos_i);
+  __ throw_if_not_x(Assembler::never, Interpreter::throw_exception_entry(), G3_scratch);
+  __ bind(L_done);
+}
 …
   __ mov( Lbcp, O0_cur_bcp );
   bool increment_invocation_counter_for_backward_branches = UseCompiler && UseLoopCounter;
   if ( increment_invocation_counter_for_backward_branches ) {
 …
     __ delayed()->add( O1_disp, Lbcp, Lbcp );     // add to bc addr
+    // Update Backedge branch separately from invocations
+    const Register G4_invoke_ctr = G4;
+    __ increment_backedge_counter(G4_invoke_ctr, G1_scratch);
+    if (ProfileInterpreter) {
+      __ test_invocation_counter_for_mdp(G4_invoke_ctr, Lbcp, G3_scratch, Lforward);
+      if (UseOnStackReplacement) {
+        __ test_backedge_count_for_osr(O2_bumped_count, O0_cur_bcp, G3_scratch);
+    if (TieredCompilation) {
+      Label Lno_mdo, Loverflow;
+      int increment = InvocationCounter::count_increment;
+      int mask = ((1 << Tier0BackedgeNotifyFreqLog) - 1) << InvocationCounter::count_shift;
+      if (ProfileInterpreter) {
+        // If no method data exists, go to profile_continue.
+        __ ld_ptr(Lmethod, methodOopDesc::method_data_offset(), G4_scratch);
+        __ br_null(G4_scratch, false, Assembler::pn, Lno_mdo);
+        __ delayed()->nop();
+        // Increment backedge counter in the MDO
+        Address mdo_backedge_counter(G4_scratch, in_bytes(methodDataOopDesc::backedge_counter_offset()) +
+                                                 in_bytes(InvocationCounter::counter_offset()));
+        __ increment_mask_and_jump(mdo_backedge_counter, increment, mask, G3_scratch, Lscratch,
+                                   Assembler::notZero, &Lforward);
+        __ ba(false, Loverflow);
+        __ delayed()->nop();
+      }
+      // If there's no MDO, increment counter in methodOop
+      __ bind(Lno_mdo);
+      Address backedge_counter(Lmethod, in_bytes(methodOopDesc::backedge_counter_offset()) +
+                                        in_bytes(InvocationCounter::counter_offset()));
+      __ increment_mask_and_jump(backedge_counter, increment, mask, G3_scratch, Lscratch,
+                                 Assembler::notZero, &Lforward);
+      __ bind(Loverflow);
+      // notify point for loop, pass branch bytecode
+      __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::frequency_counter_overflow), O0_cur_bcp);
+      // Was an OSR adapter generated?
+      // O0 = osr nmethod
+      __ br_null(O0, false, Assembler::pn, Lforward);
+      __ delayed()->nop();
+      // Has the nmethod been invalidated already?
+      __ ld(O0, nmethod::entry_bci_offset(), O2);
+      __ cmp(O2, InvalidOSREntryBci);
+      __ br(Assembler::equal, false, Assembler::pn, Lforward);
+      __ delayed()->nop();
+      // migrate the interpreter frame off of the stack
+      __ mov(G2_thread, L7);
+      // save nmethod
+      __ mov(O0, L6);
+      __ set_last_Java_frame(SP, noreg);
+      __ call_VM_leaf(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::OSR_migration_begin), L7);
+      __ reset_last_Java_frame();
+      __ mov(L7, G2_thread);
+      // move OSR nmethod to I1
+      __ mov(L6, I1);
+      // OSR buffer to I0
+      __ mov(O0, I0);
+      // remove the interpreter frame
+      __ restore(I5_savedSP, 0, SP);
+      // Jump to the osr code.
+      __ ld_ptr(O1, nmethod::osr_entry_point_offset(), O2);
+      __ jmp(O2, G0);
+      __ delayed()->nop();
     } else {
+      if (UseOnStackReplacement) {
+        __ test_backedge_count_for_osr(G4_invoke_ctr, O0_cur_bcp, G3_scratch);
+      // Update Backedge branch separately from invocations
+      const Register G4_invoke_ctr = G4;
+      __ increment_backedge_counter(G4_invoke_ctr, G1_scratch);
+      if (ProfileInterpreter) {
+        __ test_invocation_counter_for_mdp(G4_invoke_ctr, G3_scratch, Lforward);
+        if (UseOnStackReplacement) {
+          __ test_backedge_count_for_osr(O2_bumped_count, O0_cur_bcp, G3_scratch);
+        }
+      } else {
+        if (UseOnStackReplacement) {
+          __ test_backedge_count_for_osr(G4_invoke_ctr, O0_cur_bcp, G3_scratch);
+        }
+      }
+    }
 …
   __ ld_ptr(Rtemp, Rret, Rret);  // get return address
   __ ld_ptr(G5_callsite, __ delayed_value(java_dyn_CallSite::target_offset_in_bytes, Rscratch), G3_method_handle);
+  __ load_heap_oop(G5_callsite, __ delayed_value(java_dyn_CallSite::target_offset_in_bytes, Rscratch), G3_method_handle);
   __ null_check(G3_method_handle);
 …
     if (allow_shared_alloc) {
     // Check if tlab should be discarded (refill_waste_limit >= free)
     __ ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), RtlabWasteLimitValue);
     __ sub(RendValue, RoldTopValue, RfreeValue);
+      // Check if tlab should be discarded (refill_waste_limit >= free)
+      __ ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), RtlabWasteLimitValue);
+      __ sub(RendValue, RoldTopValue, RfreeValue);
 #ifdef _LP64
     __ srlx(RfreeValue, LogHeapWordSize, RfreeValue);
+      __ srlx(RfreeValue, LogHeapWordSize, RfreeValue);
 #else
     __ srl(RfreeValue, LogHeapWordSize, RfreeValue);
+      __ srl(RfreeValue, LogHeapWordSize, RfreeValue);
 #endif
     __ cmp(RtlabWasteLimitValue, RfreeValue);
     __ brx(Assembler::greaterEqualUnsigned, false, Assembler::pt, slow_case); // tlab waste is small
     __ delayed()->nop();
     // increment waste limit to prevent getting stuck on this slow path
     __ add(RtlabWasteLimitValue, ThreadLocalAllocBuffer::refill_waste_limit_increment(), RtlabWasteLimitValue);
     __ st_ptr(RtlabWasteLimitValue, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
+      __ cmp(RtlabWasteLimitValue, RfreeValue);
+      __ brx(Assembler::greaterEqualUnsigned, false, Assembler::pt, slow_case); // tlab waste is small
+      __ delayed()->nop();
+      // increment waste limit to prevent getting stuck on this slow path
+      __ add(RtlabWasteLimitValue, ThreadLocalAllocBuffer::refill_waste_limit_increment(), RtlabWasteLimitValue);
+      __ st_ptr(RtlabWasteLimitValue, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
     } else {
       // No allocation in the shared eden.
 …
     __ brx(Assembler::notEqual, false, Assembler::pn, retry);
     __ delayed()->nop();
+    // bump total bytes allocated by this thread
+    // RoldTopValue and RtopAddr are dead, so can use G1 and G3
+    __ incr_allocated_bytes(Roffset, G1_scratch, G3_scratch);
+  }

trunk/openjdk/hotspot/src/cpu/sparc/vm/templateTable_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1998, 2002, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_TEMPLATETABLE_SPARC_HPP
+#define CPU_SPARC_VM_TEMPLATETABLE_SPARC_HPP
   // helper function
   static void invokevfinal_helper(Register Rcache, Register Rret);
 …
   static void generate_vtable_call(Register Rrecv, Register Rindex, Register Rret);
   static void volatile_barrier(Assembler::Membar_mask_bits order_constraint);
+#endif // CPU_SPARC_VM_TEMPLATETABLE_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/vmStructs_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2001, 2007, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2001, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_VMSTRUCTS_SPARC_HPP
+#define CPU_SPARC_VM_VMSTRUCTS_SPARC_HPP
 // These are the CPU-specific fields, types and integer
 …
   /* in vmStructs_<os>_<cpu>.hpp's VM_LONG_CONSTANTS_OS_CPU macro (and must */
   /* be present there)                                                      */
+#endif // CPU_SPARC_VM_VMSTRUCTS_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/vm_version_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2009, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+# include "incls/_precompiled.incl"
+# include "incls/_vm_version_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "assembler_sparc.inline.hpp"
+#include "memory/resourceArea.hpp"
+#include "runtime/java.hpp"
+#include "runtime/stubCodeGenerator.hpp"
+#include "vm_version_sparc.hpp"
+#ifdef TARGET_OS_FAMILY_linux
+# include "os_linux.inline.hpp"
+#endif
+#ifdef TARGET_OS_FAMILY_solaris
+# include "os_solaris.inline.hpp"
+#endif
 int VM_Version::_features = VM_Version::unknown_m;
 const char* VM_Version::_features_str = "";
-bool VM_Version::is_niagara1_plus() {
-  // This is a placeholder until the real test is determined.
-  return is_niagara1() &&
-    (os::processor_count() > maximum_niagara1_processor_count());
+}
 void VM_Version::initialize() {
 …
   _supports_cx8               = has_v9();
   if (is_niagara1()) {
+  if (is_niagara()) {
     // Indirect branch is the same cost as direct
     if (FLAG_IS_DEFAULT(UseInlineCaches)) {
       FLAG_SET_DEFAULT(UseInlineCaches, false);
+    }
+    // Align loops on a single instruction boundary.
+    if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
+      FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
+    }
+    // When using CMS, we cannot use memset() in BOT updates because
+    // the sun4v/CMT version in libc_psr uses BIS which exposes
+    // "phantom zeros" to concurrent readers. See 6948537.
+    if (FLAG_IS_DEFAULT(UseMemSetInBOT) && UseConcMarkSweepGC) {
+      FLAG_SET_DEFAULT(UseMemSetInBOT, false);
+    }
 #ifdef _LP64
 …
       FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
+    }
+    if (is_niagara1_plus()) {
+      if (AllocatePrefetchStyle > 0 && FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
+    if (is_niagara_plus()) {
+      if (has_blk_init() && AllocatePrefetchStyle > 0 &&
+          FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
         // Use BIS instruction for allocation prefetch.
         FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
 …
+    }
 #endif
-    if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
-      FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
+    }
-    // When using CMS, we cannot use memset() in BOT updates because
-    // the sun4v/CMT version in libc_psr uses BIS which exposes
-    // "phantom zeros" to concurrent readers. See 6948537.
-    if (FLAG_IS_DEFAULT(UseMemSetInBOT) && UseConcMarkSweepGC) {
-      FLAG_SET_DEFAULT(UseMemSetInBOT, false);
+    }
+  }
 …
   char buf[512];
   jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s",
+  jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
                (has_v8() ? ", has_v8" : ""),
                (has_v9() ? ", has_v9" : ""),
 …
                (has_vis1() ? ", has_vis1" : ""),
                (has_vis2() ? ", has_vis2" : ""),
+               (has_vis3() ? ", has_vis3" : ""),
+               (has_blk_init() ? ", has_blk_init" : ""),
                (is_ultra3() ? ", is_ultra3" : ""),
                (is_sun4v() ? ", is_sun4v" : ""),
+               (is_niagara1() ? ", is_niagara1" : ""),
+               (is_niagara1_plus() ? ", is_niagara1_plus" : ""),
+               (is_niagara() ? ", is_niagara" : ""),
+               (is_niagara_plus() ? ", is_niagara_plus" : ""),
+               (is_sparc64() ? ", is_sparc64" : ""),
                (!has_hardware_mul32() ? ", no-mul32" : ""),
                (!has_hardware_div32() ? ", no-div32" : ""),
 …
+  }
+  if (UseNiagaraInstrs) {
+    if (is_niagara1(features)) {
+  assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
+  if (UseNiagaraInstrs) { // Force code generation for Niagara
+    if (is_T_family(features)) {
       // Happy to accomodate...
     } else {
       NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
       features = niagara1_m;
+      features |= T_family_m;
+    }
   } else {
     if (is_niagara1(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
+    if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
       NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
       features &= ~niagara1_unique_m;
+      features &= ~(T_family_m | T1_model_m);
     } else {
       // Happy to accomodate...
 …
 unsigned int VM_Version::calc_parallel_worker_threads() {
   unsigned int result;
   if (is_niagara1_plus()) {
+  if (is_niagara_plus()) {
     result = nof_parallel_worker_threads(5, 16, 8);
   } else {

trunk/openjdk/hotspot/src/cpu/sparc/vm/vm_version_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2009, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP
+#define CPU_SPARC_VM_VM_VERSION_SPARC_HPP
+#include "runtime/globals_extension.hpp"
+#include "runtime/vm_version.hpp"
 class VM_Version: public Abstract_VM_Version {
 protected:
 …
     vis1_instructions  = 6,
     vis2_instructions  = 7,
+    sun4v_instructions = 8
+    sun4v_instructions = 8,
+    blk_init_instructions = 9,
+    fmaf_instructions  = 10,
+    fmau_instructions  = 11,
+    vis3_instructions  = 12,
+    sparc64_family     = 13,
+    T_family           = 14,
+    T1_model           = 15
   };
 …
     vis2_instructions_m = 1 << vis2_instructions,
     sun4v_m             = 1 << sun4v_instructions,
+    blk_init_instructions_m = 1 << blk_init_instructions,
+    fmaf_instructions_m = 1 << fmaf_instructions,
+    fmau_instructions_m = 1 << fmau_instructions,
+    vis3_instructions_m = 1 << vis3_instructions,
+    sparc64_family_m    = 1 << sparc64_family,
+    T_family_m          = 1 << T_family,
+    T1_model_m          = 1 << T1_model,
     generic_v8_m        = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
 …
   static int  platform_features(int features);
+  static bool is_niagara1(int features) { return (features & sun4v_m) != 0; }
+  // Returns true if the platform is in the niagara line (T series)
+  static bool is_T_family(int features) { return (features & T_family_m) != 0; }
+  static bool is_niagara() { return is_T_family(_features); }
+  DEBUG_ONLY( static bool is_niagara(int features)  { return (features & sun4v_m) != 0; } )
+  // Returns true if it is niagara1 (T1).
+  static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); }
   static int maximum_niagara1_processor_count() { return 32; }
-  // Returns true if the platform is in the niagara line and
-  // newer than the niagara1.
-  static bool is_niagara1_plus();
 public:
 …
   static bool has_vis1()                { return (_features & vis1_instructions_m) != 0; }
   static bool has_vis2()                { return (_features & vis2_instructions_m) != 0; }
+  static bool has_vis3()                { return (_features & vis3_instructions_m) != 0; }
+  static bool has_blk_init()            { return (_features & blk_init_instructions_m) != 0; }
   static bool supports_compare_and_exchange()
 …
   static bool is_ultra3()               { return (_features & ultra3_m) == ultra3_m; }
   static bool is_sun4v()                { return (_features & sun4v_m) != 0; }
+  static bool is_niagara1()             { return is_niagara1(_features); }
+  // Returns true if the platform is in the niagara line (T series)
+  // and newer than the niagara1.
+  static bool is_niagara_plus()         { return is_T_family(_features) && !is_T1_model(_features); }
+  // Fujitsu SPARC64
+  static bool is_sparc64()              { return (_features & sparc64_family_m) != 0; }
+  static bool has_fast_fxtof()          { return has_v9() && !is_ultra3(); }
+  static bool has_fast_fxtof()          { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
+  static bool has_fast_idiv()           { return is_niagara_plus() || is_sparc64(); }
   static const char* cpu_features()     { return _features_str; }
 …
   static unsigned int calc_parallel_worker_threads();
 };
+#endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/vmreg_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 2006, 2007, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "incls/_precompiled.incl"
+#include "incls/_vmreg_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "asm/assembler.hpp"
+#include "code/vmreg.hpp"

trunk/openjdk/hotspot/src/cpu/sparc/vm/vmreg_sparc.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2006, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#ifndef CPU_SPARC_VM_VMREG_SPARC_HPP
+#define CPU_SPARC_VM_VMREG_SPARC_HPP
   bool is_Register();
   Register as_Register();
 …
   bool is_FloatRegister();
   FloatRegister as_FloatRegister();
+#endif // CPU_SPARC_VM_VMREG_SPARC_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/vmreg_sparc.inline.hpp

-              r278
+              r309
 /*
  * Copyright (c) 2006, 2007, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
+ *
  */
+#ifndef CPU_SPARC_VM_VMREG_SPARC_INLINE_HPP
+#define CPU_SPARC_VM_VMREG_SPARC_INLINE_HPP
 inline VMReg RegisterImpl::as_VMReg() {
 …
   return false;
+}
+#endif // CPU_SPARC_VM_VMREG_SPARC_INLINE_HPP

trunk/openjdk/hotspot/src/cpu/sparc/vm/vtableStubs_sparc.cpp

-              r278
+              r309
 /*
  * Copyright (c) 1997, 2009, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
 …
  */
+#include "incls/_precompiled.incl"
+#include "incls/_vtableStubs_sparc.cpp.incl"
+#include "precompiled.hpp"
+#include "asm/assembler.hpp"
+#include "assembler_sparc.inline.hpp"
+#include "code/vtableStubs.hpp"
+#include "interp_masm_sparc.hpp"
+#include "memory/resourceArea.hpp"
+#include "oops/instanceKlass.hpp"
+#include "oops/klassVtable.hpp"
+#include "runtime/sharedRuntime.hpp"
+#include "vmreg_sparc.inline.hpp"
+#ifdef COMPILER2
+#include "opto/runtime.hpp"
+#endif
 // machine-dependent part of VtableStubs: create vtableStub of correct size and

/branches/vendor/oracle/openjdk6/b24 (added)	merged: 308
/branches/vendor/oracle/openjdk6/current	merged: 307

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