Index: /trunk/src/os2ahci/ahci.c
===================================================================
--- /trunk/src/os2ahci/ahci.c	(revision 79)
+++ /trunk/src/os2ahci/ahci.c	(revision 80)
@@ -135,4 +135,12 @@
   for (i = 0; i < HOST_CAP2; i += sizeof(u32)) {
     ai->bios_config[i / sizeof(u32)] = readl(ai->mmio + i);
+  }
+
+  if ((ai->bios_config[HOST_CTL / sizeof(u32)] & HOST_AHCI_EN) == 0 &&
+      ai->pci->vendor == PCI_VENDOR_ID_INTEL) {
+    /* Adapter is not in AHCI mode and the spec says a COMRESET is
+     * required when switching from SATA to AHCI mode and vice versa.
+     */
+    init_reset = 1;
   }
 
@@ -184,5 +192,4 @@
         if (val & HOST_CAP2_NVMHCI)    printf(" nvmhci");
         if (val & HOST_CAP2_APST)      printf(" apst");
-
       }
       printf("\n");
@@ -277,12 +284,54 @@
   ddprintf("restoring AHCI BIOS configuration\n");
 
-  /* restore saved BIOS configuration */
-  writel(ai->mmio + HOST_CTL,       ai->bios_config[HOST_CTL / sizeof(u32)]);
+  /* Restore saved BIOS configuration; please note that HOST_CTL is restored
+   * last because it may cause AHCI mode to be turned off again.
+   */
   writel(ai->mmio + HOST_CCC,       ai->bios_config[HOST_CCC / sizeof(u32)]);
   writel(ai->mmio + HOST_CCC_PORTS, ai->bios_config[HOST_CCC_PORTS / sizeof(u32)]);
   writel(ai->mmio + HOST_EM_CTL,    ai->bios_config[HOST_EM_CTL / sizeof(u32)]);
+  writel(ai->mmio + HOST_CTL,       ai->bios_config[HOST_CTL / sizeof(u32)]);
 
   /* flush PCI MMIO delayed write buffers */
-  readl(ai->mmio + HOST_EM_CTL);
+  readl(ai->mmio + HOST_CTL);
+
+  if ((ai->bios_config[HOST_CTL / sizeof(u32)] & HOST_AHCI_EN) == 0 &&
+      ai->pci->vendor == PCI_VENDOR_ID_INTEL) {
+
+    /* This BIOS apparently accesses this controller via SATA registers and
+     * the AHCI spec says that we should issue a COMRESET on each port after
+     * disabling AHCI mode to allow the SATA controller to re-recognize attached
+     * devices. How to do this depends on the controller, of course, but so
+     * far I've only seen Dell notebook BIOSs with Intel chipsets to behave
+     * like this; all other BIOS implementations I've seen so far seem to take
+     * AHCI mode literally and operate the controller in AHCI mode from the
+     * beginning.
+     *
+     * We'll use a feature on Intel ICH7/8 controllers which provides MMIO
+     * mappings for the AHCI SCR registers even when not in AHCI mode.
+     */
+    int p;
+
+    for (p = 0; p < AHCI_MAX_PORTS; p++) {
+      if (ai->port_map & (1UL << p)) {
+        u8 _far *port_mmio = port_base(ai, p);
+        u32 tmp;
+
+        tmp = readl(port_mmio + PORT_SCR_CTL) & ~0x0000000fUL;
+        writel(port_mmio + PORT_SCR_CTL, tmp | 1);
+        readl(port_mmio + PORT_SCR_CTL);  /* flush */
+
+        /* spec says "leave reset bit on for at least 1ms"; make it 2ms */
+        mdelay(2);
+
+        writel(port_mmio + PORT_SCR_CTL, tmp);
+        readl(port_mmio + PORT_SCR_CTL);  /* flush */
+      }
+    }
+
+    /* Wait some time to give the COMRESET a chance to complete (usually, at
+     * least hard disks complete the reset within a few milliseonds)
+     */
+    mdelay(20);
+  }
 
   return(0);
@@ -298,11 +347,11 @@
 
   /* restore saved BIOS configuration */
-  writel(ai->mmio + HOST_CTL,       ai->bios_config[HOST_CTL / sizeof(u32)]);
   writel(ai->mmio + HOST_CCC,       ai->bios_config[HOST_CCC / sizeof(u32)]);
   writel(ai->mmio + HOST_CCC_PORTS, ai->bios_config[HOST_CCC_PORTS / sizeof(u32)]);
   writel(ai->mmio + HOST_EM_CTL,    ai->bios_config[HOST_EM_CTL / sizeof(u32)]);
+  writel(ai->mmio + HOST_CTL,       ai->bios_config[HOST_CTL / sizeof(u32)]);
 
   /* flush PCI MMIO delayed write buffers */
-  readl(ai->mmio + HOST_EM_CTL);
+  readl(ai->mmio + HOST_CTL);
 
   /* (re-)enable AHCI mode */
@@ -333,4 +382,5 @@
   pc->fis_rx_h   = readl(port_mmio + PORT_FIS_ADDR_HI);
   pc->irq_mask   = readl(port_mmio + PORT_IRQ_MASK);
+  pc->port_cmd   = readl(port_mmio + PORT_CMD);
 
   return(pc);
@@ -341,5 +391,5 @@
  * configuration (command list and FIS buffers and the IRQ mask).
  *
- * The port configuration automatically freed.
+ * The port configuration is automatically freed.
  */
 void ahci_restore_port_config(AD_INFO *ai, int p, AHCI_PORT_CFG *pc)
@@ -347,11 +397,21 @@
   u8 _far *port_mmio = port_base(ai, p);
 
-  writel(port_mmio + PORT_LST_ADDR,    pc->cmd_list);
-  writel(port_mmio + PORT_LST_ADDR_HI, pc->cmd_list_h);
-  writel(port_mmio + PORT_FIS_ADDR,    pc->fis_rx);
-  writel(port_mmio + PORT_FIS_ADDR_HI, pc->fis_rx_h);
-  writel(port_mmio + PORT_IRQ_MASK,    pc->irq_mask);
-
-  readl(port_base(ai, p) + PORT_IRQ_MASK); /* flush */
+  /* stop the port, first */
+  ahci_stop_port(ai, p);
+
+  if (ai->bios_config[HOST_CTL / sizeof(u32)] & HOST_AHCI_EN) {
+    /* BIOS uses AHCI, too, so we need to restore the port settings;
+     * restoring PORT_CMD way well start the port again but that's what
+     * this function is all about.
+     */
+    writel(port_mmio + PORT_LST_ADDR,    pc->cmd_list);
+    writel(port_mmio + PORT_LST_ADDR_HI, pc->cmd_list_h);
+    writel(port_mmio + PORT_FIS_ADDR,    pc->fis_rx);
+    writel(port_mmio + PORT_FIS_ADDR_HI, pc->fis_rx_h);
+    writel(port_mmio + PORT_IRQ_MASK,    pc->irq_mask);
+    writel(port_mmio + PORT_CMD,         pc->port_cmd);
+
+    readl(port_base(ai, p) + PORT_IRQ_MASK); /* flush */
+  }
 
   free(pc);
@@ -439,5 +499,4 @@
       /* start/reset port; if no device is attached, this is expected to fail */
       if (init_reset) {
-        ddprintf("init-resetting port #%d\n", p);
         rc = ahci_reset_port(ai, p, 0);
       } else {
@@ -547,7 +606,11 @@
   for (p = 0; p < AHCI_MAX_PORTS; p++) {
     if (ai->port_map & (1UL << p)) {
-      dprintf("restarting port #%d\n", p);
-      ahci_stop_port(ai, p);
-      ahci_start_port(ai, p, 1);
+      if (init_reset) {
+        ahci_reset_port(ai, p, 1);
+      } else {
+        dprintf("restarting port #%d\n", p);
+        ahci_stop_port(ai, p);
+        ahci_start_port(ai, p, 1);
+      }
     }
   }
@@ -561,5 +624,5 @@
   readl(ai->mmio + HOST_CTL); /* flush */
 
-  /* enable interrupts on PCI-level (PCI 2.3 added a feature to disable ints) */
+  /* enable interrupts on PCI-level (PCI 2.3 added a feature to disable INTs) */
   /* pci_enable_int(ai->bus, ai->dev_func); */
 
@@ -586,11 +649,18 @@
 
   dprintf("resetting port %d.%d\n", ad_no(ai), p);
-  ddprintf(" PORT_CMD_ISSUE = 0x%lx\n", readl(port_mmio + PORT_CMD_ISSUE));
-  ddprintf(" PORT_SCR_ACT   = 0x%lx\n", readl(port_mmio + PORT_SCR_ACT));
-  ddprintf(" PORT_SCR_ERR   = 0x%lx\n", readl(port_mmio + PORT_SCR_ERR));
-  ddprintf(" PORT_TFDATA    = 0x%lx\n", readl(port_mmio + PORT_TFDATA));
-  ddprintf(" PORT_IRQ_STAT  = 0x%lx\n", readl(port_mmio + PORT_IRQ_STAT));
-  ddprintf(" PORT_IRQ_MASK  = 0x%lx\n", readl(port_mmio + PORT_IRQ_MASK));
-  ddprintf(" HOST_IRQ_STAT  = 0x%lx\n", readl(ai->mmio + HOST_IRQ_STAT));
+  if (debug > 1) {
+    printf("command engine status:\n");
+    printf(" PORT_SCR_ACT   = 0x%lx\n", readl(port_mmio + PORT_SCR_ACT));
+    printf(" PORT_CMD_ISSUE = 0x%lx\n", readl(port_mmio + PORT_CMD_ISSUE));
+    printf("link/device status:\n");
+    printf(" PORT_SCR_STAT  = 0x%lx\n", readl(port_mmio + PORT_SCR_STAT));
+    printf(" PORT_SCR_CTL   = 0x%lx\n", readl(port_mmio + PORT_SCR_CTL));
+    printf(" PORT_SCR_ERR   = 0x%lx\n", readl(port_mmio + PORT_SCR_ERR));
+    printf(" PORT_TFDATA    = 0x%lx\n", readl(port_mmio + PORT_TFDATA));
+    printf("interrupt status:\n");
+    printf(" PORT_IRQ_STAT  = 0x%lx\n", readl(port_mmio + PORT_IRQ_STAT));
+    printf(" PORT_IRQ_MASK  = 0x%lx\n", readl(port_mmio + PORT_IRQ_MASK));
+    printf(" HOST_IRQ_STAT  = 0x%lx\n", readl(ai->mmio + HOST_IRQ_STAT));
+  }
 
   /* stop port engines (we don't care whether there is an error doing so) */
@@ -600,11 +670,4 @@
   tmp = readl(port_mmio + PORT_SCR_ERR);
   writel(port_mmio + PORT_SCR_ERR, tmp);
-
-  /* clear pending port IRQs */
-  tmp = readl(port_mmio + PORT_IRQ_STAT);
-  if (tmp) {
-    writel(port_mmio + PORT_IRQ_STAT, tmp);
-  }
-  writel(ai->mmio + HOST_IRQ_STAT, 1UL << p);
 
   /* set link speed and power management options */
@@ -721,5 +784,5 @@
   u32 tmp;
 
-  /* set comand header and FIS address registers */
+  /* set command header and FIS address registers */
   writel(port_mmio + PORT_LST_ADDR, port_dma + offsetof(AHCI_PORT_DMA, cmd_hdr));
   writel(port_mmio + PORT_LST_ADDR_HI, 0);
@@ -757,4 +820,5 @@
 {
   u8 _far *port_mmio = port_base(ai, p);
+  u32 tmp;
   int rc;
 
@@ -773,4 +837,11 @@
     return(rc);
   }
+
+  /* clear any pending port IRQs */
+  tmp = readl(port_mmio + PORT_IRQ_STAT);
+  if (tmp) {
+    writel(port_mmio + PORT_IRQ_STAT, tmp);
+  }
+  writel(ai->mmio + HOST_IRQ_STAT, 1UL << p);
 
   /* reset PxSACT register (tagged command queues, not reset by COMRESET) */
@@ -1023,6 +1094,19 @@
   }
 
-  /* restart port (includes the necessary port configuration) */
-  if (ahci_stop_port(ai, p) || ahci_start_port(ai, p, 0)) {
+  /* restart/reset port (includes the necessary port configuration) */
+  if ((ai->bios_config[HOST_CTL / sizeof(u32)] & HOST_AHCI_EN) == 0 &&
+      ai->pci->vendor == PCI_VENDOR_ID_INTEL) {
+    /* As outlined in ahci_restore_bios_config(), switching back and
+     * forth between SATA and AHCI mode requires a COMRESET to force
+     * the corresponding controller subsystem to rediscover attached
+     * devices. Thus, we'll reset the port instead of stopping and
+     * starting it.
+     */
+    if (ahci_reset_port(ai, p, 0)) {
+      iorb_seterr(iorb, IOERR_ADAPTER_NONSPECIFIC);
+      goto restore_bios_config;
+    }
+
+  } else if (ahci_stop_port(ai, p) || ahci_start_port(ai, p, 0)) {
     iorb_seterr(iorb, IOERR_ADAPTER_NONSPECIFIC);
     goto restore_bios_config;
@@ -1500,14 +1584,11 @@
   } else {
     /* complete ATA-specific device information */
-    if (disable_ncq[ad_no(ai)][p]) {
-      /* MT: set ncq_max to 1 if NCQ is disabled for this port */
+    if (enable_ncq[ad_no(ai)][p]) {
+      ai->ports[p].devs[d].ncq_max = id_buf[ATA_ID_QUEUE_DEPTH] & 0x001fU;
+    }
+    if (ai->ports[p].devs[d].ncq_max < 1) {
+      /* NCQ not enabled for this device, or device doesn't support NCQ */
       ai->ports[p].devs[d].ncq_max = 1;
-      dprintf("NCQ off for a:%d p:%d\n", (int) ad_no(ai), p);
-    } else {
-      ai->ports[p].devs[d].ncq_max = max(id_buf[ATA_ID_QUEUE_DEPTH] & 0x001fU, 1);
-      dprintf("NCQ max=%d for a:%d p:%d\n", ai->ports[p].devs[d].ncq_max,
-                                            (int) ad_no(ai), p);
-    }
-
+    }
     if (id_buf[ATA_ID_CFS_ENABLE_2] & 0x0400U) {
       ai->ports[p].devs[d].lba48   = 1;
@@ -1515,9 +1596,10 @@
   }
 
-  dprintf("found device %d.%d.%d: removable = %d, dev_type = %d, atapi = %d\n",
-          ad_no(ai), p, d,
+  dprintf("found device %d.%d.%d: removable = %d, dev_type = %d, atapi = %d, "
+          "ncq_max = %d\n", ad_no(ai), p, d,
           ai->ports[p].devs[d].removable,
           ai->ports[p].devs[d].dev_type,
-          ai->ports[p].devs[d].atapi);
+          ai->ports[p].devs[d].atapi,
+          ai->ports[p].devs[d].ncq_max);
 
   /* add device to resource manager; we don't really care about errors here */
Index: /trunk/src/os2ahci/ahci.h
===================================================================
--- /trunk/src/os2ahci/ahci.h	(revision 79)
+++ /trunk/src/os2ahci/ahci.h	(revision 80)
@@ -276,4 +276,5 @@
   u32   fis_rx_h;                          /* FIS receive bufffer high */
   u32   irq_mask;                          /* IRQ mask */
+  u32   port_cmd;                          /* port engine status */
 } AHCI_PORT_CFG;
 
Index: /trunk/src/os2ahci/ata.c
===================================================================
--- /trunk/src/os2ahci/ata.c	(revision 79)
+++ /trunk/src/os2ahci/ata.c	(revision 80)
@@ -501,12 +501,6 @@
     geometry->TotalCylinders  = ATA_CYLS(id_buf);
 
-  } 
-  
-  /* MT: if neither ATA nor BIOS supply valid data, or if their
-   * 	 CHS values result in a sector count lower than determined,
-   *     we use a typical [SCSI] BIOS algorithm 
-   */
-  if ((u32) geometry->NumHeads * (u32) geometry->SectorsPerTrack *
-	  (u32) geometry->TotalCylinders < geometry->TotalSectors) {
+  } else {
+    /* use typical SCSI geometry */
     geometry->NumHeads        = 255;
     geometry->SectorsPerTrack = 63;
Index: /trunk/src/os2ahci/ctxhook.c
===================================================================
--- /trunk/src/os2ahci/ctxhook.c	(revision 79)
+++ /trunk/src/os2ahci/ctxhook.c	(revision 80)
@@ -38,4 +38,5 @@
 /* port reset context hook and input data */
 ULONG           reset_ctxhook_h;
+ULONG           th_reset_watchdog;
 volatile u32    ports_to_reset[MAX_AD];
 IORB_QUEUE      abort_queue;
@@ -284,4 +285,10 @@
   spin_lock(drv_lock);
 
+  if (th_reset_watchdog != 0) {
+    /* watchdog timer still active -- just reset it */
+    ADD_CancelTimer(th_reset_watchdog);
+    th_reset_watchdog = 0;
+  }
+
   /* add ports of active IORBs from the abort queue to ports_to_reset[] */
   for (iorb = abort_queue.root; iorb != NULL; iorb = next) {
Index: /trunk/src/os2ahci/os2ahci.c
===================================================================
--- /trunk/src/os2ahci/os2ahci.c	(revision 79)
+++ /trunk/src/os2ahci/os2ahci.c	(revision 80)
@@ -101,5 +101,5 @@
 /* apapter/port-specific options saved when parsing the command line */
 u8              emulate_scsi[MAX_AD][AHCI_MAX_PORTS];
-u8              disable_ncq[MAX_AD][AHCI_MAX_PORTS];
+u8              enable_ncq[MAX_AD][AHCI_MAX_PORTS];
 u8              link_speed[MAX_AD][AHCI_MAX_PORTS];
 u8              link_power[MAX_AD][AHCI_MAX_PORTS];
@@ -261,5 +261,5 @@
       case 'n':
         /* disable NCQ */
-        set_port_option(disable_ncq, !invert_option);
+        set_port_option(enable_ncq, !invert_option);
         break;
 
@@ -789,8 +789,8 @@
  *        requests.
  *
- *        In order to support applications that can't deal with ATAPI devies
+ *        In order to support applications that can't deal with ATAPI devices
  *        (i.e. need a SCSI adapter) os2ahci will optionally report ATAPI
  *        dvices as SCSI devices. The corresponding SCSI adapter doesn't
- *        really  exist and is only reported here for the IOCM_GET_DEVICETABLE
+ *        really exist and is only reported here for the IOCM_GET_DEVICETABLE
  *        request. The units attached to this adapter will use the real HW
  *        unit IDs, thus we'll never receive a command specific to the
@@ -1164,5 +1164,5 @@
 
 /******************************************************************************
- * Complete an IORB. It should be called without the adapter-level spinlock
+ * Complete an IORB. This should be called without the adapter-level spinlock
  * to allow the IORB completion routine to perform whatever processing it
  * requires. This implies that the IORB should no longer be in any global
@@ -1220,5 +1220,6 @@
 /******************************************************************************
  * Lock the adapter, waiting for availability if necessary. This is expected
- * to be called without the driver-level spinlock aquired.
+ * to be called at task/request time without the driver-level spinlock
+ * aquired. Don't call at interrupt time.
  */
 void lock_adapter(AD_INFO *ai)
@@ -1282,4 +1283,34 @@
    */
   DevHelp_ArmCtxHook(0, reset_ctxhook_h);
+
+  /* Set up a watchdog timer which calls the context hook manually in case
+   * some kernel thread is looping around the IORB_COMPLETE status bit
+   * without yielding the CPU (kernel threads don't preempt). This shouldn't
+   * happen per design because kernel threads are supposed to yield but it
+   * does in the early boot phase.
+   */
+  ADD_StartTimerMS(&th_reset_watchdog, 5000, (PFN) reset_watchdog, 0, 0);
+}
+
+/******************************************************************************
+ * Reset handler watchdog. If a timeout occurs, a context hook is armed which
+ * will execute as soon as a kernel thread yields the CPU. However, some
+ * kernel components won't yield the CPU during the early boot phase and the
+ * only way to kick some sense into those components is to run the context
+ * hook right inside this timer callback. Not exactly pretty, especially
+ * considering the fact that context hooks were implemented to prevent running
+ * lengthy operations like a port reset at task time, but without this
+ * watchdog mechanism we run the risk of getting completely stalled by device
+ * problems during the early boot phase.
+ */
+void _cdecl _far reset_watchdog(ULONG timer_handle, ULONG p1,
+                                ULONG p2)
+{
+  /* reset watchdog timer */
+  ADD_CancelTimer(timer_handle);
+  dprintf("reset watchdog invoked\n");
+
+  /* call context hook manually */
+  reset_ctxhook(0);
 }
 
Index: /trunk/src/os2ahci/os2ahci.def
===================================================================
--- /trunk/src/os2ahci/os2ahci.def	(revision 79)
+++ /trunk/src/os2ahci/os2ahci.def	(revision 80)
@@ -1,4 +1,4 @@
 library os2ahci
-Description '$@#thi.guten (www.thiguten.de):1.00.20110224#@OS/2 AHCI Adapter Device Driver'
+Description '$@#thi.guten (www.thiguten.de):1.00.20110228#@OS/2 AHCI Adapter Device Driver'
 protmode
 
Index: /trunk/src/os2ahci/os2ahci.h
===================================================================
--- /trunk/src/os2ahci/os2ahci.h	(revision 79)
+++ /trunk/src/os2ahci/os2ahci.h	(revision 80)
@@ -383,4 +383,5 @@
 extern void    unlock_adapter         (AD_INFO *ai);
 extern void _cdecl _far timeout_callback    (ULONG timer_handle, ULONG p1, ULONG p2);
+extern void _cdecl _far reset_watchdog      (ULONG timer_handle, ULONG p1, ULONG p2);
 
 /* ahci.c */
@@ -499,4 +500,5 @@
 /* port reset context hook and input data */
 extern ULONG         reset_ctxhook_h;
+extern ULONG         th_reset_watchdog;
 extern volatile u32  ports_to_reset[MAX_AD];
 extern IORB_QUEUE    abort_queue;
@@ -507,5 +509,5 @@
 /* apapter/port-specific options saved when parsing the command line */
 extern u8            emulate_scsi[MAX_AD][AHCI_MAX_PORTS];
-extern u8            disable_ncq[MAX_AD][AHCI_MAX_PORTS];
+extern u8            enable_ncq[MAX_AD][AHCI_MAX_PORTS];
 extern u8            link_speed[MAX_AD][AHCI_MAX_PORTS];
 extern u8            link_power[MAX_AD][AHCI_MAX_PORTS];
Index: /trunk/src/os2ahci/pci.c
===================================================================
--- /trunk/src/os2ahci/pci.c	(revision 79)
+++ /trunk/src/os2ahci/pci.c	(revision 80)
@@ -183,5 +183,5 @@
  * other strings
  */
-static char s_already_claimed[] = "Warning: device already claimed by other driver.\n";
+static char s_already_claimed[] = "Warning: device already claimed by another driver.\n";
 
 
@@ -684,6 +684,5 @@
    *       the MMIO base address register (BAR), read back the resulting value
    *       and check the 0 bits from the right end. After doing this, we must
-   *       restore the original value set up by the BIOS because we're not yet
-   *       ready to take over.
+   *       restore the original value set up by the BIOS.
    *
    * The least significant 4 bits are not relevant for the MMIO address, thus
@@ -713,6 +712,6 @@
        mmio_size <<= 1);
 
-  ddprintf("MMIO size            = %ld\n", mmio_size);
-  ddprintf("MMIO address (BIOS)  = 0x%08lx\n", mmio_bios & 0xfffffff0UL);
+  ddprintf("MMIO size    = %ld\n", mmio_size);
+  ddprintf("MMIO address = 0x%08lx\n", mmio_bios & 0xfffffff0UL);
 
   /* register BIOS MMIO address space with resource manager */
@@ -724,51 +723,13 @@
 
   ret = RMAllocResource(rm_drvh, &ad_info->rm_mmio, &resource);
-
   if (ret != RMRC_SUCCESS) {
     if (ret == RMRC_RES_ALREADY_CLAIMED) {
-      /* MT: according to my observations, this is the 2nd place
-       * where we could fail due to the adapter having been already
-       * claimed by another driver...
-       */
       cprintf(s_already_claimed);
-      return;
+    } else {
+      cprintf("error: couldn't register MMIO region (rc = %d)\n", ret);
     }
-    /* didn't work; try to find another MMIO region */
-    cprintf("warning: BIOS MMIO address not accepted by resource manager "
-            "(code %d)\n", ret);
-    memset(&resource, 0x00, sizeof(resource));
-    resource.ResourceType         = RS_TYPE_MEM;
-    resource.MEMResource.MemSize  = mmio_size;
-    resource.MEMResource.MemFlags = RS_MEM_EXCLUSIVE | RS_SEARCH;
-    
-    ret = RMAllocResource(rm_drvh, &ad_info->rm_mmio, &resource);
-    
-    if (ret == RMRC_SUCCESS) {
-      /* MT: got a new address from Resource Manager; now we
-       * need to tell PCI about the new address.
-       * Leave the last 4 bits of the original MMIO value alone.
-       */
-      mmio_bios = (mmio_bios & 0x0000000fUL) |
-        (resource.MEMResource.MemBase & 0xfffffff0UL);
-      ddprintf("address we got from RM: 0x%08lx\n",
-               resource.MEMResource.MemBase);
-      ddprintf("setting new MMIO addr to 0x%08lx\n", mmio_bios);
-      
-      if (pci_write_conf(bus, dev_func, AHCI_MMIO,
-                         sizeof(u32), mmio_bios) != OH_SUCCESS) {
-        /* failed to update MMIO address - bail out */
-        cprintf("error: couldn't update MMIO address\n");
-        ret = ~RMRC_SUCCESS;
-        return;
-      }
-    }
-  }
-
-  if (ret != RMRC_SUCCESS) {
-    cprintf("error: couldn't register MMIO region (rc = %d)\n", ret);
     return;
   }
   rc_list->hResource[rc_list->NumResource++] = ad_info->rm_mmio;
-  ddprintf("MMIO address (final) = 0x%08lx\n", resource.MEMResource.MemBase);
 
   /****************************************************************************
Index: /trunk/src/os2ahci/version.h
===================================================================
--- /trunk/src/os2ahci/version.h	(revision 79)
+++ /trunk/src/os2ahci/version.h	(revision 80)
@@ -6,5 +6,5 @@
 
 
-#define VERSION            105       /* driver version (2 implied decimals) */
+#define VERSION            106       /* driver version (2 implied decimals) */
 
 /* BLDLEVEL information (in C source modules added via macro
