source: trunk/src/os2ahci/pci.c@ 78

Last change on this file since 78 was 77, checked in by chris, 15 years ago
  • Further fixes to automatic ATAPI sense handling, now supporting sense buffers larger than 64 bytes if requested by initiator (cdrecord wanted 96 bytes)
  • Separate, and internally handled, spinlock for libc malloc/free calls to reduce chances of memory corruption if somebody forgets to get the driver-level spinlock before calling malloc/free. There was no real problem with that, just some awkward code fragments which look much better now.
  • Link power management implemented
  • More generic support for adapter/port options so all of them can now have a global, adapter or port scope
  • Generic support for inverting driver options (i.e. turn them off with '!')
  • Thorough PCI scan is now the default; the reason it wasn't so far was a delay in Virtualbox but that was never a problem on real hardware
  • SCSI emulation for ATAPI devices; this can be enabled on global, adapter or port scope
File size: 40.4 KB
Line 
1/******************************************************************************
2 * PCI.c - PCI constants and detection code for os2ahci driver
3 *
4 * Copyright (c) 2010 Christian Mueller, Markus Thielen.
5 * Parts copied from/inspired by the LINUX ahci driver;
6 * those parts are (c) Linux AHCI/ATA maintainers
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include "os2ahci.h"
24
25/* -------------------------- macros and constants ------------------------- */
26
27/* offset of PCI base address register (BAR) in the PCI config space */
28#define PCI_BAR(reg) (0x10 + (reg) * sizeof(u32))
29
30/* offset of MMIO base address register (BAR) for AHCI adapters */
31#define AHCI_MMIO PCI_BAR(AHCI_PCI_BAR)
32
33/******************************************************************************
34 * OEMHLP constants for PCI access
35 */
36#define GENERIC_IOCTL 0x10
37#define OH_CATEGORY 0x00
38#define OH_FUNC_PCI 0x0b
39
40/* subfunctions */
41#define OH_BIOS_INFO 0x00
42#define OH_FIND_DEVICE 0x01
43#define OH_FIND_CLASS 0x02
44#define OH_READ_CONFIG 0x03
45#define OH_WRITE_CONFIG 0x04
46
47/* return codes */
48#define OH_SUCCESS 0x00
49#define OH_NOT_SUPPORTED 0x81
50#define OH_BAD_VENDOR 0x83
51#define OH_NOT_FOUND 0x86
52#define OH_BAD_REGISTER 0x87
53
54/* ------------------------ typedefs and structures ------------------------ */
55
56/******************************************************************************
57 * OEMHLP IOCtl parameter union. The parameter area is generally used as input
58 * to the OEMHLP IOCtl calls.
59 */
60typedef union {
61
62 /* query PCI BIOS information" */
63 struct {
64 UCHAR subfunction;
65 } bios_info;
66
67 /* find PCI device */
68 struct {
69 UCHAR subfunction;
70 USHORT device;
71 USHORT vendor;
72 UCHAR index;
73 } find_device;
74
75 /* find PCI class code */
76 struct {
77 UCHAR subfunction;
78 ULONG class;
79 UCHAR index;
80 } find_class;
81
82 /* read PCI configuration space */
83 struct {
84 UCHAR subfunction;
85 UCHAR bus;
86 UCHAR dev_func;
87 UCHAR reg;
88 UCHAR size;
89 } read_config;
90
91 /* write PCI configuration space */
92 struct {
93 UCHAR subfunction;
94 UCHAR bus;
95 UCHAR dev_func;
96 UCHAR reg;
97 UCHAR size;
98 ULONG data;
99 } write_config;
100
101} OH_PARM;
102
103/******************************************************************************
104 * OEMHLP IOCtl data union. The data area is generally used as output from the
105 * OEMHLP IOCtl calls.
106 */
107typedef union {
108
109 /* query PCI BIOS information" */
110 struct {
111 UCHAR rc;
112 UCHAR hw_mech;
113 UCHAR major_version;
114 UCHAR minor_version;
115 UCHAR last_bus;
116 } bios_info;
117
118 /* find PCI device */
119 struct {
120 UCHAR rc;
121 UCHAR bus;
122 UCHAR dev_func;
123 } find_device;
124
125 /* find PCI class code */
126 struct {
127 UCHAR rc;
128 UCHAR bus;
129 UCHAR dev_func;
130 } find_class;
131
132 /* read PCI confguration space */
133 struct {
134 UCHAR rc;
135 ULONG data;
136 } read_config;
137
138 /* write PCI confguration space */
139 struct {
140 UCHAR rc;
141 } write_config;
142
143} OH_DATA;
144
145/* -------------------------- function prototypes -------------------------- */
146
147static void add_pci_device (PCI_ID *pci_id, OH_DATA _far *data);
148static UCHAR pci_read_conf (UCHAR bus, UCHAR dev_func, UCHAR indx,
149 UCHAR size, ULONG _far *val);
150static UCHAR pci_write_conf (UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
151 ULONG val);
152static int oemhlp_call (UCHAR subfunction, OH_PARM _far *parm,
153 OH_DATA _far *data);
154
155/* ------------------------ global/static variables ------------------------ */
156
157/******************************************************************************
158 * chipset/controller name strings
159 */
160static char chip_esb2[] = "ESB2";
161static char chip_ich8[] = "ICH8";
162static char chip_ich8m[] = "ICH8M";
163static char chip_ich9[] = "ICH9";
164static char chip_ich9m[] = "ICH9M";
165static char chip_ich10[] = "ICH10";
166static char chip_pchahci[] = "PCH AHCI";
167static char chip_pchraid[] = "PCH RAID";
168static char chip_tolapai[] = "Tolapai";
169static char chip_sb600[] = "SB600";
170static char chip_sb700[] = "SB700/800";
171static char chip_vt8251[] = "VT8251";
172static char chip_mcp65[] = "MCP65";
173static char chip_mcp67[] = "MCP67";
174static char chip_mcp73[] = "MCP73";
175static char chip_mcp77[] = "MCP77";
176static char chip_mcp79[] = "MCP79";
177static char chip_mcp89[] = "MCP689";
178static char chip_sis968[] = "968";
179
180static char s_generic[] = "Generic";
181
182/******************************************************************************
183 * other strings
184 */
185static char s_already_claimed[] = "Warning: device already claimed by other driver.\n";
186
187
188
189/******************************************************************************
190 * PCI vendor and device IDs for known AHCI adapters. Copied from the Linux
191 * AHCI driver.
192 */
193
194PCI_ID pci_ids[] = {
195
196 /* Intel
197 * NOTE: ICH5 controller does NOT support AHCI, so we do
198 * not add it here! */
199 { PCI_VDEVICE(INTEL, 0x2652), board_ahci, "ICH6" }, /* ICH6 */
200 { PCI_VDEVICE(INTEL, 0x2653), board_ahci, "ICH6M" }, /* ICH6M */
201 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci, "ICH7" }, /* ICH7 */
202 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci, "ICH7M" }, /* ICH7M */
203 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci, "ICH7R" }, /* ICH7R */
204 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr, "ULiM5288" }, /* ULi M5288 */
205 { PCI_VDEVICE(INTEL, 0x2681), board_ahci, chip_esb2 }, /* ESB2 */
206 { PCI_VDEVICE(INTEL, 0x2682), board_ahci, chip_esb2 }, /* ESB2 */
207 { PCI_VDEVICE(INTEL, 0x2683), board_ahci, chip_esb2 }, /* ESB2 */
208 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci, "ICH7MDH" }, /* ICH7-M DH */
209 { PCI_VDEVICE(INTEL, 0x2821), board_ahci, chip_ich8 }, /* ICH8 */
210 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf, chip_ich8 }, /* ICH8 */
211 { PCI_VDEVICE(INTEL, 0x2824), board_ahci, chip_ich8 }, /* ICH8 */
212 { PCI_VDEVICE(INTEL, 0x2829), board_ahci, chip_ich8m }, /* ICH8M */
213 { PCI_VDEVICE(INTEL, 0x282a), board_ahci, chip_ich8m }, /* ICH8M */
214 { PCI_VDEVICE(INTEL, 0x2922), board_ahci, chip_ich9 }, /* ICH9 */
215 { PCI_VDEVICE(INTEL, 0x2923), board_ahci, chip_ich9 }, /* ICH9 */
216 { PCI_VDEVICE(INTEL, 0x2924), board_ahci, chip_ich9 }, /* ICH9 */
217 { PCI_VDEVICE(INTEL, 0x2925), board_ahci, chip_ich9 }, /* ICH9 */
218 { PCI_VDEVICE(INTEL, 0x2927), board_ahci, chip_ich9 }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x2929), board_ahci, chip_ich9m }, /* ICH9M */
220 { PCI_VDEVICE(INTEL, 0x292a), board_ahci, chip_ich9m }, /* ICH9M */
221 { PCI_VDEVICE(INTEL, 0x292b), board_ahci, chip_ich9m }, /* ICH9M */
222 { PCI_VDEVICE(INTEL, 0x292c), board_ahci, chip_ich9m }, /* ICH9M */
223 { PCI_VDEVICE(INTEL, 0x292f), board_ahci, chip_ich9m }, /* ICH9M */
224 { PCI_VDEVICE(INTEL, 0x294d), board_ahci, chip_ich9 }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x294e), board_ahci, chip_ich9m }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x502a), board_ahci, chip_tolapai }, /* Tolapai */
227 { PCI_VDEVICE(INTEL, 0x502b), board_ahci, chip_tolapai }, /* Tolapai */
228 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci, chip_ich10 }, /* ICH10 */
229 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci, chip_ich10 }, /* ICH10 */
230 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci, chip_ich10 }, /* ICH10 */
231 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci, chip_pchahci }, /* PCH AHCI */
232 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci, chip_pchahci }, /* PCH AHCI */
233 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci, chip_pchraid }, /* PCH RAID */
234 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci, chip_pchraid }, /* PCH RAID */
235 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci, chip_pchahci }, /* PCH AHCI */
236 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci, chip_pchraid }, /* PCH RAID */
237 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci, chip_pchraid }, /* PCH RAID */
238 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci, chip_pchahci }, /* PCH AHCI */
239
240 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
241 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
242 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffffL, board_ahci_ign_iferr, "360" },
243
244 /* ATI */
245 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600, chip_sb600 }, /* ATI SB600 */
246 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
247 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
248 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
249 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
250 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
251 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
252
253 /* AMD */
254 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
255 /* AMD is using RAID class only for ahci controllers */
256 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
257 PCI_CLASS_STORAGE_RAID << 8, 0xffffffL, board_ahci, "Hudson2" },
258
259 /* VIA */
260 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251, chip_vt8251 }, /* VIA VT8251 */
261 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251, chip_vt8251 }, /* VIA VT8251 */
262
263 /* NVIDIA */
264 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
265 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
266 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
267 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
268 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
269 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
270 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
271 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
272 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
273 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
274 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
275 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
276 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
277 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
278 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
279 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
280 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
281 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
282 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
283 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
284 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq, chip_mcp67 }, /* Linux ID */
285 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
286 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
287 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
288 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
289 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
290 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
291 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
292 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
293 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
294 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
295 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
296 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
297 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci, chip_mcp77 }, /* MCP77 */
298 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci, chip_mcp77 }, /* MCP77 */
299 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci, chip_mcp77 }, /* MCP77 */
300 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci, chip_mcp77 }, /* MCP77 */
301 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci, chip_mcp77 }, /* MCP77 */
302 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci, chip_mcp77 }, /* MCP77 */
303 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci, chip_mcp77 }, /* MCP77 */
304 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci, chip_mcp77 }, /* MCP77 */
305 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci, chip_mcp77 }, /* MCP77 */
306 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci, chip_mcp77 }, /* MCP77 */
307 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci, chip_mcp77 }, /* MCP77 */
308 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci, chip_mcp77 }, /* MCP77 */
309 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci, chip_mcp79 }, /* MCP79 */
310 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci, chip_mcp79 }, /* MCP79 */
311 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci, chip_mcp79 }, /* MCP79 */
312 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci, chip_mcp79 }, /* MCP79 */
313 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci, chip_mcp79 }, /* MCP79 */
314 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci, chip_mcp79 }, /* MCP79 */
315 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci, chip_mcp79 }, /* MCP79 */
316 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci, chip_mcp79 }, /* MCP79 */
317 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci, chip_mcp79 }, /* MCP79 */
318 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci, chip_mcp79 }, /* MCP79 */
319 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci, chip_mcp79 }, /* MCP79 */
320 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci, chip_mcp79 }, /* MCP79 */
321 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci, chip_mcp89 }, /* MCP89 */
322 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci, chip_mcp89 }, /* MCP89 */
323 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci, chip_mcp89 }, /* MCP89 */
324 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci, chip_mcp89 }, /* MCP89 */
325 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci, chip_mcp89 }, /* MCP89 */
326 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci, chip_mcp89 }, /* MCP89 */
327 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci, chip_mcp89 }, /* MCP89 */
328 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci, chip_mcp89 }, /* MCP89 */
329 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci, chip_mcp89 }, /* MCP89 */
330 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci, chip_mcp89 }, /* MCP89 */
331 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci, chip_mcp89 }, /* MCP89 */
332 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci, chip_mcp89 }, /* MCP89 */
333
334 /* SiS */
335 { PCI_VDEVICE(SI, 0x1184), board_ahci, "966" }, /* SiS 966 */
336 { PCI_VDEVICE(SI, 0x1185), board_ahci, chip_sis968 }, /* SiS 968 */
337 { PCI_VDEVICE(SI, 0x0186), board_ahci, chip_sis968 }, /* SiS 968 */
338
339 /* Marvell */
340 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv, "6145" }, /* 6145 */
341 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv, "6121" }, /* 6121 */
342
343 /* Promise */
344 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci, "PDC42819" }, /* PDC42819 */
345
346 /* Generic, PCI class code for AHCI */
347 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
348 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffffL, board_ahci, s_generic },
349
350 /* end of list, including a few slots to define custom adapters (10) */
351 { 0, 0, 0, 0, 0, 0, 0, NULL },
352 { 0, 0, 0, 0, 0, 0, 0, NULL },
353 { 0, 0, 0, 0, 0, 0, 0, NULL },
354 { 0, 0, 0, 0, 0, 0, 0, NULL },
355 { 0, 0, 0, 0, 0, 0, 0, NULL },
356 { 0, 0, 0, 0, 0, 0, 0, NULL },
357 { 0, 0, 0, 0, 0, 0, 0, NULL },
358 { 0, 0, 0, 0, 0, 0, 0, NULL },
359 { 0, 0, 0, 0, 0, 0, 0, NULL },
360 { 0, 0, 0, 0, 0, 0, 0, NULL },
361
362 { 0, 0, 0, 0, 0, 0, 0, NULL }
363};
364
365/******************************************************************************
366 * OEMHLP$ is used by OS/2 to provide access to OEM-specific machine resources
367 * like PCI BIOS access. We're using this to enumerate the PCI bus. Due to
368 * BIOS bugs, it may be necessary to use I/O operations for this purpose but
369 * so far I think this is only relevant for rather old PCs and SATA is not
370 * expected to be a priority on those machines.
371 */
372static IDCTABLE oemhlp; /* OEMHLP$ IDC entry point */
373
374/* ----------------------------- start of code ----------------------------- */
375
376/******************************************************************************
377 * Add specified PCI vendor and device ID to the list of supported AHCI
378 * controllers. Please note that the last slot in pci_ids needs to remain
379 * empty because it's used as end marker.
380 */
381int add_pci_id(u16 vendor, u16 device)
382{
383 int max_slot = sizeof(pci_ids) / sizeof(*pci_ids) - 2;
384 int i;
385
386 /* search for last used slot in 'pci_ids' */
387 for (i = max_slot; i >= 0 && pci_ids[i].vendor == 0; i--);
388 if (i >= max_slot) {
389 /* all slots in use */
390 return(-1);
391 }
392
393 /* use slot after the last used slot */
394 i++;
395 pci_ids[i].vendor = vendor;
396 pci_ids[i].device = device;
397 pci_ids[i].board = board_ahci;
398 pci_ids[i].chipname = s_generic;
399 return(0);
400}
401
402/******************************************************************************
403 * Scan PCI bus using OEMHLP$ IOCTLs and build adapter list.
404 */
405void scan_pci_bus(void)
406{
407 OH_PARM parm;
408 OH_DATA data;
409 UCHAR index;
410 UCHAR rc;
411 int ad_indx = 0;
412 int i;
413
414 ddprintf("scanning PCI bus...\n");
415
416 /* verify that we have a PCI system */
417 memset(&parm, 0x00, sizeof(parm));
418 if (oemhlp_call(OH_BIOS_INFO, &parm, &data) != OH_SUCCESS) {
419 cprintf("couldn't get PCI BIOS information\n");
420 return;
421 }
422
423 /* Go through the list of PCI IDs and search for each device
424 *
425 * NOTES:
426 *
427 * - When searching via class code, the OEMHLP$ interface doesn't allow
428 * setting a bitmask to look for individual portions of class code,
429 * subclass code and programming interface. However, all bitmasks in the
430 * PCI list currently use 0xffffff, thus this should not be a problem at
431 * this point in time.
432 *
433 * - Scanning via OEMHLP$ seems rather slow, at least in the virtual
434 * machine I'm currenly using to test this driver. Thus, class code
435 * scans are preferred unless the option "-t" (thorough_scan) has been
436 * specified. The assumption is that most, if not all, modern AHCI
437 * adapters have the correct class code (PCI_CLASS_STORAGE_SATA_AHCI).
438 */
439 for (i = 0; pci_ids[i].vendor != 0; i++) {
440 index = 0;
441 do {
442 if (pci_ids[i].device == PCI_ANY_ID || pci_ids[i].vendor == PCI_ANY_ID) {
443 /* look for class code */
444 memset(&parm, 0x00, sizeof(parm));
445 parm.find_class.class = pci_ids[i].class;
446 parm.find_class.index = index;
447 rc = oemhlp_call(OH_FIND_CLASS, &parm, &data);
448
449 } else if (thorough_scan) {
450 /* look for this specific vendor and device ID */
451 memset(&parm, 0x00, sizeof(parm));
452 parm.find_device.device = pci_ids[i].device;
453 parm.find_device.vendor = pci_ids[i].vendor;
454 parm.find_device.index = index;
455 rc = oemhlp_call(OH_FIND_DEVICE, &parm, &data);
456
457 } else {
458 rc = OH_NOT_FOUND;
459 }
460
461 if (rc == OH_SUCCESS) {
462 /* found a device */
463 if (ad_ignore & (1U << ad_indx++)) {
464 /* ignore this adapter */
465 continue;
466 }
467 add_pci_device(pci_ids + i, &data);
468 if (++index > 180) {
469 /* something's wrong here... */
470 return;
471 }
472 }
473
474 } while (rc == OH_SUCCESS);
475 }
476}
477
478/******************************************************************************
479 * Enable interrupt generation. PCI 2.3 added a bit which allows disabling
480 * interrupt generation for a device. This function clears the corresponding
481 * bit in the configuration space command register.
482 */
483int pci_enable_int(UCHAR bus, UCHAR dev_func)
484{
485 ULONG tmp;
486
487 if (pci_read_conf (bus, dev_func, 4, sizeof(u32), &tmp) != OH_SUCCESS ||
488 pci_write_conf(bus, dev_func, 4, sizeof(u32), tmp & ~(1UL << 10)) != OH_SUCCESS) {
489 return(-1);
490 }
491 return(0);
492}
493
494/******************************************************************************
495 * Hack to set up proper IRQ mappings in the emulated PIIX3 ISA bridge in
496 * VirtualBox (for some reason, the first mapped IRQ is 0x80 without this
497 * hack).
498 */
499void pci_hack_virtualbox(void)
500{
501 ULONG irq = 0;
502
503 if (pci_read_conf(0, 0x08, 0x60, 1, &irq) == OH_SUCCESS && irq == 0x80) {
504 /* set IRQ for first device/func to 11 */
505 dprintf("hacking virtualbox PIIX3 PCI to ISA bridge IRQ mapping\n");
506 irq = ad_infos[0].irq;
507 pci_write_conf(0, 0x08, 0x60, 1, irq);
508 }
509}
510
511/******************************************************************************
512 * Add a single PCI device to the list of adapters.
513 */
514static void add_pci_device(PCI_ID *pci_id, OH_DATA _far *data)
515{
516 char rc_list_buf[sizeof(AHRESOURCE) + sizeof(HRESOURCE) * 4];
517 AHRESOURCE _far *rc_list = (AHRESOURCE _far *) rc_list_buf;
518 RESOURCESTRUCT resource;
519 ADAPTERSTRUCT adapter;
520 ADJUNCT adj;
521 AD_INFO *ad_info;
522 APIRET ret;
523 UCHAR bus = data->find_class.bus;
524 UCHAR dev_func = data->find_class.dev_func;
525 ULONG val;
526 SEL gdt[PORT_DMA_BUF_SEGS + 1];
527 char tmp[40];
528 u16 device;
529 u16 vendor;
530 u32 class;
531 u32 mmio_bios = 0;
532 u32 mmio_size;
533 u32 mmio_rqd;
534 int irq;
535 int pin;
536 int i;
537
538 /*****************************************************************************
539 * Part 1: Get further information about the device to be added; PCI ID...
540 */
541 if (pci_read_conf(bus, dev_func, 0x00, sizeof(ULONG), &val) != OH_SUCCESS) {
542 return;
543 }
544 device = (u16) (val >> 16);
545 vendor = (u16) (val & 0xffff);
546
547 /* ... and class code */
548 if (pci_read_conf(bus, dev_func, 0x08, sizeof(ULONG), &val) != OH_SUCCESS) {
549 return;
550 }
551 class = (u32) (val >> 8);
552
553 if (pci_id->device == PCI_ANY_ID) {
554 /* We found this device in a wildcard search. There are two possible
555 * reasons which require a different handling:
556 *
557 * 1) This device uses a non-standard PCI class and has been identified
558 * with the corresponding class in pci_ids[] (e.g. the entry
559 * PCI_VENDOR_ID_JMICRON), but there is a vendor ID in pci_ids[]. In
560 * this case, we need to verify that the vendor is correct (see
561 * comments regarding OEMHLP limitations in 'scan_pci_bus()')
562 *
563 * 2) This device was identified using a generic PCI class for AHCI
564 * adapters such as PCI_CLASS_STORAGE_SATA_AHCI and we need to map
565 * the device and vendor ID to the corresponding index in pci_ids[]
566 * if there is such an entry; the index passed to this function will
567 * be the generic class-based index which is fine as long as there's
568 * not special treatment required as indicated by the board_*
569 * constants in pci_ids[]...
570 *
571 * The main reason for this kludge is that it seems as if OEMHLP$
572 * is rather slow searching for PCI devices, adding around 30s
573 * to the boot time when scanning for individual AHCI PCI IDs. Thus,
574 * the OS2AHCI driver avoids this kind of scan in favor of a class-
575 * based scan (unless overridden with the "/T" option).
576 */
577 if (pci_id->vendor != PCI_ANY_ID) {
578 /* case 1: the vendor is known but we found the PCI device using a class
579 * search; verify vendor matches the one in pci_ids[]
580 */
581 if (pci_id->vendor != vendor) {
582 /* vendor doesn't match */
583 return;
584 }
585
586 } else {
587 /* case 2: we found this device using a generic class search; if the
588 * device/vendor is listed in pci_ids[], use this entry in favor of the
589 * one passed in 'pci_id'
590 */
591 for (i = 0; pci_ids[i].vendor != 0; i++) {
592 if (pci_ids[i].device == device && pci_ids[i].vendor == vendor) {
593 pci_id = pci_ids + i;
594 break;
595 }
596 }
597 }
598 }
599
600 /* found a supported AHCI device */
601 cprintf("found AHCI device: %s %s (%04x:%04x)\n"
602 " class:0x%06lx bus:%d devfunc:0x%02x\n",
603 vendor_from_id(vendor), device_from_id(device),
604 vendor, device,
605 class, bus, dev_func);
606
607 /* make sure we got room in the adapter information array */
608 if (ad_info_cnt >= MAX_AD - 1) {
609 cprintf("error: too many AHCI devices\n");
610 return;
611 }
612
613 /****************************************************************************
614 * Part 2: Determine resource requirements and allocate resources with the
615 * OS/2 resource manager. While doing so, some of the entries of the
616 * corresponding slot in the AD_INFO array, namely resource manager
617 * handles, are initialized so we need prepare the slot.
618 *
619 * NOTE: While registering resources with the resource manager, each new
620 * resource is added to the corresponding rc_list.hResource[] slot.
621 * rc_list is used further down to associate resources to adapters
622 * when the adapter itself is registered with the OS/2 resource
623 * manager.
624 */
625 ad_info = ad_infos + ad_info_cnt;
626 memset(ad_info, 0x00, sizeof(*ad_info));
627 rc_list->NumResource = 0;
628
629 /* Register IRQ with resource manager
630 *
631 * NOTE: We rely on the IRQ number saved in the PCI config space by the PCI
632 * BIOS. There's no reliable way to find out the IRQ number in any
633 * other way unless we start using message-driven interrupts (which
634 * is out of scope for the time being).
635 */
636 if (pci_read_conf(bus, dev_func, 0x3c, sizeof(u32), &val) != OH_SUCCESS) {
637 return;
638 }
639 irq = (int) (val & 0xff);
640 pin = (int) ((val >> 8) & 0xff);
641
642 memset(&resource, 0x00, sizeof(resource));
643 resource.ResourceType = RS_TYPE_IRQ;
644 resource.IRQResource.IRQLevel = irq;
645 resource.IRQResource.PCIIrqPin = pin;
646 resource.IRQResource.IRQFlags = RS_IRQ_SHARED;
647
648 ret = RMAllocResource(rm_drvh, &ad_info->rm_irq, &resource);
649 switch (ret) {
650 case RMRC_SUCCESS:
651 break;
652 case RMRC_DEV_ALREADY_CLAIMED:
653 case RMRC_RES_ALREADY_CLAIMED:
654 cprintf(s_already_claimed);
655 return;
656 default:
657 cprintf("error: couldn't register IRQ %d (rc = %d)\n", irq, ret);
658 return;
659 }
660 rc_list->hResource[rc_list->NumResource++] = ad_info->rm_irq;
661
662 /* Determine MMIO size for this device
663 *
664 * NOTE: In order to do this, we need to temporarily write 0xffffffff to
665 * the MMIO base address register (BAR), read back the resulting value
666 * and check the 0 bits from the right end. After doing this, we must
667 * restore the original value set up by the BIOS because we're not yet
668 * ready to take over.
669 *
670 * The least significant 4 bits are not relevant for the MMIO address, thus
671 * we'll start at 0x10:
672 *
673 * 31 4 3 2 1 0
674 * -------------------------------------------------------------------
675 * base address P T T I
676 * P = prefetchable
677 * T = type
678 * I = I/O (1) or memory (0)
679 */
680 if (pci_read_conf (bus, dev_func, AHCI_MMIO, sizeof(u32), &mmio_bios) != OH_SUCCESS ||
681 pci_write_conf(bus, dev_func, AHCI_MMIO, sizeof(u32), ~(0UL)) != OH_SUCCESS ||
682 pci_read_conf (bus, dev_func, AHCI_MMIO, sizeof(u32), &mmio_rqd) != OH_SUCCESS ||
683 pci_write_conf(bus, dev_func, AHCI_MMIO, sizeof(u32), mmio_bios) != OH_SUCCESS) {
684
685 cprintf("error: couldn't determine MMIO size\n");
686 if (mmio_bios != 0) {
687 cprintf("restoring BIOS MMIO address\n");
688 pci_write_conf(bus, dev_func, AHCI_MMIO, sizeof(u32), mmio_bios);
689 }
690 return;
691 }
692 for (mmio_size = 0x00000010UL;
693 mmio_size < 0x10000000UL && (mmio_rqd & mmio_size) == 0;
694 mmio_size <<= 1);
695
696 ddprintf("MMIO size = %ld\n", mmio_size);
697 ddprintf("MMIO address (BIOS) = 0x%08lx\n", mmio_bios & 0xfffffff0UL);
698
699 /* register BIOS MMIO address space with resource manager */
700 memset(&resource, 0x00, sizeof(resource));
701 resource.ResourceType = RS_TYPE_MEM;
702 resource.MEMResource.MemBase = mmio_bios & 0xfffffff0UL;
703 resource.MEMResource.MemSize = mmio_size;
704 resource.MEMResource.MemFlags = RS_MEM_EXCLUSIVE;
705
706 ret = RMAllocResource(rm_drvh, &ad_info->rm_mmio, &resource);
707
708 if (ret != RMRC_SUCCESS) {
709 if (ret == RMRC_RES_ALREADY_CLAIMED) {
710 /* MT: according to my observations, this is the 2nd place
711 * where we could fail due to the adapter having been already
712 * claimed by another driver...
713 */
714 cprintf(s_already_claimed);
715 return;
716 }
717 /* didn't work; try to find another MMIO region */
718 cprintf("warning: BIOS MMIO address not accepted by resource manager "
719 "(code %d)\n", ret);
720 memset(&resource, 0x00, sizeof(resource));
721 resource.ResourceType = RS_TYPE_MEM;
722 resource.MEMResource.MemSize = mmio_size;
723 resource.MEMResource.MemFlags = RS_MEM_EXCLUSIVE | RS_SEARCH;
724
725 ret = RMAllocResource(rm_drvh, &ad_info->rm_mmio, &resource);
726
727 if (ret == RMRC_SUCCESS) {
728 /* MT: got a new address from Resource Manager; now we
729 * need to tell PCI about the new address.
730 * Leave the last 4 bits of the original MMIO value alone.
731 */
732 mmio_bios = (mmio_bios & 0x0000000fUL) |
733 (resource.MEMResource.MemBase & 0xfffffff0UL);
734 ddprintf("address we got from RM: 0x%08lx\n",
735 resource.MEMResource.MemBase);
736 ddprintf("setting new MMIO addr to 0x%08lx\n", mmio_bios);
737
738 if (pci_write_conf(bus, dev_func, AHCI_MMIO,
739 sizeof(u32), mmio_bios) != OH_SUCCESS) {
740 /* failed to update MMIO address - bail out */
741 cprintf("error: couldn't update MMIO address\n");
742 ret = ~RMRC_SUCCESS;
743 return;
744 }
745 }
746 }
747
748 if (ret != RMRC_SUCCESS) {
749 cprintf("error: couldn't register MMIO region (rc = %d)\n", ret);
750 return;
751 }
752 rc_list->hResource[rc_list->NumResource++] = ad_info->rm_mmio;
753 ddprintf("MMIO address (final) = 0x%08lx\n", resource.MEMResource.MemBase);
754
755 /****************************************************************************
756 * Part 3: Fill in the remaining fields in the AD_INFO slot and allocate
757 * memory and GDT selectors for the adapter. Finally, register the adapter
758 * itself with the OS/2 resource manager
759 */
760 ad_info->pci = pci_ids + i;
761 ad_info->bus = bus;
762 ad_info->dev_func = dev_func;
763 ad_info->irq = irq;
764 ad_info->mmio_phys = resource.MEMResource.MemBase;
765
766 /* allocate memory for port-specific DMA scratch buffers */
767 if (DevHelp_AllocPhys((long) AHCI_PORT_PRIV_DMA_SZ * AHCI_MAX_PORTS,
768 MEMTYPE_ABOVE_1M, &ad_info->dma_buf_phys) != 0) {
769 cprintf("error: couldn't allocate DMA scratch buffers for AHCI ports\n");
770 ad_info->dma_buf_phys = 0;
771 goto add_pci_fail;
772 }
773
774 /* allocate GDT selectors for memory-mapped I/O and DMA scratch buffers */
775 if (DevHelp_AllocGDTSelector(gdt, PORT_DMA_BUF_SEGS + 1) != 0) {
776 cprintf("error: couldn't allocate GDT selectors\n");
777 memset(gdt, 0x00, sizeof(gdt));
778 goto add_pci_fail;
779 }
780
781 /* map MMIO address to first GDT selector */
782 if (DevHelp_PhysToGDTSelector(ad_info->mmio_phys, (USHORT) mmio_size,
783 gdt[0]) != 0) {
784 cprintf("error: couldn't map MMIO address to GDT selector\n");
785 goto add_pci_fail;
786 }
787
788 /* map DMA scratch buffers to remaining GDT selectors */
789 for (i = 0; i < PORT_DMA_BUF_SEGS; i++) {
790 ULONG addr = ad_info->dma_buf_phys + i * PORT_DMA_SEG_SIZE;
791 USHORT len = AHCI_PORT_PRIV_DMA_SZ * PORT_DMA_BUFS_PER_SEG;
792
793 if (DevHelp_PhysToGDTSelector(addr, len, gdt[i+1]) != 0) {
794 cprintf("error: couldn't map DMA scratch buffer to GDT selector\n");
795 goto add_pci_fail;
796 }
797 }
798
799 /* fill in MMIO and DMA scratch buffer addresses in adapter info */
800 ad_info->mmio = (u8 _far *) ((u32) gdt[0] << 16);
801 for (i = 0; i < PORT_DMA_BUF_SEGS; i++) {
802 ad_info->dma_buf[i] = (u8 _far *) ((u32) gdt[i+1] << 16);
803 }
804
805 /* register adapter with resource manager */
806 memset(&adj, 0x00, sizeof(adj));
807 adj.pNextAdj = NULL;
808 adj.AdjLength = sizeof(adj);
809 adj.AdjType = ADJ_ADAPTER_NUMBER;
810 adj.Adapter_Number = ad_info_cnt;
811
812 memset(&adapter, 0x00, sizeof(adapter));
813 sprintf(tmp, "AHCI_%d Controller", ad_info_cnt);
814 adapter.AdaptDescriptName = tmp;
815 adapter.AdaptFlags = 0;
816 adapter.BaseType = AS_BASE_MSD;
817 adapter.SubType = AS_SUB_IDE;
818 adapter.InterfaceType = AS_INTF_GENERIC;
819 adapter.HostBusType = AS_HOSTBUS_PCI;
820 adapter.HostBusWidth = AS_BUSWIDTH_32BIT;
821 adapter.pAdjunctList = &adj;
822
823 ret = RMCreateAdapter(rm_drvh, &ad_info->rm_adh, &adapter, NULL, rc_list);
824 if (ret != RMRC_SUCCESS) {
825 cprintf("error: couldn't register adapter (rc = %d)\n", ret);
826 goto add_pci_fail;
827 }
828
829 /* Successfully added the adapter and reserved its resources; the adapter
830 * is still under BIOS control so we're not going to do anything else at
831 * this point.
832 */
833 ad_info_cnt++;
834 return;
835
836add_pci_fail:
837 /* something went wrong; try to clean up as far as possible */
838 if (ad_info->rm_mmio != 0) {
839 RMDeallocResource(rm_drvh, ad_info->rm_mmio);
840 }
841 if (ad_info->rm_irq != 0) {
842 RMDeallocResource(rm_drvh, ad_info->rm_irq);
843 }
844 if (&ad_info->dma_buf_phys != 0) {
845 DevHelp_FreePhys(ad_info->dma_buf_phys);
846 }
847 for (i = 0; i < sizeof(gdt) / sizeof(*gdt); i++) {
848 if (gdt[i] != 0) {
849 DevHelp_FreeGDTSelector(gdt[i]);
850 }
851 }
852}
853
854/******************************************************************************
855 * Read PCI configuration space register
856 */
857static UCHAR pci_read_conf(UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
858 ULONG _far *val)
859{
860 OH_PARM parm;
861 OH_DATA data;
862 UCHAR rc;
863
864 memset(&parm, 0x00, sizeof(parm));
865 parm.read_config.bus = bus;
866 parm.read_config.dev_func = dev_func;
867 parm.read_config.reg = indx;
868 parm.read_config.size = size;
869 if ((rc = oemhlp_call(OH_READ_CONFIG, &parm, &data) != OH_SUCCESS)) {
870 cprintf("error: couldn't read config space (bus = %d, dev_func = 0x%02x, indx = 0x%02x, rc = %d)\n",
871 bus, dev_func, indx, rc);
872 return(rc);
873 }
874
875 *val = data.read_config.data;
876 return(OH_SUCCESS);
877}
878
879/******************************************************************************
880 * Write PCI configuration space register
881 */
882static UCHAR pci_write_conf(UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
883 ULONG val)
884{
885 OH_PARM parm;
886 OH_DATA data;
887 UCHAR rc;
888
889 memset(&parm, 0x00, sizeof(parm));
890 parm.write_config.bus = bus;
891 parm.write_config.dev_func = dev_func;
892 parm.write_config.reg = indx;
893 parm.write_config.size = size;
894 parm.write_config.data = val;
895
896 if ((rc = oemhlp_call(OH_WRITE_CONFIG, &parm, &data) != OH_SUCCESS)) {
897 cprintf("error: couldn't write config space (bus = %d, dev_func = 0x%02x, indx = 0x%02x, rc = %d)\n",
898 bus, dev_func, indx, rc);
899 return(rc);
900 }
901
902 return(OH_SUCCESS);
903}
904/******************************************************************************
905 * Call OEMHLP$ IDC entry point with the specified IOCtl parameter and data
906 * packets.
907 */
908static int oemhlp_call(UCHAR subfunction, OH_PARM _far *parm,
909 OH_DATA _far *data)
910{
911 void (_far *func)(void);
912 RP_GENIOCTL ioctl;
913 unsigned short prot_idc_ds;
914
915 if (oemhlp.ProtIDCEntry == NULL || oemhlp.ProtIDC_DS == 0) {
916 /* attach to OEMHLP$ device driver */
917 if (DevHelp_AttachDD("OEMHLP$ ", (NPBYTE) &oemhlp) ||
918 oemhlp.ProtIDCEntry == NULL ||
919 oemhlp.ProtIDC_DS == 0) {
920 cprintf("couldn't attach to OEMHLP$\n");
921 return(OH_NOT_SUPPORTED);
922 }
923 }
924
925 /* store subfuntion in first byte of pararameter packet */
926 parm->bios_info.subfunction = subfunction;
927 memset(data, 0x00, sizeof(*data));
928
929 /* assemble IOCtl request */
930 memset(&ioctl, 0x00, sizeof(ioctl));
931 ioctl.rph.Len = sizeof(ioctl);
932 ioctl.rph.Unit = 0;
933 ioctl.rph.Cmd = GENERIC_IOCTL;
934 ioctl.rph.Status = 0;
935
936 ioctl.Category = OH_CATEGORY;
937 ioctl.Function = OH_FUNC_PCI;
938 ioctl.ParmPacket = (PUCHAR) parm;
939 ioctl.DataPacket = (PUCHAR) data;
940 ioctl.ParmLen = sizeof(*parm);
941 ioctl.DataLen = sizeof(*data);
942
943 /* Call OEMHLP's IDC routine. Before doing so, we need to assign the address
944 * to be called to a stack variable because the inter-device driver calling
945 * convention forces us to set DS to the device driver's data segment and ES
946 * to the segment of the request packet.
947 */
948 func = oemhlp.ProtIDCEntry;
949
950 /* The WATCOM compiler does not support struct references in inline
951 * assembler code, so we pass it in a stack variable
952 */
953 prot_idc_ds = oemhlp.ProtIDC_DS;
954
955 _asm {
956 push ds;
957 push es;
958 push bx;
959 push si;
960 push di;
961
962 push ss
963 pop es
964 lea bx, ioctl;
965 mov ds, prot_idc_ds;
966 call dword ptr [func];
967
968 pop di;
969 pop si;
970 pop bx;
971 pop es;
972 pop ds;
973 }
974
975 dddphex(parm, sizeof(*parm), "oemhlp_parm: ");
976 dddphex(data, sizeof(*data), "oemhlp_data: ");
977
978 if (ioctl.rph.Status & STERR) {
979 return(OH_NOT_SUPPORTED);
980 }
981 return(data->bios_info.rc);
982}
983
984/******************************************************************************
985 * return vendor name for PCI vendor ID
986 */
987char *vendor_from_id(u16 id)
988{
989
990 switch(id) {
991
992 case PCI_VENDOR_ID_AL:
993 return "Ali";
994 case PCI_VENDOR_ID_AMD:
995 case PCI_VENDOR_ID_ATI:
996 return "AMD";
997 case PCI_VENDOR_ID_AT:
998 return "Allied Telesyn";
999 case PCI_VENDOR_ID_ATT:
1000 return "ATT";
1001 case PCI_VENDOR_ID_CMD:
1002 return "CMD";
1003 case PCI_VENDOR_ID_CT:
1004 return "CT";
1005 case PCI_VENDOR_ID_INTEL:
1006 return "Intel";
1007 case PCI_VENDOR_ID_INITIO:
1008 return "Initio";
1009 case PCI_VENDOR_ID_JMICRON:
1010 return "JMicron";
1011 case PCI_VENDOR_ID_MARVELL:
1012 return "Marvell";
1013 case PCI_VENDOR_ID_NVIDIA:
1014 return "NVIDIA";
1015 case PCI_VENDOR_ID_PROMISE:
1016 return "PROMISE";
1017 case PCI_VENDOR_ID_SI:
1018 return "SiS";
1019 case PCI_VENDOR_ID_VIA:
1020 return "VIA";
1021 default:
1022 break;
1023 }
1024
1025 return "Generic";
1026
1027}
1028
1029/******************************************************************************
1030 * return a device name for a PCI device id
1031 * NOTE: this is as simple as can be, so don't call it twice in one statement.
1032 */
1033char *device_from_id(u16 device)
1034{
1035 int i;
1036
1037 for (i = 0; pci_ids[i].vendor != 0; i++) {
1038
1039 if (pci_ids[i].device == device) {
1040 return pci_ids[i].chipname;
1041 }
1042
1043 }
1044
1045 return s_generic;
1046}
Note: See TracBrowser for help on using the repository browser.