| 1 | /******************************************************************************
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| 2 | * PCI.c - PCI constants and detection code for os2ahci driver
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| 3 | *
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| 4 | * Copyright (c) 2010 Christian Mueller, Markus Thielen.
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| 5 | * Parts copied from/inspired by the LINUX ahci driver;
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| 6 | * those parts are (c) Linux AHCI/ATA maintainers
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| 7 | *
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| 8 | * This program is free software; you can redistribute it and/or modify
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| 9 | * it under the terms of the GNU General Public License as published by
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| 10 | * the Free Software Foundation; either version 2 of the License, or
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| 11 | * (at your option) any later version.
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| 12 | *
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| 13 | * This program is distributed in the hope that it will be useful,
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| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 16 | * GNU General Public License for more details.
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| 17 | *
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| 18 | * You should have received a copy of the GNU General Public License
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| 19 | * along with this program; if not, write to the Free Software
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| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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| 21 | */
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| 22 |
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| 23 | #include "os2ahci.h"
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| 24 |
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| 25 | /* -------------------------- macros and constants ------------------------- */
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| 26 |
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| 27 | /* offset of PCI base address register (BAR) in the PCI config space */
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| 28 | #define PCI_BAR(reg) (0x10 + (reg) * sizeof(u32))
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| 29 |
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| 30 | /* offset of MMIO base address register (BAR) for AHCI adapters */
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| 31 | #define AHCI_MMIO PCI_BAR(AHCI_PCI_BAR)
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| 32 |
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| 33 | /******************************************************************************
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| 34 | * OEMHLP constants for PCI access
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| 35 | */
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| 36 | #define GENERIC_IOCTL 0x10
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| 37 | #define OH_CATEGORY 0x00
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| 38 | #define OH_FUNC_PCI 0x0b
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| 39 |
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| 40 | /* subfunctions */
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| 41 | #define OH_BIOS_INFO 0x00
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| 42 | #define OH_FIND_DEVICE 0x01
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| 43 | #define OH_FIND_CLASS 0x02
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| 44 | #define OH_READ_CONFIG 0x03
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| 45 | #define OH_WRITE_CONFIG 0x04
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| 46 |
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| 47 | /* return codes */
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| 48 | #define OH_SUCCESS 0x00
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| 49 | #define OH_NOT_SUPPORTED 0x81
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| 50 | #define OH_BAD_VENDOR 0x83
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| 51 | #define OH_NOT_FOUND 0x86
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| 52 | #define OH_BAD_REGISTER 0x87
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| 53 |
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| 54 | /* ------------------------ typedefs and structures ------------------------ */
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| 55 |
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| 56 | /******************************************************************************
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| 57 | * OEMHLP IOCtl parameter union. The parameter area is generally used as input
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| 58 | * to the OEMHLP IOCtl calls.
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| 59 | */
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| 60 | typedef union {
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| 61 |
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| 62 | /* query PCI BIOS information" */
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| 63 | struct {
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| 64 | UCHAR subfunction;
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| 65 | } bios_info;
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| 66 |
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| 67 | /* find PCI device */
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| 68 | struct {
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| 69 | UCHAR subfunction;
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| 70 | USHORT device;
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| 71 | USHORT vendor;
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| 72 | UCHAR index;
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| 73 | } find_device;
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| 74 |
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| 75 | /* find PCI class code */
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| 76 | struct {
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| 77 | UCHAR subfunction;
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| 78 | ULONG class;
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| 79 | UCHAR index;
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| 80 | } find_class;
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| 81 |
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| 82 | /* read PCI configuration space */
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| 83 | struct {
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| 84 | UCHAR subfunction;
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| 85 | UCHAR bus;
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| 86 | UCHAR dev_func;
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| 87 | UCHAR reg;
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| 88 | UCHAR size;
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| 89 | } read_config;
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| 90 |
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| 91 | /* write PCI configuration space */
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| 92 | struct {
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| 93 | UCHAR subfunction;
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| 94 | UCHAR bus;
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| 95 | UCHAR dev_func;
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| 96 | UCHAR reg;
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| 97 | UCHAR size;
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| 98 | ULONG data;
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| 99 | } write_config;
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| 100 |
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| 101 | } OH_PARM;
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| 102 |
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| 103 | /******************************************************************************
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| 104 | * OEMHLP IOCtl data union. The data area is generally used as output from the
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| 105 | * OEMHLP IOCtl calls.
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| 106 | */
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| 107 | typedef union {
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| 108 |
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| 109 | /* query PCI BIOS information" */
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| 110 | struct {
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| 111 | UCHAR rc;
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| 112 | UCHAR hw_mech;
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| 113 | UCHAR major_version;
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| 114 | UCHAR minor_version;
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| 115 | UCHAR last_bus;
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| 116 | } bios_info;
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| 117 |
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| 118 | /* find PCI device */
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| 119 | struct {
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| 120 | UCHAR rc;
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| 121 | UCHAR bus;
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| 122 | UCHAR dev_func;
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| 123 | } find_device;
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| 124 |
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| 125 | /* find PCI class code */
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| 126 | struct {
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| 127 | UCHAR rc;
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| 128 | UCHAR bus;
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| 129 | UCHAR dev_func;
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| 130 | } find_class;
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| 131 |
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| 132 | /* read PCI confguration space */
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| 133 | struct {
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| 134 | UCHAR rc;
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| 135 | ULONG data;
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| 136 | } read_config;
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| 137 |
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| 138 | /* write PCI confguration space */
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| 139 | struct {
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| 140 | UCHAR rc;
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| 141 | } write_config;
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| 142 |
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| 143 | } OH_DATA;
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| 144 |
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| 145 | /* -------------------------- function prototypes -------------------------- */
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| 146 |
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| 147 | static void add_pci_device (PCI_ID *pci_id, OH_DATA _far *data);
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| 148 | static UCHAR pci_read_conf (UCHAR bus, UCHAR dev_func, UCHAR indx,
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| 149 | UCHAR size, ULONG _far *val);
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| 150 | static UCHAR pci_write_conf (UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
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| 151 | ULONG val);
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| 152 | static int oemhlp_call (UCHAR subfunction, OH_PARM _far *parm,
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| 153 | OH_DATA _far *data);
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| 154 |
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| 155 | /* ------------------------ global/static variables ------------------------ */
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| 156 |
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| 157 | /******************************************************************************
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| 158 | * chipset/controller name strings
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| 159 | */
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| 160 | static char chip_esb2[] = "ESB2";
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| 161 | static char chip_ich8[] = "ICH8";
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| 162 | static char chip_ich8m[] = "ICH8M";
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| 163 | static char chip_ich9[] = "ICH9";
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| 164 | static char chip_ich9m[] = "ICH9M";
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| 165 | static char chip_ich10[] = "ICH10";
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| 166 | static char chip_pchahci[] = "PCH AHCI";
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| 167 | static char chip_pchraid[] = "PCH RAID";
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| 168 | static char chip_tolapai[] = "Tolapai";
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| 169 | static char chip_sb600[] = "SB600";
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| 170 | static char chip_sb700[] = "SB700/800";
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| 171 | static char chip_vt8251[] = "VT8251";
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| 172 | static char chip_mcp65[] = "MCP65";
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| 173 | static char chip_mcp67[] = "MCP67";
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| 174 | static char chip_mcp73[] = "MCP73";
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| 175 | static char chip_mcp77[] = "MCP77";
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| 176 | static char chip_mcp79[] = "MCP79";
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| 177 | static char chip_mcp89[] = "MCP689";
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| 178 | static char chip_sis968[] = "968";
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| 179 |
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| 180 | static char s_generic[] = "Generic";
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| 181 |
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| 182 |
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| 183 |
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| 184 | /******************************************************************************
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| 185 | * PCI vendor and device IDs for known AHCI adapters. Copied from the Linux
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| 186 | * AHCI driver.
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| 187 | */
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| 188 |
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| 189 | PCI_ID pci_ids[] = {
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| 190 |
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| 191 | /* Intel
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| 192 | * NOTE: ICH5 controller does NOT support AHCI, so we do
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| 193 | * not add it here! */
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| 194 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci, "ICH6" }, /* ICH6 */
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| 195 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci, "ICH6M" }, /* ICH6M */
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| 196 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci, "ICH7" }, /* ICH7 */
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| 197 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci, "ICH7M" }, /* ICH7M */
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| 198 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci, "ICH7R" }, /* ICH7R */
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| 199 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr, "ULiM5288" }, /* ULi M5288 */
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| 200 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci, chip_esb2 }, /* ESB2 */
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| 201 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci, chip_esb2 }, /* ESB2 */
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| 202 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci, chip_esb2 }, /* ESB2 */
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| 203 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci, "ICH7MDH" }, /* ICH7-M DH */
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| 204 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci, chip_ich8 }, /* ICH8 */
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| 205 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf, chip_ich8 }, /* ICH8 */
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| 206 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci, chip_ich8 }, /* ICH8 */
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| 207 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci, chip_ich8m }, /* ICH8M */
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| 208 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci, chip_ich8m }, /* ICH8M */
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| 209 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci, chip_ich9 }, /* ICH9 */
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| 210 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci, chip_ich9 }, /* ICH9 */
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| 211 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci, chip_ich9 }, /* ICH9 */
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| 212 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci, chip_ich9 }, /* ICH9 */
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| 213 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci, chip_ich9 }, /* ICH9 */
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| 214 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci, chip_ich9m }, /* ICH9M */
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| 215 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci, chip_ich9m }, /* ICH9M */
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| 216 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci, chip_ich9m }, /* ICH9M */
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| 217 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci, chip_ich9m }, /* ICH9M */
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| 218 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci, chip_ich9m }, /* ICH9M */
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| 219 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci, chip_ich9 }, /* ICH9 */
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| 220 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci, chip_ich9m }, /* ICH9M */
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| 221 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci, chip_tolapai }, /* Tolapai */
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| 222 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci, chip_tolapai }, /* Tolapai */
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| 223 | { PCI_VDEVICE(INTEL, 0x3a05), board_ahci, chip_ich10 }, /* ICH10 */
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| 224 | { PCI_VDEVICE(INTEL, 0x3a22), board_ahci, chip_ich10 }, /* ICH10 */
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| 225 | { PCI_VDEVICE(INTEL, 0x3a25), board_ahci, chip_ich10 }, /* ICH10 */
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| 226 | { PCI_VDEVICE(INTEL, 0x3b22), board_ahci, chip_pchahci }, /* PCH AHCI */
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| 227 | { PCI_VDEVICE(INTEL, 0x3b23), board_ahci, chip_pchahci }, /* PCH AHCI */
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| 228 | { PCI_VDEVICE(INTEL, 0x3b24), board_ahci, chip_pchraid }, /* PCH RAID */
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| 229 | { PCI_VDEVICE(INTEL, 0x3b25), board_ahci, chip_pchraid }, /* PCH RAID */
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| 230 | { PCI_VDEVICE(INTEL, 0x3b29), board_ahci, chip_pchahci }, /* PCH AHCI */
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| 231 | { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci, chip_pchraid }, /* PCH RAID */
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| 232 | { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci, chip_pchraid }, /* PCH RAID */
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| 233 | { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci, chip_pchahci }, /* PCH AHCI */
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| 234 |
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| 235 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */
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| 236 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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| 237 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffffL, board_ahci_ign_iferr, "360" },
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| 238 |
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| 239 | /* ATI */
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| 240 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600, chip_sb600 }, /* ATI SB600 */
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| 241 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
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| 242 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
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| 243 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
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| 244 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
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| 245 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
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| 246 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
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| 247 |
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| 248 | /* AMD */
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| 249 | { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
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| 250 | /* AMD is using RAID class only for ahci controllers */
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| 251 | { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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| 252 | PCI_CLASS_STORAGE_RAID << 8, 0xffffffL, board_ahci, "Hudson2" },
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| 253 |
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| 254 | /* VIA */
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| 255 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251, chip_vt8251 }, /* VIA VT8251 */
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| 256 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251, chip_vt8251 }, /* VIA VT8251 */
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| 257 |
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| 258 | /* NVIDIA */
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| 259 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
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| 260 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
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| 261 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
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| 262 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
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| 263 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
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| 264 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
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| 265 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
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| 266 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
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| 267 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
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| 268 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
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| 269 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
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| 270 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
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| 271 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
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| 272 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
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| 273 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
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| 274 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
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| 275 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
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| 276 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
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| 277 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
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| 278 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
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| 279 | { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq, chip_mcp67 }, /* Linux ID */
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| 280 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
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| 281 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
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| 282 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
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| 283 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
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| 284 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
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| 285 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
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| 286 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
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| 287 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
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| 288 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
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| 289 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
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| 290 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
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| 291 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
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| 292 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci, chip_mcp77 }, /* MCP77 */
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| 293 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci, chip_mcp77 }, /* MCP77 */
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| 294 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci, chip_mcp77 }, /* MCP77 */
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| 295 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci, chip_mcp77 }, /* MCP77 */
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| 296 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci, chip_mcp77 }, /* MCP77 */
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| 297 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci, chip_mcp77 }, /* MCP77 */
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| 298 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci, chip_mcp77 }, /* MCP77 */
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| 299 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci, chip_mcp77 }, /* MCP77 */
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| 300 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci, chip_mcp77 }, /* MCP77 */
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| 301 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci, chip_mcp77 }, /* MCP77 */
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| 302 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci, chip_mcp77 }, /* MCP77 */
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| 303 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci, chip_mcp77 }, /* MCP77 */
|
|---|
| 304 | { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci, chip_mcp79 }, /* MCP79 */
|
|---|
| 305 | { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci, chip_mcp79 }, /* MCP79 */
|
|---|
| 306 | { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci, chip_mcp79 }, /* MCP79 */
|
|---|
| 307 | { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci, chip_mcp79 }, /* MCP79 */
|
|---|
| 308 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci, chip_mcp79 }, /* MCP79 */
|
|---|
| 309 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci, chip_mcp79 }, /* MCP79 */
|
|---|
| 310 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci, chip_mcp79 }, /* MCP79 */
|
|---|
| 311 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci, chip_mcp79 }, /* MCP79 */
|
|---|
| 312 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci, chip_mcp79 }, /* MCP79 */
|
|---|
| 313 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci, chip_mcp79 }, /* MCP79 */
|
|---|
| 314 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci, chip_mcp79 }, /* MCP79 */
|
|---|
| 315 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci, chip_mcp79 }, /* MCP79 */
|
|---|
| 316 | { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci, chip_mcp89 }, /* MCP89 */
|
|---|
| 317 | { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci, chip_mcp89 }, /* MCP89 */
|
|---|
| 318 | { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci, chip_mcp89 }, /* MCP89 */
|
|---|
| 319 | { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci, chip_mcp89 }, /* MCP89 */
|
|---|
| 320 | { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci, chip_mcp89 }, /* MCP89 */
|
|---|
| 321 | { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci, chip_mcp89 }, /* MCP89 */
|
|---|
| 322 | { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci, chip_mcp89 }, /* MCP89 */
|
|---|
| 323 | { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci, chip_mcp89 }, /* MCP89 */
|
|---|
| 324 | { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci, chip_mcp89 }, /* MCP89 */
|
|---|
| 325 | { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci, chip_mcp89 }, /* MCP89 */
|
|---|
| 326 | { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci, chip_mcp89 }, /* MCP89 */
|
|---|
| 327 | { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci, chip_mcp89 }, /* MCP89 */
|
|---|
| 328 |
|
|---|
| 329 | /* SiS */
|
|---|
| 330 | { PCI_VDEVICE(SI, 0x1184), board_ahci, "966" }, /* SiS 966 */
|
|---|
| 331 | { PCI_VDEVICE(SI, 0x1185), board_ahci, chip_sis968 }, /* SiS 968 */
|
|---|
| 332 | { PCI_VDEVICE(SI, 0x0186), board_ahci, chip_sis968 }, /* SiS 968 */
|
|---|
| 333 |
|
|---|
| 334 | /* Marvell */
|
|---|
| 335 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv, "6145" }, /* 6145 */
|
|---|
| 336 | { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv, "6121" }, /* 6121 */
|
|---|
| 337 |
|
|---|
| 338 | /* Promise */
|
|---|
| 339 | { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci, "PDC42819" }, /* PDC42819 */
|
|---|
| 340 |
|
|---|
| 341 | /* Generic, PCI class code for AHCI */
|
|---|
| 342 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
|---|
| 343 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffffL, board_ahci, s_generic },
|
|---|
| 344 |
|
|---|
| 345 | /* end of list, including a few slots to define custom adapters (10) */
|
|---|
| 346 | { 0, 0, 0, 0, 0, 0, 0, NULL },
|
|---|
| 347 | { 0, 0, 0, 0, 0, 0, 0, NULL },
|
|---|
| 348 | { 0, 0, 0, 0, 0, 0, 0, NULL },
|
|---|
| 349 | { 0, 0, 0, 0, 0, 0, 0, NULL },
|
|---|
| 350 | { 0, 0, 0, 0, 0, 0, 0, NULL },
|
|---|
| 351 | { 0, 0, 0, 0, 0, 0, 0, NULL },
|
|---|
| 352 | { 0, 0, 0, 0, 0, 0, 0, NULL },
|
|---|
| 353 | { 0, 0, 0, 0, 0, 0, 0, NULL },
|
|---|
| 354 | { 0, 0, 0, 0, 0, 0, 0, NULL },
|
|---|
| 355 | { 0, 0, 0, 0, 0, 0, 0, NULL },
|
|---|
| 356 |
|
|---|
| 357 | { 0, 0, 0, 0, 0, 0, 0, NULL }
|
|---|
| 358 | };
|
|---|
| 359 |
|
|---|
| 360 | /******************************************************************************
|
|---|
| 361 | * OEMHLP$ is used by OS/2 to provide access to OEM-specific machine resources
|
|---|
| 362 | * like PCI BIOS access. We're using this to enumerate the PCI bus. Due to
|
|---|
| 363 | * BIOS bugs, it may be necessary to use I/O operations for this purpose but
|
|---|
| 364 | * so far I think this is only relevant for rather old PCs and SATA is not
|
|---|
| 365 | * expected to be a priority on those machines.
|
|---|
| 366 | */
|
|---|
| 367 | static IDCTABLE oemhlp; /* OEMHLP$ IDC entry point */
|
|---|
| 368 |
|
|---|
| 369 | /* ----------------------------- start of code ----------------------------- */
|
|---|
| 370 |
|
|---|
| 371 | /******************************************************************************
|
|---|
| 372 | * Add specified PCI vendor and device ID to the list of supported AHCI
|
|---|
| 373 | * controllers. Please note that the last slot in pci_ids needs to remain
|
|---|
| 374 | * empty because it's used as end marker.
|
|---|
| 375 | */
|
|---|
| 376 | int add_pci_id(u16 vendor, u16 device)
|
|---|
| 377 | {
|
|---|
| 378 | int max_slot = sizeof(pci_ids) / sizeof(*pci_ids) - 2;
|
|---|
| 379 | int i;
|
|---|
| 380 |
|
|---|
| 381 | /* search for last used slot in 'pci_ids' */
|
|---|
| 382 | for (i = max_slot; i >= 0 && pci_ids[i].vendor == 0; i--);
|
|---|
| 383 | if (i >= max_slot) {
|
|---|
| 384 | /* all slots in use */
|
|---|
| 385 | return(-1);
|
|---|
| 386 | }
|
|---|
| 387 |
|
|---|
| 388 | /* use slot after the last used slot */
|
|---|
| 389 | i++;
|
|---|
| 390 | pci_ids[i].vendor = vendor;
|
|---|
| 391 | pci_ids[i].device = device;
|
|---|
| 392 | pci_ids[i].board = board_ahci;
|
|---|
| 393 | pci_ids[i].chipname = s_generic;
|
|---|
| 394 | return(0);
|
|---|
| 395 | }
|
|---|
| 396 |
|
|---|
| 397 | /******************************************************************************
|
|---|
| 398 | * Scan PCI bus using OEMHLP$ IOCTLs and build adapter list.
|
|---|
| 399 | */
|
|---|
| 400 | void scan_pci_bus(void)
|
|---|
| 401 | {
|
|---|
| 402 | OH_PARM parm;
|
|---|
| 403 | OH_DATA data;
|
|---|
| 404 | UCHAR index;
|
|---|
| 405 | UCHAR rc;
|
|---|
| 406 | int i;
|
|---|
| 407 |
|
|---|
| 408 | ddprintf("scanning PCI bus...\n");
|
|---|
| 409 |
|
|---|
| 410 | /* verify that we have a PCI system */
|
|---|
| 411 | memset(&parm, 0x00, sizeof(parm));
|
|---|
| 412 | if (oemhlp_call(OH_BIOS_INFO, &parm, &data) != OH_SUCCESS) {
|
|---|
| 413 | cprintf("couldn't get PCI BIOS information\n");
|
|---|
| 414 | return;
|
|---|
| 415 | }
|
|---|
| 416 |
|
|---|
| 417 | /* Go through the list of PCI IDs and search for each device
|
|---|
| 418 | *
|
|---|
| 419 | * NOTES:
|
|---|
| 420 | *
|
|---|
| 421 | * - When searching via class code, the OEMHLP$ interface doesn't allow
|
|---|
| 422 | * setting a bitmask to look for individual portions of class code,
|
|---|
| 423 | * subclass code and programming interface. However, all bitmasks in the
|
|---|
| 424 | * PCI list currently use 0xffffff, thus this should not be a problem at
|
|---|
| 425 | * this point in time.
|
|---|
| 426 | *
|
|---|
| 427 | * - Scanning via OEMHLP$ seems rather slow, at least in the virtual
|
|---|
| 428 | * machine I'm currenly using to test this driver. Thus, class code
|
|---|
| 429 | * scans are preferred unless the option "-t" (thorough_scan) has been
|
|---|
| 430 | * specified. The assumption is that most, if not all, modern AHCI
|
|---|
| 431 | * adapters have the correct class code (PCI_CLASS_STORAGE_SATA_AHCI).
|
|---|
| 432 | */
|
|---|
| 433 | for (i = 0; pci_ids[i].vendor != 0; i++) {
|
|---|
| 434 | index = 0;
|
|---|
| 435 | do {
|
|---|
| 436 | if (pci_ids[i].device == PCI_ANY_ID || pci_ids[i].vendor == PCI_ANY_ID) {
|
|---|
| 437 | /* look for class code */
|
|---|
| 438 | memset(&parm, 0x00, sizeof(parm));
|
|---|
| 439 | parm.find_class.class = pci_ids[i].class;
|
|---|
| 440 | parm.find_class.index = index;
|
|---|
| 441 | rc = oemhlp_call(OH_FIND_CLASS, &parm, &data);
|
|---|
| 442 |
|
|---|
| 443 | } else if (thorough_scan) {
|
|---|
| 444 | /* look for this specific vendor and device ID */
|
|---|
| 445 | memset(&parm, 0x00, sizeof(parm));
|
|---|
| 446 | parm.find_device.device = pci_ids[i].device;
|
|---|
| 447 | parm.find_device.vendor = pci_ids[i].vendor;
|
|---|
| 448 | parm.find_device.index = index;
|
|---|
| 449 | rc = oemhlp_call(OH_FIND_DEVICE, &parm, &data);
|
|---|
| 450 |
|
|---|
| 451 | } else {
|
|---|
| 452 | rc = OH_NOT_FOUND;
|
|---|
| 453 | }
|
|---|
| 454 |
|
|---|
| 455 | if (rc == OH_SUCCESS) {
|
|---|
| 456 | /* found a device */
|
|---|
| 457 | add_pci_device(pci_ids + i, &data);
|
|---|
| 458 | if (++index > 180) {
|
|---|
| 459 | /* something's wrong here... */
|
|---|
| 460 | return;
|
|---|
| 461 | }
|
|---|
| 462 | }
|
|---|
| 463 |
|
|---|
| 464 | } while (rc == OH_SUCCESS);
|
|---|
| 465 | }
|
|---|
| 466 | }
|
|---|
| 467 |
|
|---|
| 468 | /******************************************************************************
|
|---|
| 469 | * Enable interrupt generation. PCI 2.3 added a bit which allows disabling
|
|---|
| 470 | * interrupt generation for a device. This function clears the corresponding
|
|---|
| 471 | * bit in the configuration space command register.
|
|---|
| 472 | */
|
|---|
| 473 | int pci_enable_int(UCHAR bus, UCHAR dev_func)
|
|---|
| 474 | {
|
|---|
| 475 | ULONG tmp;
|
|---|
| 476 |
|
|---|
| 477 | if (pci_read_conf (bus, dev_func, 4, sizeof(u32), &tmp) != OH_SUCCESS ||
|
|---|
| 478 | pci_write_conf(bus, dev_func, 4, sizeof(u32), tmp & ~(1UL << 10)) != OH_SUCCESS) {
|
|---|
| 479 | return(-1);
|
|---|
| 480 | }
|
|---|
| 481 | return(0);
|
|---|
| 482 | }
|
|---|
| 483 |
|
|---|
| 484 | /******************************************************************************
|
|---|
| 485 | * Hack to set up proper IRQ mappings in the emulated PIIX3 ISA bridge in
|
|---|
| 486 | * VirtualBox (for some reason, the first mapped IRQ is 0x80 without this
|
|---|
| 487 | * hack).
|
|---|
| 488 | */
|
|---|
| 489 | void pci_hack_virtualbox(void)
|
|---|
| 490 | {
|
|---|
| 491 | ULONG irq = 0;
|
|---|
| 492 |
|
|---|
| 493 | if (pci_read_conf(0, 0x08, 0x60, 1, &irq) == OH_SUCCESS && irq == 0x80) {
|
|---|
| 494 | /* set IRQ for first device/func to 11 */
|
|---|
| 495 | dprintf("hacking virtualbox PIIX3 PCI to ISA bridge IRQ mapping\n");
|
|---|
| 496 | irq = ad_infos[0].irq;
|
|---|
| 497 | pci_write_conf(0, 0x08, 0x60, 1, irq);
|
|---|
| 498 | }
|
|---|
| 499 | }
|
|---|
| 500 |
|
|---|
| 501 | /******************************************************************************
|
|---|
| 502 | * Add a single PCI device to the list of adapters.
|
|---|
| 503 | */
|
|---|
| 504 | static void add_pci_device(PCI_ID *pci_id, OH_DATA _far *data)
|
|---|
| 505 | {
|
|---|
| 506 | char rc_list_buf[sizeof(AHRESOURCE) + sizeof(HRESOURCE) * 4];
|
|---|
| 507 | AHRESOURCE _far *rc_list = (AHRESOURCE _far *) rc_list_buf;
|
|---|
| 508 | RESOURCESTRUCT resource;
|
|---|
| 509 | ADAPTERSTRUCT adapter;
|
|---|
| 510 | ADJUNCT adj;
|
|---|
| 511 | AD_INFO *ad_info;
|
|---|
| 512 | APIRET ret;
|
|---|
| 513 | UCHAR bus = data->find_class.bus;
|
|---|
| 514 | UCHAR dev_func = data->find_class.dev_func;
|
|---|
| 515 | ULONG val;
|
|---|
| 516 | SEL gdt[PORT_DMA_BUF_SEGS + 1];
|
|---|
| 517 | char tmp[40];
|
|---|
| 518 | u16 device;
|
|---|
| 519 | u16 vendor;
|
|---|
| 520 | u32 class;
|
|---|
| 521 | u32 mmio_bios = 0;
|
|---|
| 522 | u32 mmio_size;
|
|---|
| 523 | u32 mmio_rqd;
|
|---|
| 524 | int irq;
|
|---|
| 525 | int pin;
|
|---|
| 526 | int i;
|
|---|
| 527 |
|
|---|
| 528 | /*****************************************************************************
|
|---|
| 529 | * Part 1: Get further information about the device to be added; PCI ID...
|
|---|
| 530 | */
|
|---|
| 531 | if (pci_read_conf(bus, dev_func, 0x00, sizeof(ULONG), &val) != OH_SUCCESS) {
|
|---|
| 532 | return;
|
|---|
| 533 | }
|
|---|
| 534 | device = (u16) (val >> 16);
|
|---|
| 535 | vendor = (u16) (val & 0xffff);
|
|---|
| 536 |
|
|---|
| 537 | /* ... and class code */
|
|---|
| 538 | if (pci_read_conf(bus, dev_func, 0x08, sizeof(ULONG), &val) != OH_SUCCESS) {
|
|---|
| 539 | return;
|
|---|
| 540 | }
|
|---|
| 541 | class = (u32) (val >> 8);
|
|---|
| 542 |
|
|---|
| 543 | if (pci_id->device == PCI_ANY_ID) {
|
|---|
| 544 | /* We found this device in a wildcard search. There are two possible
|
|---|
| 545 | * reasons which require a different handling:
|
|---|
| 546 | *
|
|---|
| 547 | * 1) This device uses a non-standard PCI class and has been identified
|
|---|
| 548 | * with the corresponding class in pci_ids[] (e.g. the entry
|
|---|
| 549 | * PCI_VENDOR_ID_JMICRON), but there is a vendor ID in pci_ids[]. In
|
|---|
| 550 | * this case, we need to verify that the vendor is correct (see
|
|---|
| 551 | * comments regarding OEMHLP limitations in 'scan_pci_bus()')
|
|---|
| 552 | *
|
|---|
| 553 | * 2) This device was identified using a generic PCI class for AHCI
|
|---|
| 554 | * adapters such as PCI_CLASS_STORAGE_SATA_AHCI and we need to map
|
|---|
| 555 | * the device and vendor ID to the corresponding index in pci_ids[]
|
|---|
| 556 | * if there is such an entry; the index passed to this function will
|
|---|
| 557 | * be the generic class-based index which is fine as long as there's
|
|---|
| 558 | * not special treatment required as indicated by the board_*
|
|---|
| 559 | * constants in pci_ids[]...
|
|---|
| 560 | *
|
|---|
| 561 | * The main reason for this kludge is that it seems as if OEMHLP$
|
|---|
| 562 | * is rather slow searching for PCI devices, adding around 30s
|
|---|
| 563 | * to the boot time when scanning for individual AHCI PCI IDs. Thus,
|
|---|
| 564 | * the OS2AHCI driver avoids this kind of scan in favor of a class-
|
|---|
| 565 | * based scan (unless overridden with the "/T" option).
|
|---|
| 566 | */
|
|---|
| 567 | if (pci_id->vendor != PCI_ANY_ID) {
|
|---|
| 568 | /* case 1: the vendor is known but we found the PCI device using a class
|
|---|
| 569 | * search; verify vendor matches the one in pci_ids[]
|
|---|
| 570 | */
|
|---|
| 571 | if (pci_id->vendor != vendor) {
|
|---|
| 572 | /* vendor doesn't match */
|
|---|
| 573 | return;
|
|---|
| 574 | }
|
|---|
| 575 |
|
|---|
| 576 | } else {
|
|---|
| 577 | /* case 2: we found this device using a generic class search; if the
|
|---|
| 578 | * device/vendor is listed in pci_ids[], use this entry in favor of the
|
|---|
| 579 | * one passed in 'pci_id'
|
|---|
| 580 | */
|
|---|
| 581 | for (i = 0; pci_ids[i].vendor != 0; i++) {
|
|---|
| 582 | if (pci_ids[i].device == device && pci_ids[i].vendor == vendor) {
|
|---|
| 583 | pci_id = pci_ids + i;
|
|---|
| 584 | break;
|
|---|
| 585 | }
|
|---|
| 586 | }
|
|---|
| 587 | }
|
|---|
| 588 | }
|
|---|
| 589 |
|
|---|
| 590 | /* found a supported AHCI device */
|
|---|
| 591 | cprintf("found AHCI device: %s %s (%04x:%04x)\n"
|
|---|
| 592 | " class:0x%06lx bus:%d devfunc:0x%02x\n",
|
|---|
| 593 | vendor_from_id(vendor), device_from_id(device),
|
|---|
| 594 | vendor, device,
|
|---|
| 595 | class, bus, dev_func);
|
|---|
| 596 |
|
|---|
| 597 | /* make sure we got room in the adapter information array */
|
|---|
| 598 | if (ad_info_cnt >= MAX_AD - 1) {
|
|---|
| 599 | cprintf("error: too many AHCI devices\n");
|
|---|
| 600 | return;
|
|---|
| 601 | }
|
|---|
| 602 |
|
|---|
| 603 | /****************************************************************************
|
|---|
| 604 | * Part 2: Determine resource requirements and allocate resources with the
|
|---|
| 605 | * OS/2 resource manager. While doing so, some of the entries of the
|
|---|
| 606 | * corresponding slot in the AD_INFO array, namely resource manager
|
|---|
| 607 | * handles, are initialized so we need prepare the slot.
|
|---|
| 608 | *
|
|---|
| 609 | * NOTE: While registering resources with the resource manager, each new
|
|---|
| 610 | * resource is added to the corresponding rc_list.hResource[] slot.
|
|---|
| 611 | * rc_list is used further down to associate resources to adapters
|
|---|
| 612 | * whe the adapter itself is registered with the OS/2 resource manager.
|
|---|
| 613 | */
|
|---|
| 614 | ad_info = ad_infos + ad_info_cnt;
|
|---|
| 615 | memset(ad_info, 0x00, sizeof(*ad_info));
|
|---|
| 616 | rc_list->NumResource = 0;
|
|---|
| 617 |
|
|---|
| 618 | /* Register IRQ with resource manager
|
|---|
| 619 | *
|
|---|
| 620 | * NOTE: We rely on the IRQ number saved in the PCI config space by the PCI
|
|---|
| 621 | * BIOS. There's no reliable way to find out the IRQ number in any
|
|---|
| 622 | * other way unless we start using message-driven interrupts (which
|
|---|
| 623 | * is out of scope for the time being).
|
|---|
| 624 | */
|
|---|
| 625 | if (pci_read_conf(bus, dev_func, 0x3c, sizeof(u32), &val) != OH_SUCCESS) {
|
|---|
| 626 | return;
|
|---|
| 627 | }
|
|---|
| 628 | irq = (int) (val & 0xff);
|
|---|
| 629 | pin = (int) ((val >> 8) & 0xff);
|
|---|
| 630 |
|
|---|
| 631 | memset(&resource, 0x00, sizeof(resource));
|
|---|
| 632 | resource.ResourceType = RS_TYPE_IRQ;
|
|---|
| 633 | resource.IRQResource.IRQLevel = irq;
|
|---|
| 634 | resource.IRQResource.PCIIrqPin = pin;
|
|---|
| 635 | resource.IRQResource.IRQFlags = RS_IRQ_SHARED;
|
|---|
| 636 |
|
|---|
| 637 | ret = RMAllocResource(rm_drvh, &ad_info->rm_irq, &resource);
|
|---|
| 638 | switch (ret) {
|
|---|
| 639 | case RMRC_SUCCESS:
|
|---|
| 640 | break;
|
|---|
| 641 | case RMRC_DEV_ALREADY_CLAIMED:
|
|---|
| 642 | case RMRC_RES_ALREADY_CLAIMED:
|
|---|
| 643 | cprintf("warning: device already claimed by other driver\n");
|
|---|
| 644 | return;
|
|---|
| 645 | default:
|
|---|
| 646 | cprintf("error: couldn't register IRQ %d (rc = %d)\n", irq, ret);
|
|---|
| 647 | return;
|
|---|
| 648 | }
|
|---|
| 649 | rc_list->hResource[rc_list->NumResource++] = ad_info->rm_irq;
|
|---|
| 650 |
|
|---|
| 651 | /* Determine MMIO size for this device
|
|---|
| 652 | *
|
|---|
| 653 | * NOTE: In order to do this, we need to temporarily write 0xffffffff to
|
|---|
| 654 | * the MMIO base address register (BAR), read back the resulting value
|
|---|
| 655 | * and check the 0 bits from the right end. After doing this, we must
|
|---|
| 656 | * restore the original value set up by the BIOS because we're not yet
|
|---|
| 657 | * ready to take over.
|
|---|
| 658 | *
|
|---|
| 659 | * The least significant 4 bits are not relevant for the MMIO address, thus
|
|---|
| 660 | * we'll start at 0x10:
|
|---|
| 661 | *
|
|---|
| 662 | * 31 4 3 2 1 0
|
|---|
| 663 | * -------------------------------------------------------------------
|
|---|
| 664 | * base address P T T I
|
|---|
| 665 | * P = prefetchable
|
|---|
| 666 | * T = type
|
|---|
| 667 | * I = I/O (1) or memory (0)
|
|---|
| 668 | */
|
|---|
| 669 | if (pci_read_conf (bus, dev_func, AHCI_MMIO, sizeof(u32), &mmio_bios) != OH_SUCCESS ||
|
|---|
| 670 | pci_write_conf(bus, dev_func, AHCI_MMIO, sizeof(u32), ~(0UL)) != OH_SUCCESS ||
|
|---|
| 671 | pci_read_conf (bus, dev_func, AHCI_MMIO, sizeof(u32), &mmio_rqd) != OH_SUCCESS ||
|
|---|
| 672 | pci_write_conf(bus, dev_func, AHCI_MMIO, sizeof(u32), mmio_bios) != OH_SUCCESS) {
|
|---|
| 673 |
|
|---|
| 674 | cprintf("error: couldn't determine MMIO size\n");
|
|---|
| 675 | if (mmio_bios != 0) {
|
|---|
| 676 | cprintf("restoring BIOS MMIO address\n");
|
|---|
| 677 | pci_write_conf(bus, dev_func, AHCI_MMIO, sizeof(u32), mmio_bios);
|
|---|
| 678 | }
|
|---|
| 679 | goto add_pci_fail;
|
|---|
| 680 | }
|
|---|
| 681 | for (mmio_size = 0x00000010UL;
|
|---|
| 682 | mmio_size < 0x10000000UL && (mmio_rqd & mmio_size) == 0;
|
|---|
| 683 | mmio_size <<= 1);
|
|---|
| 684 |
|
|---|
| 685 | ddprintf("MMIO size = %ld\n", mmio_size);
|
|---|
| 686 | ddprintf("MMIO address (BIOS) = 0x%08lx\n", mmio_bios & 0xfffffff0UL);
|
|---|
| 687 |
|
|---|
| 688 | /* register BIOS MMIO address space with resource manager */
|
|---|
| 689 | memset(&resource, 0x00, sizeof(resource));
|
|---|
| 690 | resource.ResourceType = RS_TYPE_MEM;
|
|---|
| 691 | resource.MEMResource.MemBase = mmio_bios & 0xfffffff0UL;
|
|---|
| 692 | resource.MEMResource.MemSize = mmio_size;
|
|---|
| 693 | resource.MEMResource.MemFlags = RS_MEM_EXCLUSIVE;
|
|---|
| 694 |
|
|---|
| 695 | ret = RMAllocResource(rm_drvh, &ad_info->rm_mmio, &resource);
|
|---|
| 696 |
|
|---|
| 697 | if (ret != RMRC_SUCCESS) {
|
|---|
| 698 | /* didn't work; try to find another MMIO region */
|
|---|
| 699 | cprintf("warning: BIOS MMIO address not accepted by resource manager\n");
|
|---|
| 700 | memset(&resource, 0x00, sizeof(resource));
|
|---|
| 701 | resource.ResourceType = RS_TYPE_MEM;
|
|---|
| 702 | resource.MEMResource.MemSize = mmio_size;
|
|---|
| 703 | resource.MEMResource.MemFlags = RS_MEM_EXCLUSIVE | RS_SEARCH;
|
|---|
| 704 |
|
|---|
| 705 | ret = RMAllocResource(rm_drvh, &ad_info->rm_mmio, &resource);
|
|---|
| 706 |
|
|---|
| 707 | if (ret == RMRC_SUCCESS) {
|
|---|
| 708 | /* MT: got a new address from Resource Manager; now we
|
|---|
| 709 | * need to tell PCI about the new address.
|
|---|
| 710 | * Leave the last 4 bits of the original MMIO value alone.
|
|---|
| 711 | */
|
|---|
| 712 | mmio_bios = (mmio_bios & 0x0000000fUL) |
|
|---|
| 713 | (resource.MEMResource.MemBase & 0xfffffff0UL);
|
|---|
| 714 | ddprintf("address we got from RM: 0x%08lx\n",
|
|---|
| 715 | resource.MEMResource.MemBase);
|
|---|
| 716 | ddprintf("setting new MMIO addr to 0x%08lx\n", mmio_bios);
|
|---|
| 717 |
|
|---|
| 718 | if (pci_write_conf(bus, dev_func, AHCI_MMIO,
|
|---|
| 719 | sizeof(u32), mmio_bios) != OH_SUCCESS) {
|
|---|
| 720 | /* failed to update MMIO address - bail out */
|
|---|
| 721 | cprintf("error: couldn't update MMIO address\n");
|
|---|
| 722 | ret = ~RMRC_SUCCESS;
|
|---|
| 723 | goto add_pci_fail;
|
|---|
| 724 | }
|
|---|
| 725 |
|
|---|
| 726 | }
|
|---|
| 727 | }
|
|---|
| 728 |
|
|---|
| 729 | if (ret != RMRC_SUCCESS) {
|
|---|
| 730 | cprintf("error: couldn't register MMIO region (rc = %d)\n", ret);
|
|---|
| 731 | goto add_pci_fail;
|
|---|
| 732 | }
|
|---|
| 733 | rc_list->hResource[rc_list->NumResource++] = ad_info->rm_mmio;
|
|---|
| 734 | ddprintf("MMIO address (final) = 0x%08lx\n", resource.MEMResource.MemBase);
|
|---|
| 735 |
|
|---|
| 736 | /****************************************************************************
|
|---|
| 737 | * Part 3: Fill in the remaining fields in the AD_INFO slot and allocate
|
|---|
| 738 | * memory and GDT selectors for the adapter. Finally, register the adapter
|
|---|
| 739 | * itself with the OS/2 resource manager
|
|---|
| 740 | */
|
|---|
| 741 | ad_info->pci = pci_ids + i;
|
|---|
| 742 | ad_info->bus = bus;
|
|---|
| 743 | ad_info->dev_func = dev_func;
|
|---|
| 744 | ad_info->irq = irq;
|
|---|
| 745 | ad_info->mmio_phys = resource.MEMResource.MemBase;
|
|---|
| 746 |
|
|---|
| 747 | /* allocate memory for port-specific DMA scratch buffers */
|
|---|
| 748 | if (DevHelp_AllocPhys((long) AHCI_PORT_PRIV_DMA_SZ * AHCI_MAX_PORTS,
|
|---|
| 749 | MEMTYPE_ABOVE_1M, &ad_info->dma_buf_phys) != 0) {
|
|---|
| 750 | cprintf("error: couldn't allocate DMA scratch buffers for AHCI ports\n");
|
|---|
| 751 | ad_info->dma_buf_phys = 0;
|
|---|
| 752 | goto add_pci_fail;
|
|---|
| 753 | }
|
|---|
| 754 |
|
|---|
| 755 | /* allocate GDT selectors for memory-mapped I/O and DMA scratch buffers */
|
|---|
| 756 | if (DevHelp_AllocGDTSelector(gdt, PORT_DMA_BUF_SEGS + 1) != 0) {
|
|---|
| 757 | cprintf("error: couldn't allocate GDT selectors\n");
|
|---|
| 758 | memset(gdt, 0x00, sizeof(gdt));
|
|---|
| 759 | goto add_pci_fail;
|
|---|
| 760 | }
|
|---|
| 761 |
|
|---|
| 762 | /* map MMIO address to first GDT selector */
|
|---|
| 763 | if (DevHelp_PhysToGDTSelector(ad_info->mmio_phys, (USHORT) mmio_size,
|
|---|
| 764 | gdt[0]) != 0) {
|
|---|
| 765 | cprintf("error: couldn't map MMIO address to GDT selector\n");
|
|---|
| 766 | goto add_pci_fail;
|
|---|
| 767 | }
|
|---|
| 768 |
|
|---|
| 769 | /* map DMA scratch buffers to remaining GDT selectors */
|
|---|
| 770 | for (i = 0; i < PORT_DMA_BUF_SEGS; i++) {
|
|---|
| 771 | ULONG addr = ad_info->dma_buf_phys + i * PORT_DMA_SEG_SIZE;
|
|---|
| 772 | USHORT len = AHCI_PORT_PRIV_DMA_SZ * PORT_DMA_BUFS_PER_SEG;
|
|---|
| 773 |
|
|---|
| 774 | if (DevHelp_PhysToGDTSelector(addr, len, gdt[i+1]) != 0) {
|
|---|
| 775 | cprintf("error: couldn't map DMA scratch buffer to GDT selector\n");
|
|---|
| 776 | goto add_pci_fail;
|
|---|
| 777 | }
|
|---|
| 778 | }
|
|---|
| 779 |
|
|---|
| 780 | /* fill in MMIO and DMA scratch buffer addresses in adapter info */
|
|---|
| 781 | ad_info->mmio = (u8 _far *) ((u32) gdt[0] << 16);
|
|---|
| 782 | for (i = 0; i < PORT_DMA_BUF_SEGS; i++) {
|
|---|
| 783 | ad_info->dma_buf[i] = (u8 _far *) ((u32) gdt[i+1] << 16);
|
|---|
| 784 | }
|
|---|
| 785 |
|
|---|
| 786 | /* register adapter with resource manager */
|
|---|
| 787 | memset(&adj, 0x00, sizeof(adj));
|
|---|
| 788 | adj.pNextAdj = NULL;
|
|---|
| 789 | adj.AdjLength = sizeof(adj);
|
|---|
| 790 | adj.AdjType = ADJ_ADAPTER_NUMBER;
|
|---|
| 791 | adj.Adapter_Number = ad_info_cnt;
|
|---|
| 792 |
|
|---|
| 793 | memset(&adapter, 0x00, sizeof(adapter));
|
|---|
| 794 | sprintf(tmp, "AHCI_%d Controller", ad_info_cnt);
|
|---|
| 795 | adapter.AdaptDescriptName = tmp;
|
|---|
| 796 | adapter.AdaptFlags = 0;
|
|---|
| 797 | adapter.BaseType = AS_BASE_MSD;
|
|---|
| 798 | adapter.SubType = AS_SUB_IDE;
|
|---|
| 799 | adapter.InterfaceType = AS_INTF_GENERIC;
|
|---|
| 800 | adapter.HostBusType = AS_HOSTBUS_PCI;
|
|---|
| 801 | adapter.HostBusWidth = AS_BUSWIDTH_32BIT;
|
|---|
| 802 | adapter.pAdjunctList = &adj;
|
|---|
| 803 |
|
|---|
| 804 | ret = RMCreateAdapter(rm_drvh, &ad_info->rm_adh, &adapter, NULL, rc_list);
|
|---|
| 805 | if (ret != RMRC_SUCCESS) {
|
|---|
| 806 | cprintf("error: couldn't register adapter (rc = %d)\n", ret);
|
|---|
| 807 | goto add_pci_fail;
|
|---|
| 808 | }
|
|---|
| 809 |
|
|---|
| 810 | /* Successfully added the adapter and reserved its resources; the adapter
|
|---|
| 811 | * is still under BIOS control so we're not going to do anything else at
|
|---|
| 812 | * this point.
|
|---|
| 813 | */
|
|---|
| 814 | ad_info_cnt++;
|
|---|
| 815 | return;
|
|---|
| 816 |
|
|---|
| 817 | add_pci_fail:
|
|---|
| 818 | /* something went wrong; try to clean up as far as possible */
|
|---|
| 819 | if (ad_info->rm_mmio != 0) {
|
|---|
| 820 | RMDeallocResource(rm_drvh, ad_info->rm_mmio);
|
|---|
| 821 | }
|
|---|
| 822 | if (ad_info->rm_irq != 0) {
|
|---|
| 823 | RMDeallocResource(rm_drvh, ad_info->rm_irq);
|
|---|
| 824 | }
|
|---|
| 825 | if (&ad_info->dma_buf_phys != 0) {
|
|---|
| 826 | DevHelp_FreePhys(ad_info->dma_buf_phys);
|
|---|
| 827 | }
|
|---|
| 828 | for (i = 0; i < sizeof(gdt) / sizeof(*gdt); i++) {
|
|---|
| 829 | if (gdt[i] != 0) {
|
|---|
| 830 | DevHelp_FreeGDTSelector(gdt[i]);
|
|---|
| 831 | }
|
|---|
| 832 | }
|
|---|
| 833 | }
|
|---|
| 834 |
|
|---|
| 835 | /******************************************************************************
|
|---|
| 836 | * Read PCI configuration space register
|
|---|
| 837 | */
|
|---|
| 838 | static UCHAR pci_read_conf(UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
|
|---|
| 839 | ULONG _far *val)
|
|---|
| 840 | {
|
|---|
| 841 | OH_PARM parm;
|
|---|
| 842 | OH_DATA data;
|
|---|
| 843 | UCHAR rc;
|
|---|
| 844 |
|
|---|
| 845 | memset(&parm, 0x00, sizeof(parm));
|
|---|
| 846 | parm.read_config.bus = bus;
|
|---|
| 847 | parm.read_config.dev_func = dev_func;
|
|---|
| 848 | parm.read_config.reg = indx;
|
|---|
| 849 | parm.read_config.size = size;
|
|---|
| 850 | if ((rc = oemhlp_call(OH_READ_CONFIG, &parm, &data) != OH_SUCCESS)) {
|
|---|
| 851 | cprintf("error: couldn't read config space (bus = %d, dev_func = 0x%02x, indx = 0x%02x, rc = %d)\n",
|
|---|
| 852 | bus, dev_func, indx, rc);
|
|---|
| 853 | return(rc);
|
|---|
| 854 | }
|
|---|
| 855 |
|
|---|
| 856 | *val = data.read_config.data;
|
|---|
| 857 | return(OH_SUCCESS);
|
|---|
| 858 | }
|
|---|
| 859 |
|
|---|
| 860 | /******************************************************************************
|
|---|
| 861 | * Write PCI configuration space register
|
|---|
| 862 | */
|
|---|
| 863 | static UCHAR pci_write_conf(UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
|
|---|
| 864 | ULONG val)
|
|---|
| 865 | {
|
|---|
| 866 | OH_PARM parm;
|
|---|
| 867 | OH_DATA data;
|
|---|
| 868 | UCHAR rc;
|
|---|
| 869 |
|
|---|
| 870 | memset(&parm, 0x00, sizeof(parm));
|
|---|
| 871 | parm.write_config.bus = bus;
|
|---|
| 872 | parm.write_config.dev_func = dev_func;
|
|---|
| 873 | parm.write_config.reg = indx;
|
|---|
| 874 | parm.write_config.size = size;
|
|---|
| 875 | parm.write_config.data = val;
|
|---|
| 876 |
|
|---|
| 877 | if ((rc = oemhlp_call(OH_WRITE_CONFIG, &parm, &data) != OH_SUCCESS)) {
|
|---|
| 878 | cprintf("error: couldn't write config space (bus = %d, dev_func = 0x%02x, indx = 0x%02x, rc = %d)\n",
|
|---|
| 879 | bus, dev_func, indx, rc);
|
|---|
| 880 | return(rc);
|
|---|
| 881 | }
|
|---|
| 882 |
|
|---|
| 883 | return(OH_SUCCESS);
|
|---|
| 884 | }
|
|---|
| 885 | /******************************************************************************
|
|---|
| 886 | * Call OEMHLP$ IDC entry point with the specified IOCtl parameter and data
|
|---|
| 887 | * packets.
|
|---|
| 888 | */
|
|---|
| 889 | static int oemhlp_call(UCHAR subfunction, OH_PARM _far *parm,
|
|---|
| 890 | OH_DATA _far *data)
|
|---|
| 891 | {
|
|---|
| 892 | void (_far *func)(void);
|
|---|
| 893 | RP_GENIOCTL ioctl;
|
|---|
| 894 | unsigned short prot_idc_ds;
|
|---|
| 895 |
|
|---|
| 896 | if (oemhlp.ProtIDCEntry == NULL || oemhlp.ProtIDC_DS == 0) {
|
|---|
| 897 | /* attach to OEMHLP$ device driver */
|
|---|
| 898 | if (DevHelp_AttachDD("OEMHLP$ ", (NPBYTE) &oemhlp) ||
|
|---|
| 899 | oemhlp.ProtIDCEntry == NULL ||
|
|---|
| 900 | oemhlp.ProtIDC_DS == 0) {
|
|---|
| 901 | cprintf("couldn't attach to OEMHLP$\n");
|
|---|
| 902 | return(OH_NOT_SUPPORTED);
|
|---|
| 903 | }
|
|---|
| 904 | }
|
|---|
| 905 |
|
|---|
| 906 | /* store subfuntion in first byte of pararameter packet */
|
|---|
| 907 | parm->bios_info.subfunction = subfunction;
|
|---|
| 908 | memset(data, 0x00, sizeof(*data));
|
|---|
| 909 |
|
|---|
| 910 | /* assemble IOCtl request */
|
|---|
| 911 | memset(&ioctl, 0x00, sizeof(ioctl));
|
|---|
| 912 | ioctl.rph.Len = sizeof(ioctl);
|
|---|
| 913 | ioctl.rph.Unit = 0;
|
|---|
| 914 | ioctl.rph.Cmd = GENERIC_IOCTL;
|
|---|
| 915 | ioctl.rph.Status = 0;
|
|---|
| 916 |
|
|---|
| 917 | ioctl.Category = OH_CATEGORY;
|
|---|
| 918 | ioctl.Function = OH_FUNC_PCI;
|
|---|
| 919 | ioctl.ParmPacket = (PUCHAR) parm;
|
|---|
| 920 | ioctl.DataPacket = (PUCHAR) data;
|
|---|
| 921 | ioctl.ParmLen = sizeof(*parm);
|
|---|
| 922 | ioctl.DataLen = sizeof(*data);
|
|---|
| 923 |
|
|---|
| 924 | /* Call OEMHLP's IDC routine. Before doing so, we need to assign the address
|
|---|
| 925 | * to be called to a stack variable because the inter-device driver calling
|
|---|
| 926 | * convention forces us to set DS to the device driver's data segment and ES
|
|---|
| 927 | * to the segment of the request packet.
|
|---|
| 928 | */
|
|---|
| 929 | func = oemhlp.ProtIDCEntry;
|
|---|
| 930 |
|
|---|
| 931 | /* The WATCOM compiler does not support struct references in inline
|
|---|
| 932 | * assembler code, so we pass it in a stack variable
|
|---|
| 933 | */
|
|---|
| 934 | prot_idc_ds = oemhlp.ProtIDC_DS;
|
|---|
| 935 |
|
|---|
| 936 | _asm {
|
|---|
| 937 | push ds;
|
|---|
| 938 | push es;
|
|---|
| 939 | push bx;
|
|---|
| 940 | push si;
|
|---|
| 941 | push di;
|
|---|
| 942 |
|
|---|
| 943 | push ss
|
|---|
| 944 | pop es
|
|---|
| 945 | lea bx, ioctl;
|
|---|
| 946 | mov ds, prot_idc_ds;
|
|---|
| 947 | call dword ptr [func];
|
|---|
| 948 |
|
|---|
| 949 | pop di;
|
|---|
| 950 | pop si;
|
|---|
| 951 | pop bx;
|
|---|
| 952 | pop es;
|
|---|
| 953 | pop ds;
|
|---|
| 954 | }
|
|---|
| 955 |
|
|---|
| 956 | dddphex(parm, sizeof(*parm), "oemhlp_parm: ");
|
|---|
| 957 | dddphex(data, sizeof(*data), "oemhlp_data: ");
|
|---|
| 958 |
|
|---|
| 959 | if (ioctl.rph.Status & STERR) {
|
|---|
| 960 | return(OH_NOT_SUPPORTED);
|
|---|
| 961 | }
|
|---|
| 962 | return(data->bios_info.rc);
|
|---|
| 963 | }
|
|---|
| 964 |
|
|---|
| 965 | /******************************************************************************
|
|---|
| 966 | * return vendor name for PCI vendor ID
|
|---|
| 967 | */
|
|---|
| 968 | char *vendor_from_id(u16 id)
|
|---|
| 969 | {
|
|---|
| 970 |
|
|---|
| 971 | switch(id) {
|
|---|
| 972 |
|
|---|
| 973 | case PCI_VENDOR_ID_AL:
|
|---|
| 974 | return "Ali";
|
|---|
| 975 | case PCI_VENDOR_ID_AMD:
|
|---|
| 976 | case PCI_VENDOR_ID_ATI:
|
|---|
| 977 | return "AMD";
|
|---|
| 978 | case PCI_VENDOR_ID_AT:
|
|---|
| 979 | return "Allied Telesyn";
|
|---|
| 980 | case PCI_VENDOR_ID_ATT:
|
|---|
| 981 | return "ATT";
|
|---|
| 982 | case PCI_VENDOR_ID_CMD:
|
|---|
| 983 | return "CMD";
|
|---|
| 984 | case PCI_VENDOR_ID_CT:
|
|---|
| 985 | return "CT";
|
|---|
| 986 | case PCI_VENDOR_ID_INTEL:
|
|---|
| 987 | return "Intel";
|
|---|
| 988 | case PCI_VENDOR_ID_INITIO:
|
|---|
| 989 | return "Initio";
|
|---|
| 990 | case PCI_VENDOR_ID_JMICRON:
|
|---|
| 991 | return "JMicron";
|
|---|
| 992 | case PCI_VENDOR_ID_MARVELL:
|
|---|
| 993 | return "Marvell";
|
|---|
| 994 | case PCI_VENDOR_ID_NVIDIA:
|
|---|
| 995 | return "NVIDIA";
|
|---|
| 996 | case PCI_VENDOR_ID_PROMISE:
|
|---|
| 997 | return "PROMISE";
|
|---|
| 998 | case PCI_VENDOR_ID_SI:
|
|---|
| 999 | return "SiS";
|
|---|
| 1000 | case PCI_VENDOR_ID_VIA:
|
|---|
| 1001 | return "VIA";
|
|---|
| 1002 | default:
|
|---|
| 1003 | break;
|
|---|
| 1004 | }
|
|---|
| 1005 |
|
|---|
| 1006 | return "Generic";
|
|---|
| 1007 |
|
|---|
| 1008 | }
|
|---|
| 1009 |
|
|---|
| 1010 | /******************************************************************************
|
|---|
| 1011 | * return a device name for a PCI device id
|
|---|
| 1012 | * NOTE: this is as simple as can be, so don't call it twice in one statement.
|
|---|
| 1013 | */
|
|---|
| 1014 | char *device_from_id(u16 device)
|
|---|
| 1015 | {
|
|---|
| 1016 | int i;
|
|---|
| 1017 |
|
|---|
| 1018 | for (i = 0; pci_ids[i].vendor != 0; i++) {
|
|---|
| 1019 |
|
|---|
| 1020 | if (pci_ids[i].device == device) {
|
|---|
| 1021 | return pci_ids[i].chipname;
|
|---|
| 1022 | }
|
|---|
| 1023 |
|
|---|
| 1024 | }
|
|---|
| 1025 |
|
|---|
| 1026 | return s_generic;
|
|---|
| 1027 | }
|
|---|
