source: trunk/src/os2ahci/pci.c@ 205

Last change on this file since 205 was 205, checked in by David Azarewicz, 5 years ago

Fixed ADD RM id.
File size: 33.6 KB
Line 
1/**
2 * PCI.c - PCI constants and detection code for os2ahci driver
3 *
4 * Copyright (c) 2011 thi.guten Software Development
5 * Copyright (c) 2011 Mensys B.V.
6 * Copyright (c) 2013-2021 David Azarewicz <david@88watts.net>
7 *
8 * Authors: Christian Mueller, Markus Thielen
9 *
10 * Parts copied from/inspired by the Linux AHCI driver;
11 * those parts are (c) Linux AHCI/ATA maintainers
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 */
27
28#include "os2ahci.h"
29
30/* offset of PCI base address register (BAR) in the PCI config space */
31#define PCI_BAR(reg) (UCHAR) (0x10 + (reg) * sizeof(u32))
32
33static void add_pci_device(PCI_ID *pci_id, USHORT BusDevFunc);
34static long bar_resource(USHORT BusDevFunc, RESOURCESTRUCT *resource, int i);
35static char *rmerr(APIRET ret);
36
37/******************************************************************************
38 * chipset/controller name strings
39 */
40static char chip_esb2[] = "ESB2";
41static char chip_ich8[] = "ICH8";
42static char chip_ich8m[] = "ICH8M";
43static char chip_ich9[] = "ICH9";
44static char chip_ich9m[] = "ICH9M";
45static char chip_ich10[] = "ICH10";
46static char chip_pchahci[] = "PCH AHCI";
47static char chip_pchraid[] = "PCH RAID";
48static char chip_tolapai[] = "Tolapai";
49static char chip_sb600[] = "SB600";
50static char chip_sb700[] = "SB700/800";
51static char chip_vt8251[] = "VT8251";
52static char chip_mcp65[] = "MCP65";
53static char chip_mcp67[] = "MCP67";
54static char chip_mcp73[] = "MCP73";
55static char chip_mcp77[] = "MCP77";
56static char chip_mcp79[] = "MCP79";
57static char chip_mcp89[] = "MCP689";
58static char chip_sis968[] = "968";
59
60static char s_generic[] = "Generic";
61
62
63/******************************************************************************
64 * PCI vendor and device IDs for known AHCI adapters. Copied from the Linux
65 * AHCI driver.
66 */
67
68PCI_ID pci_ids[] =
69{
70 /* Intel
71 * NOTE: ICH5 controller does NOT support AHCI, so we do
72 * not add it here! */
73 { PCI_VDEVICE(INTEL, 0x2652), board_ahci, "ICH6" }, /* ICH6 */
74 { PCI_VDEVICE(INTEL, 0x2653), board_ahci, "ICH6M" }, /* ICH6M */
75 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci, "ICH7" }, /* ICH7 */
76 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci, "ICH7M" }, /* ICH7M */
77 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci, "ICH7R" }, /* ICH7R */
78 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr, "ULiM5288" }, /* ULi M5288 */
79 { PCI_VDEVICE(INTEL, 0x2681), board_ahci, chip_esb2 }, /* ESB2 */
80 { PCI_VDEVICE(INTEL, 0x2682), board_ahci, chip_esb2 }, /* ESB2 */
81 { PCI_VDEVICE(INTEL, 0x2683), board_ahci, chip_esb2 }, /* ESB2 */
82 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci, "ICH7MDH" }, /* ICH7-M DH */
83 { PCI_VDEVICE(INTEL, 0x2821), board_ahci, chip_ich8 }, /* ICH8 */
84 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf, chip_ich8 }, /* ICH8 */
85 { PCI_VDEVICE(INTEL, 0x2824), board_ahci, chip_ich8 }, /* ICH8 */
86 { PCI_VDEVICE(INTEL, 0x2829), board_ahci, chip_ich8m }, /* ICH8M */
87 { PCI_VDEVICE(INTEL, 0x282a), board_ahci, chip_ich8m }, /* ICH8M */
88 { PCI_VDEVICE(INTEL, 0x2922), board_ahci, chip_ich9 }, /* ICH9 */
89 { PCI_VDEVICE(INTEL, 0x2923), board_ahci, chip_ich9 }, /* ICH9 */
90 { PCI_VDEVICE(INTEL, 0x2924), board_ahci, chip_ich9 }, /* ICH9 */
91 { PCI_VDEVICE(INTEL, 0x2925), board_ahci, chip_ich9 }, /* ICH9 */
92 { PCI_VDEVICE(INTEL, 0x2927), board_ahci, chip_ich9 }, /* ICH9 */
93 { PCI_VDEVICE(INTEL, 0x2929), board_ahci, chip_ich9m }, /* ICH9M */
94 { PCI_VDEVICE(INTEL, 0x292a), board_ahci, chip_ich9m }, /* ICH9M */
95 { PCI_VDEVICE(INTEL, 0x292b), board_ahci, chip_ich9m }, /* ICH9M */
96 { PCI_VDEVICE(INTEL, 0x292c), board_ahci, chip_ich9m }, /* ICH9M */
97 { PCI_VDEVICE(INTEL, 0x292f), board_ahci, chip_ich9m }, /* ICH9M */
98 { PCI_VDEVICE(INTEL, 0x294d), board_ahci, chip_ich9 }, /* ICH9 */
99 { PCI_VDEVICE(INTEL, 0x294e), board_ahci, chip_ich9m }, /* ICH9M */
100 { PCI_VDEVICE(INTEL, 0x502a), board_ahci, chip_tolapai }, /* Tolapai */
101 { PCI_VDEVICE(INTEL, 0x502b), board_ahci, chip_tolapai }, /* Tolapai */
102 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci, chip_ich10 }, /* ICH10 */
103 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci, chip_ich10 }, /* ICH10 */
104 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci, chip_ich10 }, /* ICH10 */
105 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci, chip_pchahci }, /* PCH AHCI */
106 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci, chip_pchahci }, /* PCH AHCI */
107 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci, chip_pchraid }, /* PCH RAID */
108 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci, chip_pchraid }, /* PCH RAID */
109 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci, chip_pchahci }, /* PCH AHCI */
110 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci, chip_pchraid }, /* PCH RAID */
111 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci, chip_pchraid }, /* PCH RAID */
112 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci, chip_pchahci }, /* PCH AHCI */
113
114 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
115 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
116 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffffL, board_ahci_ign_iferr, "360" },
117
118 /* ATI */
119 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600, chip_sb600 }, /* ATI SB600 */
120 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
121 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
122 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
123 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
124 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
125 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
126
127 /* AMD */
128 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
129 /* AMD is using RAID class only for ahci controllers */
130 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
131 PCI_CLASS_STORAGE_RAID << 8, 0xffffffL, board_ahci, "Hudson2" },
132
133 /* VIA */
134 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251, chip_vt8251 }, /* VIA VT8251 */
135 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251, chip_vt8251 }, /* VIA VT8251 */
136
137 /* NVIDIA */
138 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
139 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
140 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
141 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
142 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
143 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
144 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
145 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
146 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
147 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
148 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
149 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
150 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
151 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
152 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
153 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
154 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
155 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
156 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
157 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
158 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq, chip_mcp67 }, /* Linux ID */
159 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
160 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
161 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
162 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
163 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
164 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
165 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
166 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
167 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
168 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
169 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
170 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
171 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci, chip_mcp77 }, /* MCP77 */
172 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci, chip_mcp77 }, /* MCP77 */
173 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci, chip_mcp77 }, /* MCP77 */
174 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci, chip_mcp77 }, /* MCP77 */
175 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci, chip_mcp77 }, /* MCP77 */
176 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci, chip_mcp77 }, /* MCP77 */
177 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci, chip_mcp77 }, /* MCP77 */
178 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci, chip_mcp77 }, /* MCP77 */
179 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci, chip_mcp77 }, /* MCP77 */
180 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci, chip_mcp77 }, /* MCP77 */
181 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci, chip_mcp77 }, /* MCP77 */
182 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci, chip_mcp77 }, /* MCP77 */
183 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci, chip_mcp79 }, /* MCP79 */
184 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci, chip_mcp79 }, /* MCP79 */
185 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci, chip_mcp79 }, /* MCP79 */
186 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci, chip_mcp79 }, /* MCP79 */
187 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci, chip_mcp79 }, /* MCP79 */
188 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci, chip_mcp79 }, /* MCP79 */
189 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci, chip_mcp79 }, /* MCP79 */
190 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci, chip_mcp79 }, /* MCP79 */
191 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci, chip_mcp79 }, /* MCP79 */
192 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci, chip_mcp79 }, /* MCP79 */
193 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci, chip_mcp79 }, /* MCP79 */
194 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci, chip_mcp79 }, /* MCP79 */
195 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci, chip_mcp89 }, /* MCP89 */
196 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci, chip_mcp89 }, /* MCP89 */
197 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci, chip_mcp89 }, /* MCP89 */
198 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci, chip_mcp89 }, /* MCP89 */
199 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci, chip_mcp89 }, /* MCP89 */
200 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci, chip_mcp89 }, /* MCP89 */
201 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci, chip_mcp89 }, /* MCP89 */
202 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci, chip_mcp89 }, /* MCP89 */
203 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci, chip_mcp89 }, /* MCP89 */
204 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci, chip_mcp89 }, /* MCP89 */
205 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci, chip_mcp89 }, /* MCP89 */
206 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci, chip_mcp89 }, /* MCP89 */
207
208 /* SiS */
209 { PCI_VDEVICE(SI, 0x1184), board_ahci, "966" }, /* SiS 966 */
210 { PCI_VDEVICE(SI, 0x1185), board_ahci, chip_sis968 }, /* SiS 968 */
211 { PCI_VDEVICE(SI, 0x0186), board_ahci, chip_sis968 }, /* SiS 968 */
212
213 /* Marvell */
214 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv, "6145" }, /* 6145 */
215 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv, "6121" }, /* 6121 */
216
217 /* Promise */
218 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci, "PDC42819" }, /* PDC42819 */
219
220 /* Generic, PCI class code for AHCI */
221 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
222 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffffL, board_ahci, s_generic },
223
224 /* end of list, including a few slots to define custom adapters (10) */
225 { 0, 0, 0, 0, 0, 0, 0, NULL },
226 { 0, 0, 0, 0, 0, 0, 0, NULL },
227 { 0, 0, 0, 0, 0, 0, 0, NULL },
228 { 0, 0, 0, 0, 0, 0, 0, NULL },
229 { 0, 0, 0, 0, 0, 0, 0, NULL },
230 { 0, 0, 0, 0, 0, 0, 0, NULL },
231 { 0, 0, 0, 0, 0, 0, 0, NULL },
232 { 0, 0, 0, 0, 0, 0, 0, NULL },
233 { 0, 0, 0, 0, 0, 0, 0, NULL },
234 { 0, 0, 0, 0, 0, 0, 0, NULL },
235
236 { 0, 0, 0, 0, 0, 0, 0, NULL }
237};
238
239/******************************************************************************
240 * Add specified PCI vendor and device ID to the list of supported AHCI
241 * controllers. Please note that the last slot in pci_ids needs to remain
242 * empty because it's used as end marker.
243 */
244int add_pci_id(u16 vendor, u16 device)
245{
246 int max_slot = sizeof(pci_ids) / sizeof(*pci_ids) - 2;
247 int i;
248
249 /* search for last used slot in 'pci_ids' */
250 for (i = max_slot; i >= 0 && pci_ids[i].vendor == 0; i--);
251 if (i >= max_slot) return(-1); /* all slots in use */
252
253 /* use slot after the last used slot */
254 i++;
255 pci_ids[i].vendor = vendor;
256 pci_ids[i].device = device;
257 pci_ids[i].board = board_ahci;
258 pci_ids[i].chipname = s_generic;
259 return(0);
260}
261
262/******************************************************************************
263 * Scan PCI bus using OEMHLP$ IOCTLs and build adapter list.
264 */
265void scan_pci_bus(void)
266{
267 UCHAR index;
268 int ad_indx = 0;
269 int i;
270 int n;
271 USHORT BusDevFunc;
272
273 DPRINTF(3,"scanning PCI bus...\n");
274
275 /* Go through the list of PCI IDs and search for each device
276 *
277 * NOTES:
278 *
279 * - When searching via class code, the OEMHLP$ interface doesn't allow
280 * setting a bitmask to look for individual portions of class code,
281 * subclass code and programming interface. However, all bitmasks in the
282 * PCI list currently use 0xffffff, thus this should not be a problem at
283 * this point in time.
284 *
285 * - Scanning via OEMHLP$ seems rather slow, at least in the virtual
286 * machine I'm currenly using to test this driver. Thus, class code
287 * scans are preferred unless the option "-t" (thorough_scan) has been
288 * specified. The assumption is that most, if not all, modern AHCI
289 * adapters have the correct class code (PCI_CLASS_STORAGE_SATA_AHCI).
290 */
291 for (i = 0; pci_ids[i].vendor != 0; i++)
292 {
293 index = 0;
294 do
295 {
296 if (pci_ids[i].device == PCI_ANY_ID || pci_ids[i].vendor == PCI_ANY_ID)
297 {
298 /* look for class code */
299 BusDevFunc = PciFindClass(pci_ids[i].class, index);
300 }
301 else if (thorough_scan)
302 {
303 /* look for this specific vendor and device ID */
304 BusDevFunc = PciFindDevice( pci_ids[i].vendor, pci_ids[i].device, index);
305
306 }
307 else
308 {
309 BusDevFunc = 0xffff;
310 }
311
312 if (BusDevFunc != 0xffff)
313 {
314 /* found a device */
315 int already_found = 0;
316
317 /* increment index for next loop */
318 if (++index > 180) return; /* something's wrong here... */
319
320 /* check whether we already found this device */
321 for (n = 0; n < ad_info_cnt; n++)
322 {
323 if (ad_infos[n].bus_dev_func == BusDevFunc)
324 {
325 /* this device has already been found (e.g. via thorough scan) */
326 already_found = 1;
327 break;
328 }
329 }
330
331 if (already_found || (ad_ignore & (1U << ad_indx++)))
332 {
333 /* ignore this device; it has either already been found via a
334 * thorough scan or has been specified to be ignored via command
335 * line option */
336 continue;
337 }
338
339 /* add this PCI device to ad_infos[] */
340 add_pci_device(pci_ids + i, BusDevFunc);
341 }
342
343 } while (BusDevFunc != 0xffff);
344 }
345}
346
347/******************************************************************************
348 * Enable interrupt generation. PCI 2.3 added a bit which allows disabling
349 * interrupt generation for a device. This function clears the corresponding
350 * bit in the configuration space command register.
351 */
352int pci_enable_int(USHORT BusDevFunc)
353{
354 ULONG tmp;
355
356 if (PciReadConfig(BusDevFunc, 4, sizeof(tmp), &tmp) ||
357 PciWriteConfig(BusDevFunc, 4, sizeof(tmp), tmp & ~(1UL << 10)))
358 {
359 return(-1);
360 }
361 return(0);
362}
363
364/******************************************************************************
365 * Hack to set up proper IRQ mappings in the emulated PIIX3 ISA bridge in
366 * VirtualBox (for some reason, the first mapped IRQ is 0x80 without this
367 * hack).
368 */
369void pci_hack_virtualbox(void)
370{
371 UCHAR irq = 0;
372
373 if (!PciReadConfig(0x0008, 0x60, sizeof(irq), &irq) && irq == 0x80)
374 {
375 /* set IRQ for first device/func to 11 */
376 DPRINTF(1,"hacking virtualbox PIIX3 PCI to ISA bridge IRQ mapping\n");
377 irq = ad_infos[0].irq;
378 PciWriteConfig(0x0008, 0x60, sizeof(irq), irq);
379 }
380}
381
382/******************************************************************************
383 * Add a single PCI device to the list of adapters.
384 */
385static void add_pci_device(PCI_ID *pci_id, USHORT BusDevFunc)
386{
387 char rc_list_buf[sizeof(AHRESOURCE) + sizeof(HRESOURCE) * 15];
388 AHRESOURCE *rc_list = (AHRESOURCE *) rc_list_buf;
389 RESOURCESTRUCT resource;
390 ADAPTERSTRUCT adapter;
391 ADJUNCT adj;
392 AD_INFO *ad_info;
393 APIRET ret;
394 ULONG val;
395 char tmp[40];
396 u16 device;
397 u16 vendor;
398 u32 class;
399 int irq;
400 int pin;
401 int i;
402
403 /*****************************************************************************
404 * Part 1: Get further information about the device to be added; PCI ID...
405 */
406 if (PciReadConfig(BusDevFunc, 0x00, sizeof(ULONG), &val)) return;
407 device = (val >> 16);
408 vendor = (val & 0xffff);
409
410 /* ... and class code */
411 if (PciReadConfig(BusDevFunc, 0x08, sizeof(ULONG), &val)) return;
412 class = (val >> 8);
413
414 if (pci_id->device == PCI_ANY_ID)
415 {
416 /* We found this device in a wildcard search. There are two possible
417 * reasons which require a different handling:
418 *
419 * 1) This device uses a non-standard PCI class and has been identified
420 * with the corresponding class in pci_ids[] (e.g. the entry
421 * PCI_VENDOR_ID_JMICRON), but there is a vendor ID in pci_ids[]. In
422 * this case, we need to verify that the vendor is correct (see
423 * comments regarding OEMHLP limitations in 'scan_pci_bus()')
424 *
425 * 2) This device was identified using a generic PCI class for AHCI
426 * adapters such as PCI_CLASS_STORAGE_SATA_AHCI and we need to map
427 * the device and vendor ID to the corresponding index in pci_ids[]
428 * if there is such an entry; the index passed to this function will
429 * be the generic class-based index which is fine as long as there's
430 * not special treatment required as indicated by the board_*
431 * constants in pci_ids[]...
432 *
433 * The main reason for this kludge is that it seems as if OEMHLP$
434 * is rather slow searching for PCI devices, adding around 30s
435 * to the boot time when scanning for individual AHCI PCI IDs. Thus,
436 * the OS2AHCI driver avoids this kind of scan in favor of a class-
437 * based scan (unless overridden with the "/T" option).
438 */
439 if (pci_id->vendor != PCI_ANY_ID)
440 {
441 /* case 1: the vendor is known but we found the PCI device using a class
442 * search; verify vendor matches the one in pci_ids[]
443 */
444 if (pci_id->vendor != vendor) return; /* vendor doesn't match */
445 }
446 else
447 {
448 /* case 2: we found this device using a generic class search; if the
449 * device/vendor is listed in pci_ids[], use this entry in favor of the
450 * one passed in 'pci_id'
451 */
452 for (i = 0; pci_ids[i].vendor != 0; i++)
453 {
454 if (pci_ids[i].device == device && pci_ids[i].vendor == vendor)
455 {
456 pci_id = pci_ids + i;
457 break;
458 }
459 }
460 }
461 }
462
463 /* found a supported AHCI device */
464
465 if (PciReadConfig(BusDevFunc, 0x3c, sizeof(u32), &val)) return;
466 irq = (int) (val & 0xff);
467 pin = (int) ((val >> 8) & 0xff);
468
469 #if 0
470 i = 1;
471 if (irq==0 || irq==255) i = 0;
472
473 if (verbosity > i)
474 {
475 iprintf("%s AHCI device %s %s (%d:%d:%d %04x:%04x) class:0x%06x", i?"Found":"Ignoring",
476 vendor_from_id(vendor), device_from_id(device),
477 PCI_BUS_FROM_BDF(BusDevFunc), PCI_DEV_FROM_BDF(BusDevFunc), PCI_FUNC_FROM_BDF(BusDevFunc),
478 vendor, device, class);
479 if (i==0) iprintf("Invalid interrupt (IRQ=%d).", irq);
480 }
481 if (i==0) return;
482 #endif
483
484 /* make sure we got room in the adapter information array */
485 if (ad_info_cnt >= MAX_AD - 1)
486 {
487 iprintf("%s: too many AHCI devices", drv_name);
488 return;
489 }
490
491 /****************************************************************************
492 * Part 2: Determine resource requirements and allocate resources with the
493 * OS/2 resource manager. While doing so, some of the entries of the
494 * corresponding slot in the AD_INFO array, namely resource manager
495 * handles, are initialized so we need prepare the slot.
496 *
497 * NOTE: While registering resources with the resource manager, each new
498 * resource is added to the corresponding rc_list.hResource[] slot.
499 * rc_list is used further down to associate resources to adapters
500 * when the adapter itself is registered with the OS/2 resource
501 * manager.
502 */
503 ad_info = ad_infos + ad_info_cnt;
504 memset(ad_info, 0x00, sizeof(*ad_info));
505 rc_list->NumResource = 0;
506
507 /* Allocate all I/O and MMIO addresses offered by this device. In theory,
508 * we need only BAR #5, the AHCI MMIO BAR, but in order to prevent any
509 * other driver from hijacking our device and accessing it via legacy
510 * registers we'll reserve anything we can find.
511 */
512
513 ciprintf("Adapter %d PCI=%d:%d:%d ID=%04x:%04x\n", ad_info_cnt, PCI_BUS_FROM_BDF(BusDevFunc),
514 PCI_DEV_FROM_BDF(BusDevFunc), PCI_FUNC_FROM_BDF(BusDevFunc), vendor, device);
515 DPRINTF(1,"Adapter %d PCI=%d:%d:%d ID=%04x:%04x\n", ad_info_cnt, PCI_BUS_FROM_BDF(BusDevFunc),
516 PCI_DEV_FROM_BDF(BusDevFunc), PCI_FUNC_FROM_BDF(BusDevFunc), vendor, device);
517
518 for (i = 0; i < sizeof(ad_info->rm_bars) / sizeof(*ad_info->rm_bars); i++)
519 {
520 long len = bar_resource(BusDevFunc, &resource, i);
521
522 if (len < 0)
523 {
524 /* something went wrong */
525 goto add_pci_fail;
526 }
527 if (len == 0)
528 {
529 /* this BAR is unused */
530 continue;
531 }
532
533 if (i == AHCI_PCI_BAR)
534 {
535 if (resource.ResourceType != RS_TYPE_MEM)
536 {
537 iprintf("%s: BAR #5 must be an MMIO region", drv_name);
538 goto add_pci_fail;
539 }
540 /* save this BAR's address as MMIO address */
541 ad_info->mmio_phys = resource.MEMResource.MemBase;
542 ad_info->mmio_size = resource.MEMResource.MemSize;
543 }
544
545 /* register [MM]IO region with resource manager */
546 ret = RMAllocResource(rm_drvh, ad_info->rm_bars + i, &resource);
547 if (ret != RMRC_SUCCESS)
548 {
549 if (ret == RMRC_RES_ALREADY_CLAIMED)
550 {
551 ciiprintf("Device already claimed.");
552 }
553 else
554 {
555 iprintf("%s: couldn't register [MM]IO region (rc = %s)", drv_name, rmerr(ret));
556 }
557 goto add_pci_fail;
558 }
559 rc_list->hResource[rc_list->NumResource++] = ad_info->rm_bars[i];
560 }
561
562 if (ad_info->mmio_phys == 0)
563 {
564 iprintf("%s: couldn't determine MMIO base address", drv_name);
565 goto add_pci_fail;
566 }
567
568 /****************************************************************************
569 * Part 3: Fill in the remaining fields in the AD_INFO slot and allocate
570 * memory and GDT selectors for the adapter. Finally, register the adapter
571 * itself with the OS/2 resource manager
572 */
573 ad_info->pci = pci_id;
574 ad_info->pci_vendor = vendor;
575 ad_info->pci_device = device;
576 ad_info->bus_dev_func = BusDevFunc;
577 ad_info->irq = irq;
578 ad_info->irq_pin = pin;
579
580 ad_info->mmio = MapPhysToLin(ad_info->mmio_phys, ad_info->mmio_size);
581 if (!ad_info->mmio) goto add_pci_fail;
582
583 /* register adapter with resource manager */
584 memset(&adj, 0x00, sizeof(adj));
585 adj.pNextAdj = NULL;
586 adj.AdjLength = sizeof(adj);
587 adj.AdjType = ADJ_ADAPTER_NUMBER;
588 adj.Adapter_Number = ad_info_cnt;
589
590 memset(&adapter, 0x00, sizeof(adapter));
591 snprintf(tmp, sizeof(tmp), "AHCI_%d Controller", ad_info_cnt);
592 adapter.AdaptDescriptName = tmp;
593 adapter.AdaptFlags = 0;
594 adapter.BaseType = AS_BASE_MSD;
595 adapter.SubType = AS_SUB_IDE;
596 adapter.InterfaceType = AS_INTF_GENERIC;
597 adapter.HostBusType = AS_HOSTBUS_PCI;
598 adapter.HostBusWidth = AS_BUSWIDTH_32BIT;
599 adapter.pAdjunctList = &adj;
600
601 ret = RMCreateAdapter(rm_drvh, &ad_info->rm_adh, &adapter, NULL, rc_list);
602 if (ret != RMRC_SUCCESS)
603 {
604 iprintf("%s: couldn't register adapter (rc = %s)", drv_name, rmerr(ret));
605 goto add_pci_fail;
606 }
607
608 if (ahci_config_caps(ad_info)) goto add_pci_fail;
609
610 #ifndef DAZ_NEW_CODE
611 /* fill in DMA scratch buffer addresses in adapter info */
612 for (i = 0; i < AHCI_MAX_PORTS; i++)
613 {
614 if (!(ad_info->port_map & (1UL << i))) continue;
615
616 ad_info->ports[i].dma_buf = MemAllocAlign(AHCI_PORT_PRIV_DMA_SZ, 1024);
617 ad_info->ports[i].dma_buf_phys = MemPhysAdr(ad_info->ports[i].dma_buf);
618 }
619 #endif
620
621 /* Successfully added the adapter and reserved its resources; the adapter
622 * is still under BIOS control so we're not going to do anything else at
623 * this point.
624 */
625
626 ad_info_cnt++;
627 return;
628
629add_pci_fail:
630 /* something went wrong; try to clean up as far as possible */
631 for (i = 0; i < sizeof(ad_info->rm_bars) / sizeof(*ad_info->rm_bars); i++)
632 {
633 if (ad_info->rm_bars[i] != 0) RMDeallocResource(rm_drvh, ad_info->rm_bars[i]);
634 }
635}
636
637/******************************************************************************
638 * Prepare a resource structure for a PCI Base Address Register (BAR). This
639 * basically means the type, address and range of the I/O address space. It
640 * returns the length of the address range as a signed long to allow the caller
641 * to differentiate between error conditions (< 0), unused BARs (0) or valid
642 * bars (> 0).
643 *
644 * NOTE: In order to do this, we need to temporarily write 0xffffffff to
645 * the MMIO base address register (BAR), read back the resulting value
646 * and check the 0 bits from the right end, masking the lower 2 (I/O) or
647 * 4 (MMIO) bits. After doing this, we must restore the original value
648 * set up by the BIOS.
649 *
650 * 31 4 3 2 1 0
651 * -------------------------------------------------------------------
652 * base address P T T I
653 * P = prefetchable
654 * T = type (0 = any 32 bit, 1 = <1M, 2 = 64 bit)
655 * I = I/O (1) or memory (0)
656 */
657static long bar_resource(USHORT BusDevFunc, RESOURCESTRUCT *resource, int i)
658{
659 u32 bar_addr = 0;
660 u32 bar_size = 0;
661
662 /* temporarily write 1s to this BAR to determine the address range */
663 if (PciReadConfig (BusDevFunc, PCI_BAR(i), sizeof(u32), &bar_addr) ||
664 PciWriteConfig(BusDevFunc, PCI_BAR(i), sizeof(u32), ~(0UL)) ||
665 PciReadConfig (BusDevFunc, PCI_BAR(i), sizeof(u32), &bar_size) ||
666 PciWriteConfig(BusDevFunc, PCI_BAR(i), sizeof(u32), bar_addr) )
667 {
668 iprintf("%s: couldn't determine [MM]IO size", drv_name);
669 if (bar_addr != 0)
670 {
671 PciWriteConfig(BusDevFunc, PCI_BAR(i), sizeof(u32), bar_addr);
672 }
673 return(-1);
674 }
675
676 /* bar not implemented or device not working properly */
677 if (bar_size == 0 || bar_size == 0xffffffffUL) return(0);
678
679 /* prepare resource allocation structure */
680 memset(resource, 0x00, sizeof(*resource));
681 if (bar_addr & 1)
682 {
683 bar_size = ~(bar_size & 0xfffffffcUL) + 1;
684 bar_size &= 0xffffUL; /* I/O address space is 16 bits on x86 */
685 bar_addr &= 0xfffcUL;
686
687 resource->ResourceType = RS_TYPE_IO;
688 resource->IOResource.BaseIOPort = bar_addr;
689 resource->IOResource.NumIOPorts = bar_size;
690 resource->IOResource.IOFlags = RS_IO_EXCLUSIVE;
691 resource->IOResource.IOAddressLines = 16;
692
693 }
694 else
695 {
696 bar_size = ~(bar_size & 0xfffffff0UL) + 1;
697 bar_addr &= 0xfffffff0UL;
698
699 resource->ResourceType = RS_TYPE_MEM;
700 resource->MEMResource.MemBase = bar_addr;
701 resource->MEMResource.MemSize = bar_size;
702 resource->MEMResource.MemFlags = RS_MEM_EXCLUSIVE;
703 }
704
705 DPRINTF(3,"BAR #%d: type = %s, addr = 0x%08lx, size = %d\n", i,
706 (resource->ResourceType == RS_TYPE_IO) ? "I/O" : "MEM",
707 bar_addr, bar_size);
708
709 return((long) bar_size);
710}
711
712/******************************************************************************
713 * return vendor name for PCI vendor ID
714 */
715char *vendor_from_id(u16 id)
716{
717
718 switch(id)
719 {
720 case PCI_VENDOR_ID_AL:
721 return "Ali";
722 case PCI_VENDOR_ID_AMD:
723 case PCI_VENDOR_ID_ATI:
724 return "AMD";
725 case PCI_VENDOR_ID_AT:
726 return "Allied Telesyn";
727 case PCI_VENDOR_ID_ATT:
728 return "ATT";
729 case PCI_VENDOR_ID_CMD:
730 return "CMD";
731 case PCI_VENDOR_ID_CT:
732 return "CT";
733 case PCI_VENDOR_ID_INTEL:
734 return "Intel";
735 case PCI_VENDOR_ID_INITIO:
736 return "Initio";
737 case PCI_VENDOR_ID_JMICRON:
738 return "JMicron";
739 case PCI_VENDOR_ID_MARVELL:
740 return "Marvell";
741 case PCI_VENDOR_ID_NVIDIA:
742 return "NVIDIA";
743 case PCI_VENDOR_ID_PROMISE:
744 return "PROMISE";
745 case PCI_VENDOR_ID_SI:
746 return "SiS";
747 case PCI_VENDOR_ID_VIA:
748 return "VIA";
749 default:
750 break;
751 }
752
753 return "Generic";
754}
755
756/******************************************************************************
757 * return a device name for a PCI device id
758 * NOTE: this is as simple as can be, so don't call it twice in one statement.
759 */
760char *device_from_id(u16 device)
761{
762 int i;
763
764 for (i = 0; pci_ids[i].vendor != 0; i++)
765 {
766 if (pci_ids[i].device == device)
767 {
768 return pci_ids[i].chipname;
769 }
770 }
771
772 return s_generic;
773}
774
775/******************************************************************************
776 * Return textual version of a resource manager error
777 */
778static char *rmerr(APIRET ret)
779{
780 switch (ret) {
781 case RMRC_SUCCESS:
782 return("RMRC_SUCCESS");
783 case RMRC_NOTINITIALIZED:
784 return("RMRC_NOTINITIALIZED");
785 case RMRC_BAD_DRIVERHANDLE:
786 return("RMRC_BAD_DRIVERHANDLE");
787 case RMRC_BAD_ADAPTERHANDLE:
788 return("RMRC_BAD_ADAPTERHANDLE");
789 case RMRC_BAD_DEVICEHANDLE:
790 return("RMRC_BAD_DEVICEHANDLE");
791 case RMRC_BAD_RESOURCEHANDLE:
792 return("RMRC_BAD_RESOURCEHANDLE");
793 case RMRC_BAD_LDEVHANDLE:
794 return("RMRC_BAD_LDEVHANDLE");
795 case RMRC_BAD_SYSNAMEHANDLE:
796 return("RMRC_BAD_SYSNAMEHANDLE");
797 case RMRC_BAD_DEVHELP:
798 return("RMRC_BAD_DEVHELP");
799 case RMRC_NULL_POINTER:
800 return("RMRC_NULL_POINTER");
801 case RMRC_NULL_STRINGS:
802 return("RMRC_NULL_STRINGS");
803 case RMRC_BAD_VERSION:
804 return("RMRC_BAD_VERSION");
805 case RMRC_RES_ALREADY_CLAIMED:
806 return("RMRC_RES_ALREADY_CLAIMED");
807 case RMRC_DEV_ALREADY_CLAIMED:
808 return("RMRC_DEV_ALREADY_CLAIMED");
809 case RMRC_INVALID_PARM_VALUE:
810 return("RMRC_INVALID_PARM_VALUE");
811 case RMRC_OUT_OF_MEMORY:
812 return("RMRC_OUT_OF_MEMORY");
813 case RMRC_SEARCH_FAILED:
814 return("RMRC_SEARCH_FAILED");
815 case RMRC_BUFFER_TOO_SMALL:
816 return("RMRC_BUFFER_TOO_SMALL");
817 case RMRC_GENERAL_FAILURE:
818 return("RMRC_GENERAL_FAILURE");
819 case RMRC_IRQ_ENTRY_ILLEGAL:
820 return("RMRC_IRQ_ENTRY_ILLEGAL");
821 case RMRC_NOT_IMPLEMENTED:
822 return("RMRC_NOT_IMPLEMENTED");
823 case RMRC_NOT_INSTALLED:
824 return("RMRC_NOT_INSTALLED");
825 case RMRC_BAD_DETECTHANDLE:
826 return("RMRC_BAD_DETECTHANDLE");
827 case RMRC_BAD_RMHANDLE:
828 return("RMRC_BAD_RMHANDLE");
829 case RMRC_BAD_FLAGS:
830 return("RMRC_BAD_FLAGS");
831 case RMRC_NO_DETECTED_DATA:
832 return("RMRC_NO_DETECTED_DATA");
833 default:
834 return("RMRC_UNKOWN");
835 }
836}
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