source: trunk/src/os2ahci/pci.c@ 194

Last change on this file since 194 was 190, checked in by David Azarewicz, 8 years ago

Added MSI support.
File size: 34.0 KB
Line 
1/******************************************************************************
2 * PCI.c - PCI constants and detection code for os2ahci driver
3 *
4 * Copyright (c) 2011 thi.guten Software Development
5 * Copyright (c) 2011 Mensys B.V.
6 * Copyright (c) 2013-2016 David Azarewicz
7 *
8 * Authors: Christian Mueller, Markus Thielen
9 *
10 * Parts copied from/inspired by the Linux AHCI driver;
11 * those parts are (c) Linux AHCI/ATA maintainers
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 */
27
28#include "os2ahci.h"
29
30/* -------------------------- macros and constants ------------------------- */
31
32/* offset of PCI base address register (BAR) in the PCI config space */
33#define PCI_BAR(reg) (UCHAR) (0x10 + (reg) * sizeof(u32))
34
35/* ------------------------ typedefs and structures ------------------------ */
36
37/* -------------------------- function prototypes -------------------------- */
38
39static void add_pci_device(PCI_ID *pci_id, USHORT BusDevFunc);
40static long bar_resource(USHORT BusDevFunc, RESOURCESTRUCT *resource, int i);
41static char *rmerr(APIRET ret);
42
43/* ------------------------ global/static variables ------------------------ */
44
45/******************************************************************************
46 * chipset/controller name strings
47 */
48static char chip_esb2[] = "ESB2";
49static char chip_ich8[] = "ICH8";
50static char chip_ich8m[] = "ICH8M";
51static char chip_ich9[] = "ICH9";
52static char chip_ich9m[] = "ICH9M";
53static char chip_ich10[] = "ICH10";
54static char chip_pchahci[] = "PCH AHCI";
55static char chip_pchraid[] = "PCH RAID";
56static char chip_tolapai[] = "Tolapai";
57static char chip_sb600[] = "SB600";
58static char chip_sb700[] = "SB700/800";
59static char chip_vt8251[] = "VT8251";
60static char chip_mcp65[] = "MCP65";
61static char chip_mcp67[] = "MCP67";
62static char chip_mcp73[] = "MCP73";
63static char chip_mcp77[] = "MCP77";
64static char chip_mcp79[] = "MCP79";
65static char chip_mcp89[] = "MCP689";
66static char chip_sis968[] = "968";
67
68static char s_generic[] = "Generic";
69
70
71/******************************************************************************
72 * PCI vendor and device IDs for known AHCI adapters. Copied from the Linux
73 * AHCI driver.
74 */
75
76PCI_ID pci_ids[] =
77{
78 /* Intel
79 * NOTE: ICH5 controller does NOT support AHCI, so we do
80 * not add it here! */
81 { PCI_VDEVICE(INTEL, 0x2652), board_ahci, "ICH6" }, /* ICH6 */
82 { PCI_VDEVICE(INTEL, 0x2653), board_ahci, "ICH6M" }, /* ICH6M */
83 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci, "ICH7" }, /* ICH7 */
84 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci, "ICH7M" }, /* ICH7M */
85 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci, "ICH7R" }, /* ICH7R */
86 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr, "ULiM5288" }, /* ULi M5288 */
87 { PCI_VDEVICE(INTEL, 0x2681), board_ahci, chip_esb2 }, /* ESB2 */
88 { PCI_VDEVICE(INTEL, 0x2682), board_ahci, chip_esb2 }, /* ESB2 */
89 { PCI_VDEVICE(INTEL, 0x2683), board_ahci, chip_esb2 }, /* ESB2 */
90 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci, "ICH7MDH" }, /* ICH7-M DH */
91 { PCI_VDEVICE(INTEL, 0x2821), board_ahci, chip_ich8 }, /* ICH8 */
92 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf, chip_ich8 }, /* ICH8 */
93 { PCI_VDEVICE(INTEL, 0x2824), board_ahci, chip_ich8 }, /* ICH8 */
94 { PCI_VDEVICE(INTEL, 0x2829), board_ahci, chip_ich8m }, /* ICH8M */
95 { PCI_VDEVICE(INTEL, 0x282a), board_ahci, chip_ich8m }, /* ICH8M */
96 { PCI_VDEVICE(INTEL, 0x2922), board_ahci, chip_ich9 }, /* ICH9 */
97 { PCI_VDEVICE(INTEL, 0x2923), board_ahci, chip_ich9 }, /* ICH9 */
98 { PCI_VDEVICE(INTEL, 0x2924), board_ahci, chip_ich9 }, /* ICH9 */
99 { PCI_VDEVICE(INTEL, 0x2925), board_ahci, chip_ich9 }, /* ICH9 */
100 { PCI_VDEVICE(INTEL, 0x2927), board_ahci, chip_ich9 }, /* ICH9 */
101 { PCI_VDEVICE(INTEL, 0x2929), board_ahci, chip_ich9m }, /* ICH9M */
102 { PCI_VDEVICE(INTEL, 0x292a), board_ahci, chip_ich9m }, /* ICH9M */
103 { PCI_VDEVICE(INTEL, 0x292b), board_ahci, chip_ich9m }, /* ICH9M */
104 { PCI_VDEVICE(INTEL, 0x292c), board_ahci, chip_ich9m }, /* ICH9M */
105 { PCI_VDEVICE(INTEL, 0x292f), board_ahci, chip_ich9m }, /* ICH9M */
106 { PCI_VDEVICE(INTEL, 0x294d), board_ahci, chip_ich9 }, /* ICH9 */
107 { PCI_VDEVICE(INTEL, 0x294e), board_ahci, chip_ich9m }, /* ICH9M */
108 { PCI_VDEVICE(INTEL, 0x502a), board_ahci, chip_tolapai }, /* Tolapai */
109 { PCI_VDEVICE(INTEL, 0x502b), board_ahci, chip_tolapai }, /* Tolapai */
110 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci, chip_ich10 }, /* ICH10 */
111 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci, chip_ich10 }, /* ICH10 */
112 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci, chip_ich10 }, /* ICH10 */
113 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci, chip_pchahci }, /* PCH AHCI */
114 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci, chip_pchahci }, /* PCH AHCI */
115 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci, chip_pchraid }, /* PCH RAID */
116 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci, chip_pchraid }, /* PCH RAID */
117 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci, chip_pchahci }, /* PCH AHCI */
118 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci, chip_pchraid }, /* PCH RAID */
119 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci, chip_pchraid }, /* PCH RAID */
120 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci, chip_pchahci }, /* PCH AHCI */
121
122 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
123 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
124 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffffL, board_ahci_ign_iferr, "360" },
125
126 /* ATI */
127 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600, chip_sb600 }, /* ATI SB600 */
128 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
129 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
130 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
131 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
132 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
133 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
134
135 /* AMD */
136 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
137 /* AMD is using RAID class only for ahci controllers */
138 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
139 PCI_CLASS_STORAGE_RAID << 8, 0xffffffL, board_ahci, "Hudson2" },
140
141 /* VIA */
142 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251, chip_vt8251 }, /* VIA VT8251 */
143 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251, chip_vt8251 }, /* VIA VT8251 */
144
145 /* NVIDIA */
146 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
147 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
148 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
149 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
150 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
151 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
152 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
153 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
154 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
155 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
156 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
157 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
158 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
159 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
160 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
161 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
162 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
163 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
164 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
165 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
166 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq, chip_mcp67 }, /* Linux ID */
167 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
168 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
169 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
170 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
171 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
172 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
173 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
174 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
175 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
176 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
177 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
178 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
179 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci, chip_mcp77 }, /* MCP77 */
180 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci, chip_mcp77 }, /* MCP77 */
181 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci, chip_mcp77 }, /* MCP77 */
182 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci, chip_mcp77 }, /* MCP77 */
183 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci, chip_mcp77 }, /* MCP77 */
184 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci, chip_mcp77 }, /* MCP77 */
185 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci, chip_mcp77 }, /* MCP77 */
186 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci, chip_mcp77 }, /* MCP77 */
187 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci, chip_mcp77 }, /* MCP77 */
188 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci, chip_mcp77 }, /* MCP77 */
189 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci, chip_mcp77 }, /* MCP77 */
190 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci, chip_mcp77 }, /* MCP77 */
191 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci, chip_mcp79 }, /* MCP79 */
192 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci, chip_mcp79 }, /* MCP79 */
193 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci, chip_mcp79 }, /* MCP79 */
194 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci, chip_mcp79 }, /* MCP79 */
195 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci, chip_mcp79 }, /* MCP79 */
196 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci, chip_mcp79 }, /* MCP79 */
197 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci, chip_mcp79 }, /* MCP79 */
198 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci, chip_mcp79 }, /* MCP79 */
199 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci, chip_mcp79 }, /* MCP79 */
200 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci, chip_mcp79 }, /* MCP79 */
201 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci, chip_mcp79 }, /* MCP79 */
202 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci, chip_mcp79 }, /* MCP79 */
203 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci, chip_mcp89 }, /* MCP89 */
204 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci, chip_mcp89 }, /* MCP89 */
205 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci, chip_mcp89 }, /* MCP89 */
206 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci, chip_mcp89 }, /* MCP89 */
207 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci, chip_mcp89 }, /* MCP89 */
208 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci, chip_mcp89 }, /* MCP89 */
209 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci, chip_mcp89 }, /* MCP89 */
210 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci, chip_mcp89 }, /* MCP89 */
211 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci, chip_mcp89 }, /* MCP89 */
212 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci, chip_mcp89 }, /* MCP89 */
213 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci, chip_mcp89 }, /* MCP89 */
214 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci, chip_mcp89 }, /* MCP89 */
215
216 /* SiS */
217 { PCI_VDEVICE(SI, 0x1184), board_ahci, "966" }, /* SiS 966 */
218 { PCI_VDEVICE(SI, 0x1185), board_ahci, chip_sis968 }, /* SiS 968 */
219 { PCI_VDEVICE(SI, 0x0186), board_ahci, chip_sis968 }, /* SiS 968 */
220
221 /* Marvell */
222 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv, "6145" }, /* 6145 */
223 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv, "6121" }, /* 6121 */
224
225 /* Promise */
226 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci, "PDC42819" }, /* PDC42819 */
227
228 /* Generic, PCI class code for AHCI */
229 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
230 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffffL, board_ahci, s_generic },
231
232 /* end of list, including a few slots to define custom adapters (10) */
233 { 0, 0, 0, 0, 0, 0, 0, NULL },
234 { 0, 0, 0, 0, 0, 0, 0, NULL },
235 { 0, 0, 0, 0, 0, 0, 0, NULL },
236 { 0, 0, 0, 0, 0, 0, 0, NULL },
237 { 0, 0, 0, 0, 0, 0, 0, NULL },
238 { 0, 0, 0, 0, 0, 0, 0, NULL },
239 { 0, 0, 0, 0, 0, 0, 0, NULL },
240 { 0, 0, 0, 0, 0, 0, 0, NULL },
241 { 0, 0, 0, 0, 0, 0, 0, NULL },
242 { 0, 0, 0, 0, 0, 0, 0, NULL },
243
244 { 0, 0, 0, 0, 0, 0, 0, NULL }
245};
246
247/* ----------------------------- start of code ----------------------------- */
248
249/******************************************************************************
250 * Add specified PCI vendor and device ID to the list of supported AHCI
251 * controllers. Please note that the last slot in pci_ids needs to remain
252 * empty because it's used as end marker.
253 */
254int add_pci_id(u16 vendor, u16 device)
255{
256 int max_slot = sizeof(pci_ids) / sizeof(*pci_ids) - 2;
257 int i;
258
259 /* search for last used slot in 'pci_ids' */
260 for (i = max_slot; i >= 0 && pci_ids[i].vendor == 0; i--);
261 if (i >= max_slot) return(-1); /* all slots in use */
262
263 /* use slot after the last used slot */
264 i++;
265 pci_ids[i].vendor = vendor;
266 pci_ids[i].device = device;
267 pci_ids[i].board = board_ahci;
268 pci_ids[i].chipname = s_generic;
269 return(0);
270}
271
272/******************************************************************************
273 * Scan PCI bus using OEMHLP$ IOCTLs and build adapter list.
274 */
275void scan_pci_bus(void)
276{
277 UCHAR index;
278 int ad_indx = 0;
279 int i;
280 int n;
281 USHORT BusDevFunc;
282
283 DPRINTF(3,"scanning PCI bus...\n");
284
285 /* Go through the list of PCI IDs and search for each device
286 *
287 * NOTES:
288 *
289 * - When searching via class code, the OEMHLP$ interface doesn't allow
290 * setting a bitmask to look for individual portions of class code,
291 * subclass code and programming interface. However, all bitmasks in the
292 * PCI list currently use 0xffffff, thus this should not be a problem at
293 * this point in time.
294 *
295 * - Scanning via OEMHLP$ seems rather slow, at least in the virtual
296 * machine I'm currenly using to test this driver. Thus, class code
297 * scans are preferred unless the option "-t" (thorough_scan) has been
298 * specified. The assumption is that most, if not all, modern AHCI
299 * adapters have the correct class code (PCI_CLASS_STORAGE_SATA_AHCI).
300 */
301 for (i = 0; pci_ids[i].vendor != 0; i++)
302 {
303 index = 0;
304 do
305 {
306 if (pci_ids[i].device == PCI_ANY_ID || pci_ids[i].vendor == PCI_ANY_ID)
307 {
308 /* look for class code */
309 BusDevFunc = PciFindClass(pci_ids[i].class, index);
310 }
311 else if (thorough_scan)
312 {
313 /* look for this specific vendor and device ID */
314 BusDevFunc = PciFindDevice( pci_ids[i].vendor, pci_ids[i].device, index);
315
316 }
317 else
318 {
319 BusDevFunc = 0xffff;
320 }
321
322 if (BusDevFunc != 0xffff)
323 {
324 /* found a device */
325 int already_found = 0;
326
327 /* increment index for next loop */
328 if (++index > 180) return; /* something's wrong here... */
329
330 /* check whether we already found this device */
331 for (n = 0; n < ad_info_cnt; n++)
332 {
333 if (ad_infos[n].bus_dev_func == BusDevFunc)
334 {
335 /* this device has already been found (e.g. via thorough scan) */
336 already_found = 1;
337 break;
338 }
339 }
340
341 if (already_found || (ad_ignore & (1U << ad_indx++)))
342 {
343 /* ignore this device; it has either already been found via a
344 * thorough scan or has been specified to be ignored via command
345 * line option */
346 continue;
347 }
348
349 /* add this PCI device to ad_infos[] */
350 add_pci_device(pci_ids + i, BusDevFunc);
351 }
352
353 } while (BusDevFunc != 0xffff);
354 }
355}
356
357/******************************************************************************
358 * Enable interrupt generation. PCI 2.3 added a bit which allows disabling
359 * interrupt generation for a device. This function clears the corresponding
360 * bit in the configuration space command register.
361 */
362int pci_enable_int(USHORT BusDevFunc)
363{
364 ULONG tmp;
365
366 if (PciReadConfig(BusDevFunc, 4, sizeof(tmp), &tmp) ||
367 PciWriteConfig(BusDevFunc, 4, sizeof(tmp), tmp & ~(1UL << 10)))
368 {
369 return(-1);
370 }
371 return(0);
372}
373
374/******************************************************************************
375 * Hack to set up proper IRQ mappings in the emulated PIIX3 ISA bridge in
376 * VirtualBox (for some reason, the first mapped IRQ is 0x80 without this
377 * hack).
378 */
379void pci_hack_virtualbox(void)
380{
381 UCHAR irq = 0;
382
383 if (!PciReadConfig(0x0008, 0x60, sizeof(irq), &irq) && irq == 0x80)
384 {
385 /* set IRQ for first device/func to 11 */
386 DPRINTF(1,"hacking virtualbox PIIX3 PCI to ISA bridge IRQ mapping\n");
387 irq = ad_infos[0].irq;
388 PciWriteConfig(0x0008, 0x60, sizeof(irq), irq);
389 }
390}
391
392/******************************************************************************
393 * Add a single PCI device to the list of adapters.
394 */
395static void add_pci_device(PCI_ID *pci_id, USHORT BusDevFunc)
396{
397 char rc_list_buf[sizeof(AHRESOURCE) + sizeof(HRESOURCE) * 15];
398 AHRESOURCE *rc_list = (AHRESOURCE *) rc_list_buf;
399 RESOURCESTRUCT resource;
400 ADAPTERSTRUCT adapter;
401 ADJUNCT adj;
402 AD_INFO *ad_info;
403 APIRET ret;
404 ULONG val;
405 char tmp[40];
406 u16 device;
407 u16 vendor;
408 u32 class;
409 int irq;
410 int pin;
411 int i;
412
413 /*****************************************************************************
414 * Part 1: Get further information about the device to be added; PCI ID...
415 */
416 if (PciReadConfig(BusDevFunc, 0x00, sizeof(ULONG), &val)) return;
417 device = (val >> 16);
418 vendor = (val & 0xffff);
419
420 /* ... and class code */
421 if (PciReadConfig(BusDevFunc, 0x08, sizeof(ULONG), &val)) return;
422 class = (val >> 8);
423
424 if (pci_id->device == PCI_ANY_ID)
425 {
426 /* We found this device in a wildcard search. There are two possible
427 * reasons which require a different handling:
428 *
429 * 1) This device uses a non-standard PCI class and has been identified
430 * with the corresponding class in pci_ids[] (e.g. the entry
431 * PCI_VENDOR_ID_JMICRON), but there is a vendor ID in pci_ids[]. In
432 * this case, we need to verify that the vendor is correct (see
433 * comments regarding OEMHLP limitations in 'scan_pci_bus()')
434 *
435 * 2) This device was identified using a generic PCI class for AHCI
436 * adapters such as PCI_CLASS_STORAGE_SATA_AHCI and we need to map
437 * the device and vendor ID to the corresponding index in pci_ids[]
438 * if there is such an entry; the index passed to this function will
439 * be the generic class-based index which is fine as long as there's
440 * not special treatment required as indicated by the board_*
441 * constants in pci_ids[]...
442 *
443 * The main reason for this kludge is that it seems as if OEMHLP$
444 * is rather slow searching for PCI devices, adding around 30s
445 * to the boot time when scanning for individual AHCI PCI IDs. Thus,
446 * the OS2AHCI driver avoids this kind of scan in favor of a class-
447 * based scan (unless overridden with the "/T" option).
448 */
449 if (pci_id->vendor != PCI_ANY_ID)
450 {
451 /* case 1: the vendor is known but we found the PCI device using a class
452 * search; verify vendor matches the one in pci_ids[]
453 */
454 if (pci_id->vendor != vendor) return; /* vendor doesn't match */
455 }
456 else
457 {
458 /* case 2: we found this device using a generic class search; if the
459 * device/vendor is listed in pci_ids[], use this entry in favor of the
460 * one passed in 'pci_id'
461 */
462 for (i = 0; pci_ids[i].vendor != 0; i++)
463 {
464 if (pci_ids[i].device == device && pci_ids[i].vendor == vendor)
465 {
466 pci_id = pci_ids + i;
467 break;
468 }
469 }
470 }
471 }
472
473 /* found a supported AHCI device */
474
475 if (PciReadConfig(BusDevFunc, 0x3c, sizeof(u32), &val)) return;
476 irq = (int) (val & 0xff);
477 pin = (int) ((val >> 8) & 0xff);
478
479 i = 1;
480 if (irq==0 || irq==255) i = 0;
481
482 if (verbosity > i)
483 {
484 iprintf("%s AHCI device %s %s (%d:%d:%d %04x:%04x) class:0x%06x", i?"Found":"Ignoring",
485 vendor_from_id(vendor), device_from_id(device),
486 PCI_BUS_FROM_BDF(BusDevFunc), PCI_DEV_FROM_BDF(BusDevFunc), PCI_FUNC_FROM_BDF(BusDevFunc),
487 vendor, device, class);
488 if (i==0) iprintf("Invalid interrupt (IRQ=%d).", irq);
489 }
490 if (i==0) return;
491
492 /* make sure we got room in the adapter information array */
493 if (ad_info_cnt >= MAX_AD - 1)
494 {
495 iprintf("%s: too many AHCI devices", drv_name);
496 return;
497 }
498
499 /****************************************************************************
500 * Part 2: Determine resource requirements and allocate resources with the
501 * OS/2 resource manager. While doing so, some of the entries of the
502 * corresponding slot in the AD_INFO array, namely resource manager
503 * handles, are initialized so we need prepare the slot.
504 *
505 * NOTE: While registering resources with the resource manager, each new
506 * resource is added to the corresponding rc_list.hResource[] slot.
507 * rc_list is used further down to associate resources to adapters
508 * when the adapter itself is registered with the OS/2 resource
509 * manager.
510 */
511 ad_info = ad_infos + ad_info_cnt;
512 memset(ad_info, 0x00, sizeof(*ad_info));
513 rc_list->NumResource = 0;
514
515 /* Allocate all I/O and MMIO addresses offered by this device. In theory,
516 * we need only BAR #5, the AHCI MMIO BAR, but in order to prevent any
517 * other driver from hijacking our device and accessing it via legacy
518 * registers we'll reserve anything we can find.
519 */
520
521 ciprintf("Adapter %d PCI=%d:%d:%d ID=%04x:%04x\n", ad_info_cnt, PCI_BUS_FROM_BDF(BusDevFunc),
522 PCI_DEV_FROM_BDF(BusDevFunc), PCI_FUNC_FROM_BDF(BusDevFunc), vendor, device);
523 DPRINTF(1,"Adapter %d PCI=%d:%d:%d ID=%04x:%04x\n", ad_info_cnt, PCI_BUS_FROM_BDF(BusDevFunc),
524 PCI_DEV_FROM_BDF(BusDevFunc), PCI_FUNC_FROM_BDF(BusDevFunc), vendor, device);
525
526 for (i = 0; i < sizeof(ad_info->rm_bars) / sizeof(*ad_info->rm_bars); i++)
527 {
528 long len = bar_resource(BusDevFunc, &resource, i);
529
530 if (len < 0)
531 {
532 /* something went wrong */
533 goto add_pci_fail;
534 }
535 if (len == 0)
536 {
537 /* this BAR is unused */
538 continue;
539 }
540
541 if (i == AHCI_PCI_BAR)
542 {
543 if (resource.ResourceType != RS_TYPE_MEM)
544 {
545 iprintf("%s: BAR #5 must be an MMIO region", drv_name);
546 goto add_pci_fail;
547 }
548 /* save this BAR's address as MMIO address */
549 ad_info->mmio_phys = resource.MEMResource.MemBase;
550 ad_info->mmio_size = resource.MEMResource.MemSize;
551 }
552
553 /* register [MM]IO region with resource manager */
554 ret = RMAllocResource(rm_drvh, ad_info->rm_bars + i, &resource);
555 if (ret != RMRC_SUCCESS)
556 {
557 if (ret == RMRC_RES_ALREADY_CLAIMED)
558 {
559 ciiprintf("Device already claimed.");
560 }
561 else
562 {
563 iprintf("%s: couldn't register [MM]IO region (rc = %s)", drv_name, rmerr(ret));
564 }
565 goto add_pci_fail;
566 }
567 rc_list->hResource[rc_list->NumResource++] = ad_info->rm_bars[i];
568 }
569
570 if (ad_info->mmio_phys == 0)
571 {
572 iprintf("%s: couldn't determine MMIO base address", drv_name);
573 goto add_pci_fail;
574 }
575
576 /****************************************************************************
577 * Part 3: Fill in the remaining fields in the AD_INFO slot and allocate
578 * memory and GDT selectors for the adapter. Finally, register the adapter
579 * itself with the OS/2 resource manager
580 */
581 ad_info->pci = pci_id;
582 ad_info->pci_vendor = vendor;
583 ad_info->pci_device = device;
584 ad_info->bus_dev_func = BusDevFunc;
585 ad_info->irq = irq;
586 ad_info->irq_pin = pin;
587
588 ad_info->mmio = MapPhysToLin(ad_info->mmio_phys, ad_info->mmio_size);
589 if (!ad_info->mmio) goto add_pci_fail;
590
591 /* register adapter with resource manager */
592 memset(&adj, 0x00, sizeof(adj));
593 adj.pNextAdj = NULL;
594 adj.AdjLength = sizeof(adj);
595 adj.AdjType = ADJ_ADAPTER_NUMBER;
596 adj.Adapter_Number = ad_info_cnt;
597
598 memset(&adapter, 0x00, sizeof(adapter));
599 snprintf(tmp, sizeof(tmp), "AHCI_%d Controller", ad_info_cnt);
600 adapter.AdaptDescriptName = tmp;
601 adapter.AdaptFlags = 0;
602 adapter.BaseType = AS_BASE_MSD;
603 adapter.SubType = AS_SUB_IDE;
604 adapter.InterfaceType = AS_INTF_GENERIC;
605 adapter.HostBusType = AS_HOSTBUS_PCI;
606 adapter.HostBusWidth = AS_BUSWIDTH_32BIT;
607 adapter.pAdjunctList = &adj;
608
609 ret = RMCreateAdapter(rm_drvh, &ad_info->rm_adh, &adapter, NULL, rc_list);
610 if (ret != RMRC_SUCCESS)
611 {
612 iprintf("%s: couldn't register adapter (rc = %s)", drv_name, rmerr(ret));
613 goto add_pci_fail;
614 }
615
616 if (ahci_config_caps(ad_info)) goto add_pci_fail;
617
618 #ifndef DAZ_NEW_CODE
619 /* fill in DMA scratch buffer addresses in adapter info */
620 for (i = 0; i < AHCI_MAX_PORTS; i++)
621 {
622 if (!(ad_info->port_map & (1UL << i))) continue;
623
624 ad_info->ports[i].dma_buf = MemAllocAlign(AHCI_PORT_PRIV_DMA_SZ, 1024);
625 ad_info->ports[i].dma_buf_phys = MemPhysAdr(ad_info->ports[i].dma_buf);
626 }
627 #endif
628
629 /* Successfully added the adapter and reserved its resources; the adapter
630 * is still under BIOS control so we're not going to do anything else at
631 * this point.
632 */
633
634 ad_info_cnt++;
635 return;
636
637add_pci_fail:
638 /* something went wrong; try to clean up as far as possible */
639 for (i = 0; i < sizeof(ad_info->rm_bars) / sizeof(*ad_info->rm_bars); i++)
640 {
641 if (ad_info->rm_bars[i] != 0) RMDeallocResource(rm_drvh, ad_info->rm_bars[i]);
642 }
643}
644
645/******************************************************************************
646 * Prepare a resource structure for a PCI Base Address Register (BAR). This
647 * basically means the type, address and range of the I/O address space. It
648 * returns the length of the address range as a signed long to allow the caller
649 * to differentiate between error conditions (< 0), unused BARs (0) or valid
650 * bars (> 0).
651 *
652 * NOTE: In order to do this, we need to temporarily write 0xffffffff to
653 * the MMIO base address register (BAR), read back the resulting value
654 * and check the 0 bits from the right end, masking the lower 2 (I/O) or
655 * 4 (MMIO) bits. After doing this, we must restore the original value
656 * set up by the BIOS.
657 *
658 * 31 4 3 2 1 0
659 * -------------------------------------------------------------------
660 * base address P T T I
661 * P = prefetchable
662 * T = type (0 = any 32 bit, 1 = <1M, 2 = 64 bit)
663 * I = I/O (1) or memory (0)
664 */
665static long bar_resource(USHORT BusDevFunc, RESOURCESTRUCT *resource, int i)
666{
667 u32 bar_addr = 0;
668 u32 bar_size = 0;
669
670 /* temporarily write 1s to this BAR to determine the address range */
671 if (PciReadConfig (BusDevFunc, PCI_BAR(i), sizeof(u32), &bar_addr) ||
672 PciWriteConfig(BusDevFunc, PCI_BAR(i), sizeof(u32), ~(0UL)) ||
673 PciReadConfig (BusDevFunc, PCI_BAR(i), sizeof(u32), &bar_size) ||
674 PciWriteConfig(BusDevFunc, PCI_BAR(i), sizeof(u32), bar_addr) )
675 {
676 iprintf("%s: couldn't determine [MM]IO size", drv_name);
677 if (bar_addr != 0)
678 {
679 PciWriteConfig(BusDevFunc, PCI_BAR(i), sizeof(u32), bar_addr);
680 }
681 return(-1);
682 }
683
684 /* bar not implemented or device not working properly */
685 if (bar_size == 0 || bar_size == 0xffffffffUL) return(0);
686
687 /* prepare resource allocation structure */
688 memset(resource, 0x00, sizeof(*resource));
689 if (bar_addr & 1)
690 {
691 bar_size = ~(bar_size & 0xfffffffcUL) + 1;
692 bar_size &= 0xffffUL; /* I/O address space is 16 bits on x86 */
693 bar_addr &= 0xfffcUL;
694
695 resource->ResourceType = RS_TYPE_IO;
696 resource->IOResource.BaseIOPort = bar_addr;
697 resource->IOResource.NumIOPorts = bar_size;
698 resource->IOResource.IOFlags = RS_IO_EXCLUSIVE;
699 resource->IOResource.IOAddressLines = 16;
700
701 }
702 else
703 {
704 bar_size = ~(bar_size & 0xfffffff0UL) + 1;
705 bar_addr &= 0xfffffff0UL;
706
707 resource->ResourceType = RS_TYPE_MEM;
708 resource->MEMResource.MemBase = bar_addr;
709 resource->MEMResource.MemSize = bar_size;
710 resource->MEMResource.MemFlags = RS_MEM_EXCLUSIVE;
711 }
712
713 DPRINTF(3,"BAR #%d: type = %s, addr = 0x%08lx, size = %d\n", i,
714 (resource->ResourceType == RS_TYPE_IO) ? "I/O" : "MEM",
715 bar_addr, bar_size);
716
717 return((long) bar_size);
718}
719
720/******************************************************************************
721 * return vendor name for PCI vendor ID
722 */
723char *vendor_from_id(u16 id)
724{
725
726 switch(id)
727 {
728 case PCI_VENDOR_ID_AL:
729 return "Ali";
730 case PCI_VENDOR_ID_AMD:
731 case PCI_VENDOR_ID_ATI:
732 return "AMD";
733 case PCI_VENDOR_ID_AT:
734 return "Allied Telesyn";
735 case PCI_VENDOR_ID_ATT:
736 return "ATT";
737 case PCI_VENDOR_ID_CMD:
738 return "CMD";
739 case PCI_VENDOR_ID_CT:
740 return "CT";
741 case PCI_VENDOR_ID_INTEL:
742 return "Intel";
743 case PCI_VENDOR_ID_INITIO:
744 return "Initio";
745 case PCI_VENDOR_ID_JMICRON:
746 return "JMicron";
747 case PCI_VENDOR_ID_MARVELL:
748 return "Marvell";
749 case PCI_VENDOR_ID_NVIDIA:
750 return "NVIDIA";
751 case PCI_VENDOR_ID_PROMISE:
752 return "PROMISE";
753 case PCI_VENDOR_ID_SI:
754 return "SiS";
755 case PCI_VENDOR_ID_VIA:
756 return "VIA";
757 default:
758 break;
759 }
760
761 return "Generic";
762}
763
764/******************************************************************************
765 * return a device name for a PCI device id
766 * NOTE: this is as simple as can be, so don't call it twice in one statement.
767 */
768char *device_from_id(u16 device)
769{
770 int i;
771
772 for (i = 0; pci_ids[i].vendor != 0; i++)
773 {
774 if (pci_ids[i].device == device)
775 {
776 return pci_ids[i].chipname;
777 }
778 }
779
780 return s_generic;
781}
782
783/******************************************************************************
784 * Return textual version of a resource manager error
785 */
786static char *rmerr(APIRET ret)
787{
788 switch (ret) {
789 case RMRC_SUCCESS:
790 return("RMRC_SUCCESS");
791 case RMRC_NOTINITIALIZED:
792 return("RMRC_NOTINITIALIZED");
793 case RMRC_BAD_DRIVERHANDLE:
794 return("RMRC_BAD_DRIVERHANDLE");
795 case RMRC_BAD_ADAPTERHANDLE:
796 return("RMRC_BAD_ADAPTERHANDLE");
797 case RMRC_BAD_DEVICEHANDLE:
798 return("RMRC_BAD_DEVICEHANDLE");
799 case RMRC_BAD_RESOURCEHANDLE:
800 return("RMRC_BAD_RESOURCEHANDLE");
801 case RMRC_BAD_LDEVHANDLE:
802 return("RMRC_BAD_LDEVHANDLE");
803 case RMRC_BAD_SYSNAMEHANDLE:
804 return("RMRC_BAD_SYSNAMEHANDLE");
805 case RMRC_BAD_DEVHELP:
806 return("RMRC_BAD_DEVHELP");
807 case RMRC_NULL_POINTER:
808 return("RMRC_NULL_POINTER");
809 case RMRC_NULL_STRINGS:
810 return("RMRC_NULL_STRINGS");
811 case RMRC_BAD_VERSION:
812 return("RMRC_BAD_VERSION");
813 case RMRC_RES_ALREADY_CLAIMED:
814 return("RMRC_RES_ALREADY_CLAIMED");
815 case RMRC_DEV_ALREADY_CLAIMED:
816 return("RMRC_DEV_ALREADY_CLAIMED");
817 case RMRC_INVALID_PARM_VALUE:
818 return("RMRC_INVALID_PARM_VALUE");
819 case RMRC_OUT_OF_MEMORY:
820 return("RMRC_OUT_OF_MEMORY");
821 case RMRC_SEARCH_FAILED:
822 return("RMRC_SEARCH_FAILED");
823 case RMRC_BUFFER_TOO_SMALL:
824 return("RMRC_BUFFER_TOO_SMALL");
825 case RMRC_GENERAL_FAILURE:
826 return("RMRC_GENERAL_FAILURE");
827 case RMRC_IRQ_ENTRY_ILLEGAL:
828 return("RMRC_IRQ_ENTRY_ILLEGAL");
829 case RMRC_NOT_IMPLEMENTED:
830 return("RMRC_NOT_IMPLEMENTED");
831 case RMRC_NOT_INSTALLED:
832 return("RMRC_NOT_INSTALLED");
833 case RMRC_BAD_DETECTHANDLE:
834 return("RMRC_BAD_DETECTHANDLE");
835 case RMRC_BAD_RMHANDLE:
836 return("RMRC_BAD_RMHANDLE");
837 case RMRC_BAD_FLAGS:
838 return("RMRC_BAD_FLAGS");
839 case RMRC_NO_DETECTED_DATA:
840 return("RMRC_NO_DETECTED_DATA");
841 default:
842 return("RMRC_UNKOWN");
843 }
844}
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