Context Navigation

source: trunk/src/os2ahci/pci.c@ 148

Last change on this file since 148 was 148, checked in by David Azarewicz, 12 years ago
Fix spin-up / power-up issue on some hardware Changes to debug output Fixup makefiles
File size: 43.2 KB

Line
1	/******************************************************************************
2	* PCI.c - PCI constants and detection code for os2ahci driver
3	*
4	* Copyright (c) 2011 thi.guten Software Development
5	* Copyright (c) 2011 Mensys B.V.
6	*
7	* Authors: Christian Mueller, Markus Thielen
8	*
9	* Parts copied from/inspired by the Linux AHCI driver;
10	* those parts are (c) Linux AHCI/ATA maintainers
11	*
12	* This program is free software; you can redistribute it and/or modify
13	* it under the terms of the GNU General Public License as published by
14	* the Free Software Foundation; either version 2 of the License, or
15	* (at your option) any later version.
16	*
17	* This program is distributed in the hope that it will be useful,
18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20	* GNU General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, write to the Free Software
24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25	*/
26
27	#include "os2ahci.h"
28
29	/* -------------------------- macros and constants ------------------------- */
30
31	/* offset of PCI base address register (BAR) in the PCI config space */
32	#define PCI_BAR(reg) (UCHAR) (0x10 + (reg) * sizeof(u32))
33
34	/******************************************************************************
35	* OEMHLP constants for PCI access
36	*/
37	#define GENERIC_IOCTL 0x10
38	#define OH_CATEGORY 0x00
39	#define OH_FUNC_PCI 0x0b
40
41	/* subfunctions */
42	#define OH_BIOS_INFO 0x00
43	#define OH_FIND_DEVICE 0x01
44	#define OH_FIND_CLASS 0x02
45	#define OH_READ_CONFIG 0x03
46	#define OH_WRITE_CONFIG 0x04
47
48	/* return codes */
49	#define OH_SUCCESS 0x00
50	#define OH_NOT_SUPPORTED 0x81
51	#define OH_BAD_VENDOR 0x83
52	#define OH_NOT_FOUND 0x86
53	#define OH_BAD_REGISTER 0x87
54
55	/* ------------------------ typedefs and structures ------------------------ */
56
57	/******************************************************************************
58	* OEMHLP IOCtl parameter union. The parameter area is generally used as input
59	* to the OEMHLP IOCtl calls.
60	*/
61	typedef union {
62
63	/* query PCI BIOS information" */
64	struct {
65	UCHAR subfunction;
66	} bios_info;
67
68	/* find PCI device */
69	struct {
70	UCHAR subfunction;
71	USHORT device;
72	USHORT vendor;
73	UCHAR index;
74	} find_device;
75
76	/* find PCI class code */
77	struct {
78	UCHAR subfunction;
79	ULONG class;
80	UCHAR index;
81	} find_class;
82
83	/* read PCI configuration space */
84	struct {
85	UCHAR subfunction;
86	UCHAR bus;
87	UCHAR dev_func;
88	UCHAR reg;
89	UCHAR size;
90	} read_config;
91
92	/* write PCI configuration space */
93	struct {
94	UCHAR subfunction;
95	UCHAR bus;
96	UCHAR dev_func;
97	UCHAR reg;
98	UCHAR size;
99	ULONG data;
100	} write_config;
101
102	} OH_PARM;
103
104	/******************************************************************************
105	* OEMHLP IOCtl data union. The data area is generally used as output from the
106	* OEMHLP IOCtl calls.
107	*/
108	typedef union {
109
110	/* query PCI BIOS information" */
111	struct {
112	UCHAR rc;
113	UCHAR hw_mech;
114	UCHAR major_version;
115	UCHAR minor_version;
116	UCHAR last_bus;
117	} bios_info;
118
119	/* find PCI device */
120	struct {
121	UCHAR rc;
122	UCHAR bus;
123	UCHAR dev_func;
124	} find_device;
125
126	/* find PCI class code */
127	struct {
128	UCHAR rc;
129	UCHAR bus;
130	UCHAR dev_func;
131	} find_class;
132
133	/* read PCI confguration space */
134	struct {
135	UCHAR rc;
136	ULONG data;
137	} read_config;
138
139	/* write PCI confguration space */
140	struct {
141	UCHAR rc;
142	} write_config;
143
144	} OH_DATA;
145
146	/* -------------------------- function prototypes -------------------------- */
147
148	static void add_pci_device (PCI_ID pci_id, OH_DATA _far data);
149	static int oemhlp_call (UCHAR subfunction, OH_PARM _far *parm,
150	OH_DATA _far *data);
151	static long bar_resource (UCHAR bus, UCHAR dev_func,
152	RESOURCESTRUCT _far *resource, int i);
153	static char *rmerr (APIRET ret);
154
155	/* ------------------------ global/static variables ------------------------ */
156
157	/******************************************************************************
158	* chipset/controller name strings
159	*/
160	static char chip_esb2[] = "ESB2";
161	static char chip_ich8[] = "ICH8";
162	static char chip_ich8m[] = "ICH8M";
163	static char chip_ich9[] = "ICH9";
164	static char chip_ich9m[] = "ICH9M";
165	static char chip_ich10[] = "ICH10";
166	static char chip_pchahci[] = "PCH AHCI";
167	static char chip_pchraid[] = "PCH RAID";
168	static char chip_tolapai[] = "Tolapai";
169	static char chip_sb600[] = "SB600";
170	static char chip_sb700[] = "SB700/800";
171	static char chip_vt8251[] = "VT8251";
172	static char chip_mcp65[] = "MCP65";
173	static char chip_mcp67[] = "MCP67";
174	static char chip_mcp73[] = "MCP73";
175	static char chip_mcp77[] = "MCP77";
176	static char chip_mcp79[] = "MCP79";
177	static char chip_mcp89[] = "MCP689";
178	static char chip_sis968[] = "968";
179
180	static char s_generic[] = "Generic";
181
182
183
184	/******************************************************************************
185	* PCI vendor and device IDs for known AHCI adapters. Copied from the Linux
186	* AHCI driver.
187	*/
188
189	PCI_ID pci_ids[] = {
190
191	/* Intel
192	* NOTE: ICH5 controller does NOT support AHCI, so we do
193	* not add it here! */
194	{ PCI_VDEVICE(INTEL, 0x2652), board_ahci, "ICH6" }, /* ICH6 */
195	{ PCI_VDEVICE(INTEL, 0x2653), board_ahci, "ICH6M" }, /* ICH6M */
196	{ PCI_VDEVICE(INTEL, 0x27c1), board_ahci, "ICH7" }, /* ICH7 */
197	{ PCI_VDEVICE(INTEL, 0x27c5), board_ahci, "ICH7M" }, /* ICH7M */
198	{ PCI_VDEVICE(INTEL, 0x27c3), board_ahci, "ICH7R" }, /* ICH7R */
199	{ PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr, "ULiM5288" }, /* ULi M5288 */
200	{ PCI_VDEVICE(INTEL, 0x2681), board_ahci, chip_esb2 }, /* ESB2 */
201	{ PCI_VDEVICE(INTEL, 0x2682), board_ahci, chip_esb2 }, /* ESB2 */
202	{ PCI_VDEVICE(INTEL, 0x2683), board_ahci, chip_esb2 }, /* ESB2 */
203	{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci, "ICH7MDH" }, /* ICH7-M DH */
204	{ PCI_VDEVICE(INTEL, 0x2821), board_ahci, chip_ich8 }, /* ICH8 */
205	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf, chip_ich8 }, /* ICH8 */
206	{ PCI_VDEVICE(INTEL, 0x2824), board_ahci, chip_ich8 }, /* ICH8 */
207	{ PCI_VDEVICE(INTEL, 0x2829), board_ahci, chip_ich8m }, /* ICH8M */
208	{ PCI_VDEVICE(INTEL, 0x282a), board_ahci, chip_ich8m }, /* ICH8M */
209	{ PCI_VDEVICE(INTEL, 0x2922), board_ahci, chip_ich9 }, /* ICH9 */
210	{ PCI_VDEVICE(INTEL, 0x2923), board_ahci, chip_ich9 }, /* ICH9 */
211	{ PCI_VDEVICE(INTEL, 0x2924), board_ahci, chip_ich9 }, /* ICH9 */
212	{ PCI_VDEVICE(INTEL, 0x2925), board_ahci, chip_ich9 }, /* ICH9 */
213	{ PCI_VDEVICE(INTEL, 0x2927), board_ahci, chip_ich9 }, /* ICH9 */
214	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci, chip_ich9m }, /* ICH9M */
215	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci, chip_ich9m }, /* ICH9M */
216	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci, chip_ich9m }, /* ICH9M */
217	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci, chip_ich9m }, /* ICH9M */
218	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci, chip_ich9m }, /* ICH9M */
219	{ PCI_VDEVICE(INTEL, 0x294d), board_ahci, chip_ich9 }, /* ICH9 */
220	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci, chip_ich9m }, /* ICH9M */
221	{ PCI_VDEVICE(INTEL, 0x502a), board_ahci, chip_tolapai }, /* Tolapai */
222	{ PCI_VDEVICE(INTEL, 0x502b), board_ahci, chip_tolapai }, /* Tolapai */
223	{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci, chip_ich10 }, /* ICH10 */
224	{ PCI_VDEVICE(INTEL, 0x3a22), board_ahci, chip_ich10 }, /* ICH10 */
225	{ PCI_VDEVICE(INTEL, 0x3a25), board_ahci, chip_ich10 }, /* ICH10 */
226	{ PCI_VDEVICE(INTEL, 0x3b22), board_ahci, chip_pchahci }, /* PCH AHCI */
227	{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci, chip_pchahci }, /* PCH AHCI */
228	{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci, chip_pchraid }, /* PCH RAID */
229	{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci, chip_pchraid }, /* PCH RAID */
230	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci, chip_pchahci }, /* PCH AHCI */
231	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci, chip_pchraid }, /* PCH RAID */
232	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci, chip_pchraid }, /* PCH RAID */
233	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci, chip_pchahci }, /* PCH AHCI */
234
235	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
236	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
237	PCI_CLASS_STORAGE_SATA_AHCI, 0xffffffL, board_ahci_ign_iferr, "360" },
238
239	/* ATI */
240	{ PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600, chip_sb600 }, /* ATI SB600 */
241	{ PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
242	{ PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
243	{ PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
244	{ PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
245	{ PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
246	{ PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
247
248	/* AMD */
249	{ PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
250	/* AMD is using RAID class only for ahci controllers */
251	{ PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
252	PCI_CLASS_STORAGE_RAID << 8, 0xffffffL, board_ahci, "Hudson2" },
253
254	/* VIA */
255	{ PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251, chip_vt8251 }, /* VIA VT8251 */
256	{ PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251, chip_vt8251 }, /* VIA VT8251 */
257
258	/* NVIDIA */
259	{ PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
260	{ PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
261	{ PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
262	{ PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
263	{ PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
264	{ PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
265	{ PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
266	{ PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
267	{ PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
268	{ PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
269	{ PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
270	{ PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
271	{ PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
272	{ PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
273	{ PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
274	{ PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
275	{ PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
276	{ PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
277	{ PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
278	{ PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
279	{ PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq, chip_mcp67 }, /* Linux ID */
280	{ PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
281	{ PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
282	{ PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
283	{ PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
284	{ PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
285	{ PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
286	{ PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
287	{ PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
288	{ PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
289	{ PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
290	{ PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
291	{ PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
292	{ PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci, chip_mcp77 }, /* MCP77 */
293	{ PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci, chip_mcp77 }, /* MCP77 */
294	{ PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci, chip_mcp77 }, /* MCP77 */
295	{ PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci, chip_mcp77 }, /* MCP77 */
296	{ PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci, chip_mcp77 }, /* MCP77 */
297	{ PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci, chip_mcp77 }, /* MCP77 */
298	{ PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci, chip_mcp77 }, /* MCP77 */
299	{ PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci, chip_mcp77 }, /* MCP77 */
300	{ PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci, chip_mcp77 }, /* MCP77 */
301	{ PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci, chip_mcp77 }, /* MCP77 */
302	{ PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci, chip_mcp77 }, /* MCP77 */
303	{ PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci, chip_mcp77 }, /* MCP77 */
304	{ PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci, chip_mcp79 }, /* MCP79 */
305	{ PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci, chip_mcp79 }, /* MCP79 */
306	{ PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci, chip_mcp79 }, /* MCP79 */
307	{ PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci, chip_mcp79 }, /* MCP79 */
308	{ PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci, chip_mcp79 }, /* MCP79 */
309	{ PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci, chip_mcp79 }, /* MCP79 */
310	{ PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci, chip_mcp79 }, /* MCP79 */
311	{ PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci, chip_mcp79 }, /* MCP79 */
312	{ PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci, chip_mcp79 }, /* MCP79 */
313	{ PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci, chip_mcp79 }, /* MCP79 */
314	{ PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci, chip_mcp79 }, /* MCP79 */
315	{ PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci, chip_mcp79 }, /* MCP79 */
316	{ PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci, chip_mcp89 }, /* MCP89 */
317	{ PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci, chip_mcp89 }, /* MCP89 */
318	{ PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci, chip_mcp89 }, /* MCP89 */
319	{ PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci, chip_mcp89 }, /* MCP89 */
320	{ PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci, chip_mcp89 }, /* MCP89 */
321	{ PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci, chip_mcp89 }, /* MCP89 */
322	{ PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci, chip_mcp89 }, /* MCP89 */
323	{ PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci, chip_mcp89 }, /* MCP89 */
324	{ PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci, chip_mcp89 }, /* MCP89 */
325	{ PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci, chip_mcp89 }, /* MCP89 */
326	{ PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci, chip_mcp89 }, /* MCP89 */
327	{ PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci, chip_mcp89 }, /* MCP89 */
328
329	/* SiS */
330	{ PCI_VDEVICE(SI, 0x1184), board_ahci, "966" }, /* SiS 966 */
331	{ PCI_VDEVICE(SI, 0x1185), board_ahci, chip_sis968 }, /* SiS 968 */
332	{ PCI_VDEVICE(SI, 0x0186), board_ahci, chip_sis968 }, /* SiS 968 */
333
334	/* Marvell */
335	{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv, "6145" }, /* 6145 */
336	{ PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv, "6121" }, /* 6121 */
337
338	/* Promise */
339	{ PCI_VDEVICE(PROMISE, 0x3f20), board_ahci, "PDC42819" }, /* PDC42819 */
340
341	/* Generic, PCI class code for AHCI */
342	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
343	PCI_CLASS_STORAGE_SATA_AHCI, 0xffffffL, board_ahci, s_generic },
344
345	/* end of list, including a few slots to define custom adapters (10) */
346	{ 0, 0, 0, 0, 0, 0, 0, NULL },
347	{ 0, 0, 0, 0, 0, 0, 0, NULL },
348	{ 0, 0, 0, 0, 0, 0, 0, NULL },
349	{ 0, 0, 0, 0, 0, 0, 0, NULL },
350	{ 0, 0, 0, 0, 0, 0, 0, NULL },
351	{ 0, 0, 0, 0, 0, 0, 0, NULL },
352	{ 0, 0, 0, 0, 0, 0, 0, NULL },
353	{ 0, 0, 0, 0, 0, 0, 0, NULL },
354	{ 0, 0, 0, 0, 0, 0, 0, NULL },
355	{ 0, 0, 0, 0, 0, 0, 0, NULL },
356
357	{ 0, 0, 0, 0, 0, 0, 0, NULL }
358	};
359
360	/******************************************************************************
361	* OEMHLP$ is used by OS/2 to provide access to OEM-specific machine resources
362	* like PCI BIOS access. We're using this to enumerate the PCI bus. Due to
363	* BIOS bugs, it may be necessary to use I/O operations for this purpose but
364	* so far I think this is only relevant for rather old PCs and SATA is not
365	* expected to be a priority on those machines.
366	*/
367	static IDCTABLE oemhlp; /* OEMHLP$ IDC entry point */
368
369	/* ----------------------------- start of code ----------------------------- */
370
371	/******************************************************************************
372	* Add specified PCI vendor and device ID to the list of supported AHCI
373	* controllers. Please note that the last slot in pci_ids needs to remain
374	* empty because it's used as end marker.
375	*/
376	int add_pci_id(u16 vendor, u16 device)
377	{
378	int max_slot = sizeof(pci_ids) / sizeof(*pci_ids) - 2;
379	int i;
380
381	/* search for last used slot in 'pci_ids' */
382	for (i = max_slot; i >= 0 && pci_ids[i].vendor == 0; i--);
383	if (i >= max_slot) {
384	/* all slots in use */
385	return(-1);
386	}
387
388	/* use slot after the last used slot */
389	i++;
390	pci_ids[i].vendor = vendor;
391	pci_ids[i].device = device;
392	pci_ids[i].board = board_ahci;
393	pci_ids[i].chipname = s_generic;
394	return(0);
395	}
396
397	/******************************************************************************
398	* Scan PCI bus using OEMHLP$ IOCTLs and build adapter list.
399	*/
400	void scan_pci_bus(void)
401	{
402	OH_PARM parm;
403	OH_DATA data;
404	UCHAR index;
405	UCHAR rc;
406	int ad_indx = 0;
407	int i;
408	int n;
409
410	ddprintf("scanning PCI bus...\n");
411
412	/* verify that we have a PCI system */
413	memset(&parm, 0x00, sizeof(parm));
414	if (oemhlp_call(OH_BIOS_INFO, &parm, &data) != OH_SUCCESS) {
415	cprintf("%s: couldn't get PCI BIOS information\n", drv_name);
416	return;
417	}
418
419	/* Go through the list of PCI IDs and search for each device
420	*
421	* NOTES:
422	*
423	* - When searching via class code, the OEMHLP$ interface doesn't allow
424	* setting a bitmask to look for individual portions of class code,
425	* subclass code and programming interface. However, all bitmasks in the
426	* PCI list currently use 0xffffff, thus this should not be a problem at
427	* this point in time.
428	*
429	* - Scanning via OEMHLP$ seems rather slow, at least in the virtual
430	* machine I'm currenly using to test this driver. Thus, class code
431	* scans are preferred unless the option "-t" (thorough_scan) has been
432	* specified. The assumption is that most, if not all, modern AHCI
433	* adapters have the correct class code (PCI_CLASS_STORAGE_SATA_AHCI).
434	*/
435	for (i = 0; pci_ids[i].vendor != 0; i++) {
436	index = 0;
437	do {
438	if (pci_ids[i].device == PCI_ANY_ID \|\| pci_ids[i].vendor == PCI_ANY_ID) {
439	/* look for class code */
440	memset(&parm, 0x00, sizeof(parm));
441	parm.find_class.class = pci_ids[i].class;
442	parm.find_class.index = index;
443	rc = oemhlp_call(OH_FIND_CLASS, &parm, &data);
444
445	} else if (thorough_scan) {
446	/* look for this specific vendor and device ID */
447	memset(&parm, 0x00, sizeof(parm));
448	parm.find_device.device = pci_ids[i].device;
449	parm.find_device.vendor = pci_ids[i].vendor;
450	parm.find_device.index = index;
451	rc = oemhlp_call(OH_FIND_DEVICE, &parm, &data);
452
453	} else {
454	rc = OH_NOT_FOUND;
455	}
456
457	if (rc == OH_SUCCESS) {
458	/* found a device */
459	int already_found = 0;
460
461	/* increment index for next loop */
462	if (++index > 180) {
463	/* something's wrong here... */
464	return;
465	}
466
467	/* check whether we already found this device */
468	for (n = 0; n < ad_info_cnt; n++) {
469	if (ad_infos[n].bus == data.find_device.bus &&
470	ad_infos[n].dev_func == data.find_device.dev_func) {
471	/* this device has already been found (e.g. via thorough scan) */
472	already_found = 1;
473	break;
474	}
475	}
476
477	if (already_found \|\| (ad_ignore & (1U << ad_indx++))) {
478	/* ignore this device; it has either already been found via a
479	* thorough scan or has been specified to be ignored via command
480	* line option */
481	continue;
482	}
483
484	/* add this PCI device to ad_infos[] */
485	add_pci_device(pci_ids + i, &data);
486	}
487
488	} while (rc == OH_SUCCESS);
489	}
490	}
491
492	/******************************************************************************
493	* Enable interrupt generation. PCI 2.3 added a bit which allows disabling
494	* interrupt generation for a device. This function clears the corresponding
495	* bit in the configuration space command register.
496	*/
497	int pci_enable_int(UCHAR bus, UCHAR dev_func)
498	{
499	ULONG tmp;
500
501	if (pci_read_conf (bus, dev_func, 4, sizeof(u32), &tmp) != OH_SUCCESS \|\|
502	pci_write_conf(bus, dev_func, 4, sizeof(u32), tmp & ~(1UL << 10)) != OH_SUCCESS) {
503	return(-1);
504	}
505	return(0);
506	}
507
508	/******************************************************************************
509	* Hack to set up proper IRQ mappings in the emulated PIIX3 ISA bridge in
510	* VirtualBox (for some reason, the first mapped IRQ is 0x80 without this
511	* hack).
512	*/
513	void pci_hack_virtualbox(void)
514	{
515	ULONG irq = 0;
516
517	if (pci_read_conf(0, 0x08, 0x60, 1, &irq) == OH_SUCCESS && irq == 0x80) {
518	/* set IRQ for first device/func to 11 */
519	dprintf("hacking virtualbox PIIX3 PCI to ISA bridge IRQ mapping\n");
520	irq = ad_infos[0].irq;
521	pci_write_conf(0, 0x08, 0x60, 1, irq);
522	}
523	}
524
525	/******************************************************************************
526	* Add a single PCI device to the list of adapters.
527	*/
528	static void add_pci_device(PCI_ID pci_id, OH_DATA _far data)
529	{
530	char rc_list_buf[sizeof(AHRESOURCE) + sizeof(HRESOURCE) * 15];
531	AHRESOURCE _far rc_list = (AHRESOURCE _far ) rc_list_buf;
532	RESOURCESTRUCT resource;
533	ADAPTERSTRUCT adapter;
534	ADJUNCT adj;
535	AD_INFO *ad_info;
536	APIRET ret;
537	UCHAR bus = data->find_class.bus;
538	UCHAR dev_func = data->find_class.dev_func;
539	ULONG val;
540	SEL gdt[PORT_DMA_BUF_SEGS + 1];
541	char tmp[40];
542	u16 device;
543	u16 vendor;
544	u32 class;
545	int irq;
546	int pin;
547	int i;
548
549	/*****************************************************************************
550	* Part 1: Get further information about the device to be added; PCI ID...
551	*/
552	if (pci_read_conf(bus, dev_func, 0x00, sizeof(ULONG), &val) != OH_SUCCESS) {
553	return;
554	}
555	device = (u16) (val >> 16);
556	vendor = (u16) (val & 0xffff);
557
558	/* ... and class code */
559	if (pci_read_conf(bus, dev_func, 0x08, sizeof(ULONG), &val) != OH_SUCCESS) {
560	return;
561	}
562	class = (u32) (val >> 8);
563
564	if (pci_id->device == PCI_ANY_ID) {
565	/* We found this device in a wildcard search. There are two possible
566	* reasons which require a different handling:
567	*
568	* 1) This device uses a non-standard PCI class and has been identified
569	* with the corresponding class in pci_ids[] (e.g. the entry
570	* PCI_VENDOR_ID_JMICRON), but there is a vendor ID in pci_ids[]. In
571	* this case, we need to verify that the vendor is correct (see
572	* comments regarding OEMHLP limitations in 'scan_pci_bus()')
573	*
574	* 2) This device was identified using a generic PCI class for AHCI
575	* adapters such as PCI_CLASS_STORAGE_SATA_AHCI and we need to map
576	* the device and vendor ID to the corresponding index in pci_ids[]
577	* if there is such an entry; the index passed to this function will
578	* be the generic class-based index which is fine as long as there's
579	* not special treatment required as indicated by the board_*
580	* constants in pci_ids[]...
581	*
582	* The main reason for this kludge is that it seems as if OEMHLP$
583	* is rather slow searching for PCI devices, adding around 30s
584	* to the boot time when scanning for individual AHCI PCI IDs. Thus,
585	* the OS2AHCI driver avoids this kind of scan in favor of a class-
586	* based scan (unless overridden with the "/T" option).
587	*/
588	if (pci_id->vendor != PCI_ANY_ID) {
589	/* case 1: the vendor is known but we found the PCI device using a class
590	* search; verify vendor matches the one in pci_ids[]
591	*/
592	if (pci_id->vendor != vendor) {
593	/* vendor doesn't match */
594	return;
595	}
596
597	} else {
598	/* case 2: we found this device using a generic class search; if the
599	* device/vendor is listed in pci_ids[], use this entry in favor of the
600	* one passed in 'pci_id'
601	*/
602	for (i = 0; pci_ids[i].vendor != 0; i++) {
603	if (pci_ids[i].device == device && pci_ids[i].vendor == vendor) {
604	pci_id = pci_ids + i;
605	break;
606	}
607	}
608	}
609	}
610
611	/* found a supported AHCI device */
612	ciiprintf("found AHCI device: %s %s (%04x:%04x)\n"
613	" class:0x%06lx bus:%d devfunc:0x%02x\n",
614	vendor_from_id(vendor), device_from_id(device),
615	vendor, device,
616	class, bus, dev_func);
617
618	/* make sure we got room in the adapter information array */
619	if (ad_info_cnt >= MAX_AD - 1) {
620	cprintf("%s: too many AHCI devices\n", drv_name);
621	return;
622	}
623
624	/****************************************************************************
625	* Part 2: Determine resource requirements and allocate resources with the
626	* OS/2 resource manager. While doing so, some of the entries of the
627	* corresponding slot in the AD_INFO array, namely resource manager
628	* handles, are initialized so we need prepare the slot.
629	*
630	* NOTE: While registering resources with the resource manager, each new
631	* resource is added to the corresponding rc_list.hResource[] slot.
632	* rc_list is used further down to associate resources to adapters
633	* when the adapter itself is registered with the OS/2 resource
634	* manager.
635	*/
636	ad_info = ad_infos + ad_info_cnt;
637	memset(ad_info, 0x00, sizeof(*ad_info));
638	rc_list->NumResource = 0;
639
640	/* Register IRQ with resource manager
641	*
642	* NOTE: We rely on the IRQ number saved in the PCI config space by the PCI
643	* BIOS. There's no reliable way to find out the IRQ number in any
644	* other way unless we start using message-driven interrupts (which
645	* is out of scope for the time being).
646	*/
647	if (pci_read_conf(bus, dev_func, 0x3c, sizeof(u32), &val) != OH_SUCCESS) {
648	return;
649	}
650	irq = (int) (val & 0xff);
651	pin = (int) ((val >> 8) & 0xff);
652
653	memset(&resource, 0x00, sizeof(resource));
654	resource.ResourceType = RS_TYPE_IRQ;
655	resource.IRQResource.IRQLevel = irq;
656	resource.IRQResource.PCIIrqPin = pin;
657	resource.IRQResource.IRQFlags = RS_IRQ_SHARED;
658
659	ret = RMAllocResource(rm_drvh, &ad_info->rm_irq, &resource);
660	if (ret != RMRC_SUCCESS) {
661	cprintf("%s: couldn't register IRQ %d (rc = %s)\n", drv_name, irq, rmerr(ret));
662	return;
663	}
664	rc_list->hResource[rc_list->NumResource++] = ad_info->rm_irq;
665
666	/* Allocate all I/O and MMIO addresses offered by this device. In theory,
667	* we need only BAR #5, the AHCI MMIO BAR, but in order to prevent any
668	* other driver from hijacking our device and accessing it via legacy
669	* registers we'll reserve anything we can find.
670	*/
671	for (i = 0; i < sizeof(ad_info->rm_bars) / sizeof(*ad_info->rm_bars); i++) {
672	long len = bar_resource(bus, dev_func, &resource, i);
673
674	if (len < 0) {
675	/* something went wrong */
676	goto add_pci_fail;
677	}
678	if (len == 0) {
679	/* this BAR is unused */
680	continue;
681	}
682
683	if (i == AHCI_PCI_BAR) {
684	if (resource.ResourceType != RS_TYPE_MEM) {
685	cprintf("%s: BAR #5 must be an MMIO region\n", drv_name);
686	goto add_pci_fail;
687	}
688	/* save this BAR's address as MMIO address */
689	ad_info->mmio_phys = resource.MEMResource.MemBase;
690	ad_info->mmio_size = resource.MEMResource.MemSize;
691	}
692
693	/* register [MM]IO region with resource manager */
694	ret = RMAllocResource(rm_drvh, ad_info->rm_bars + i, &resource);
695	if (ret != RMRC_SUCCESS) {
696	cprintf("%s: couldn't register [MM]IO region (rc = %s)\n",
697	drv_name, rmerr(ret));
698	goto add_pci_fail;
699	}
700	rc_list->hResource[rc_list->NumResource++] = ad_info->rm_bars[i];
701	}
702
703	if (ad_info->mmio_phys == 0) {
704	cprintf("%s: couldn't determine MMIO base address\n", drv_name);
705	goto add_pci_fail;
706	}
707
708	/****************************************************************************
709	* Part 3: Fill in the remaining fields in the AD_INFO slot and allocate
710	* memory and GDT selectors for the adapter. Finally, register the adapter
711	* itself with the OS/2 resource manager
712	*/
713	ad_info->pci = pci_ids + i;
714	ad_info->bus = bus;
715	ad_info->dev_func = dev_func;
716	ad_info->irq = irq;
717
718	/* allocate memory for port-specific DMA scratch buffers */
719	if (DevHelp_AllocPhys((long) AHCI_PORT_PRIV_DMA_SZ * AHCI_MAX_PORTS,
720	MEMTYPE_ABOVE_1M, &ad_info->dma_buf_phys) != 0) {
721	cprintf("%s: couldn't allocate DMA scratch buffers for AHCI ports\n", drv_name);
722	ad_info->dma_buf_phys = 0;
723	goto add_pci_fail;
724	}
725
726	/* allocate GDT selectors for memory-mapped I/O and DMA scratch buffers */
727	if (DevHelp_AllocGDTSelector(gdt, PORT_DMA_BUF_SEGS + 1) != 0) {
728	cprintf("%s: couldn't allocate GDT selectors\n", drv_name);
729	memset(gdt, 0x00, sizeof(gdt));
730	goto add_pci_fail;
731	}
732
733	/* map MMIO address to first GDT selector */
734	if (DevHelp_PhysToGDTSelector(ad_info->mmio_phys,
735	(USHORT) ad_info->mmio_size, gdt[0]) != 0) {
736	cprintf("%s: couldn't map MMIO address to GDT selector\n", drv_name);
737	goto add_pci_fail;
738	}
739
740	/* map DMA scratch buffers to remaining GDT selectors */
741	for (i = 0; i < PORT_DMA_BUF_SEGS; i++) {
742	ULONG addr = ad_info->dma_buf_phys + i * PORT_DMA_SEG_SIZE;
743	USHORT len = AHCI_PORT_PRIV_DMA_SZ * PORT_DMA_BUFS_PER_SEG;
744
745	if (DevHelp_PhysToGDTSelector(addr, len, gdt[i+1]) != 0) {
746	cprintf("%s: couldn't map DMA scratch buffer to GDT selector\n", drv_name);
747	goto add_pci_fail;
748	}
749	}
750
751	/* fill in MMIO and DMA scratch buffer addresses in adapter info */
752	ad_info->mmio = (u8 _far *) ((u32) gdt[0] << 16);
753	for (i = 0; i < PORT_DMA_BUF_SEGS; i++) {
754	ad_info->dma_buf[i] = (u8 _far *) ((u32) gdt[i+1] << 16);
755	}
756
757	/* register adapter with resource manager */
758	memset(&adj, 0x00, sizeof(adj));
759	adj.pNextAdj = NULL;
760	adj.AdjLength = sizeof(adj);
761	adj.AdjType = ADJ_ADAPTER_NUMBER;
762	adj.Adapter_Number = ad_info_cnt;
763
764	memset(&adapter, 0x00, sizeof(adapter));
765	sprintf(tmp, "AHCI_%d Controller", ad_info_cnt);
766	adapter.AdaptDescriptName = tmp;
767	adapter.AdaptFlags = 0;
768	adapter.BaseType = AS_BASE_MSD;
769	adapter.SubType = AS_SUB_IDE;
770	adapter.InterfaceType = AS_INTF_GENERIC;
771	adapter.HostBusType = AS_HOSTBUS_PCI;
772	adapter.HostBusWidth = AS_BUSWIDTH_32BIT;
773	adapter.pAdjunctList = &adj;
774
775	ret = RMCreateAdapter(rm_drvh, &ad_info->rm_adh, &adapter, NULL, rc_list);
776	if (ret != RMRC_SUCCESS) {
777	cprintf("%s: couldn't register adapter (rc = %s)\n", drv_name, rmerr(ret));
778	goto add_pci_fail;
779	}
780
781	/* Successfully added the adapter and reserved its resources; the adapter
782	* is still under BIOS control so we're not going to do anything else at
783	* this point.
784	*/
785	ad_info_cnt++;
786	return;
787
788	add_pci_fail:
789	/* something went wrong; try to clean up as far as possible */
790	for (i = 0; i < sizeof(ad_info->rm_bars) / sizeof(*ad_info->rm_bars); i++) {
791	if (ad_info->rm_bars[i] != 0) {
792	RMDeallocResource(rm_drvh, ad_info->rm_bars[i]);
793	}
794	}
795	if (ad_info->rm_irq != 0) {
796	RMDeallocResource(rm_drvh, ad_info->rm_irq);
797	}
798	for (i = 0; i < sizeof(gdt) / sizeof(*gdt); i++) {
799	if (gdt[i] != 0) {
800	DevHelp_FreeGDTSelector(gdt[i]);
801	}
802	}
803	if (ad_info->dma_buf_phys != 0) {
804	DevHelp_FreePhys(ad_info->dma_buf_phys);
805	}
806	}
807
808	/******************************************************************************
809	* Read PCI configuration space register
810	*/
811	UCHAR pci_read_conf(UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
812	ULONG _far *val)
813	{
814	OH_PARM parm;
815	OH_DATA data;
816	UCHAR rc;
817
818	memset(&parm, 0x00, sizeof(parm));
819	parm.read_config.bus = bus;
820	parm.read_config.dev_func = dev_func;
821	parm.read_config.reg = indx;
822	parm.read_config.size = size;
823	if ((rc = oemhlp_call(OH_READ_CONFIG, &parm, &data) != OH_SUCCESS)) {
824	cprintf("%s: couldn't read config space (bus = %d, dev_func = 0x%02x, indx = 0x%02x, rc = %d)\n",
825	drv_name, bus, dev_func, indx, rc);
826	return(rc);
827	}
828
829	*val = data.read_config.data;
830	return(OH_SUCCESS);
831	}
832
833	/******************************************************************************
834	* Write PCI configuration space register
835	*/
836	UCHAR pci_write_conf(UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
837	ULONG val)
838	{
839	OH_PARM parm;
840	OH_DATA data;
841	UCHAR rc;
842
843	memset(&parm, 0x00, sizeof(parm));
844	parm.write_config.bus = bus;
845	parm.write_config.dev_func = dev_func;
846	parm.write_config.reg = indx;
847	parm.write_config.size = size;
848	parm.write_config.data = val;
849
850	if ((rc = oemhlp_call(OH_WRITE_CONFIG, &parm, &data) != OH_SUCCESS)) {
851	cprintf("%s: couldn't write config space (bus = %d, dev_func = 0x%02x, indx = 0x%02x, rc = %d)\n",
852	drv_name, bus, dev_func, indx, rc);
853	return(rc);
854	}
855
856	return(OH_SUCCESS);
857	}
858	/******************************************************************************
859	* Call OEMHLP$ IDC entry point with the specified IOCtl parameter and data
860	* packets.
861	*/
862	static int oemhlp_call(UCHAR subfunction, OH_PARM _far *parm,
863	OH_DATA _far *data)
864	{
865	void (_far *func)(void);
866	RP_GENIOCTL ioctl;
867	unsigned short prot_idc_ds;
868
869	if (oemhlp.ProtIDCEntry == NULL \|\| oemhlp.ProtIDC_DS == 0) {
870	/* attach to OEMHLP$ device driver */
871	if (DevHelp_AttachDD("OEMHLP$ ", (NPBYTE) &oemhlp) \|\|
872	oemhlp.ProtIDCEntry == NULL \|\|
873	oemhlp.ProtIDC_DS == 0) {
874	cprintf("%s: couldn't attach to OEMHLP$\n", drv_name);
875	return(OH_NOT_SUPPORTED);
876	}
877	}
878
879	/* store subfuntion in first byte of pararameter packet */
880	parm->bios_info.subfunction = subfunction;
881	memset(data, 0x00, sizeof(*data));
882
883	/* assemble IOCtl request */
884	memset(&ioctl, 0x00, sizeof(ioctl));
885	ioctl.rph.Len = sizeof(ioctl);
886	ioctl.rph.Unit = 0;
887	ioctl.rph.Cmd = GENERIC_IOCTL;
888	ioctl.rph.Status = 0;
889
890	ioctl.Category = OH_CATEGORY;
891	ioctl.Function = OH_FUNC_PCI;
892	ioctl.ParmPacket = (PUCHAR) parm;
893	ioctl.DataPacket = (PUCHAR) data;
894	ioctl.ParmLen = sizeof(*parm);
895	ioctl.DataLen = sizeof(*data);
896
897	/* Call OEMHLP's IDC routine. Before doing so, we need to assign the address
898	* to be called to a stack variable because the inter-device driver calling
899	* convention forces us to set DS to the device driver's data segment and ES
900	* to the segment of the request packet.
901	*/
902	func = oemhlp.ProtIDCEntry;
903
904	/* The WATCOM compiler does not support struct references in inline
905	* assembler code, so we pass it in a stack variable
906	*/
907	prot_idc_ds = oemhlp.ProtIDC_DS;
908
909	_asm {
910	push ds;
911	push es;
912	push bx;
913	push si;
914	push di;
915
916	push ss
917	pop es
918	lea bx, ioctl;
919	mov ds, prot_idc_ds;
920	call dword ptr [func];
921
922	pop di;
923	pop si;
924	pop bx;
925	pop es;
926	pop ds;
927	}
928
929	dddphex(parm, sizeof(*parm), "oemhlp_parm: ");
930	dddphex(data, sizeof(*data), "oemhlp_data: ");
931
932	if (ioctl.rph.Status & STERR) {
933	return(OH_NOT_SUPPORTED);
934	}
935	return(data->bios_info.rc);
936	}
937
938	/******************************************************************************
939	* Prepare a resource structure for a PCI Base Address Register (BAR). This
940	* basically means the type, address and range of the I/O address space. It
941	* returns the length of the address range as a signed long to allow the caller
942	* to differentiate between error conditions (< 0), unused BARs (0) or valid
943	* bars (> 0).
944	*
945	* NOTE: In order to do this, we need to temporarily write 0xffffffff to
946	* the MMIO base address register (BAR), read back the resulting value
947	* and check the 0 bits from the right end, masking the lower 2 (I/O) or
948	* 4 (MMIO) bits. After doing this, we must restore the original value
949	* set up by the BIOS.
950	*
951	* 31 4 3 2 1 0
952	* -------------------------------------------------------------------
953	* base address P T T I
954	* P = prefetchable
955	* T = type (0 = any 32 bit, 1 = <1M, 2 = 64 bit)
956	* I = I/O (1) or memory (0)
957	*/
958	static long bar_resource(UCHAR bus, UCHAR dev_func,
959	RESOURCESTRUCT _far *resource, int i)
960	{
961	u32 bar_addr = 0;
962	u32 bar_size = 0;
963
964	/* temporarily write 1s to this BAR to determine the address range */
965	if (pci_read_conf (bus, dev_func, PCI_BAR(i), sizeof(u32), &bar_addr) != OH_SUCCESS \|\|
966	pci_write_conf(bus, dev_func, PCI_BAR(i), sizeof(u32), ~(0UL)) != OH_SUCCESS \|\|
967	pci_read_conf (bus, dev_func, PCI_BAR(i), sizeof(u32), &bar_size) != OH_SUCCESS \|\|
968	pci_write_conf(bus, dev_func, PCI_BAR(i), sizeof(u32), bar_addr) != OH_SUCCESS) {
969
970	cprintf("%s: couldn't determine [MM]IO size\n", drv_name);
971	if (bar_addr != 0) {
972	pci_write_conf(bus, dev_func, PCI_BAR(i), sizeof(u32), bar_addr);
973	}
974	return(-1);
975	}
976
977	if (bar_size == 0 \|\| bar_size == 0xffffffffUL) {
978	/* bar not implemented or device not working properly */
979	return(0);
980	}
981
982	/* prepare resource allocation structure */
983	memset(resource, 0x00, sizeof(*resource));
984	if (bar_addr & 1) {
985	bar_size = ~(bar_size & 0xfffffffcUL) + 1;
986	bar_size &= 0xffffUL; /* I/O address space is 16 bits on x86 */
987	bar_addr &= 0xfffcUL;
988
989	resource->ResourceType = RS_TYPE_IO;
990	resource->IOResource.BaseIOPort = bar_addr;
991	resource->IOResource.NumIOPorts = bar_size;
992	resource->IOResource.IOFlags = RS_IO_EXCLUSIVE;
993	resource->IOResource.IOAddressLines = 16;
994
995	} else {
996	bar_size = ~(bar_size & 0xfffffff0UL) + 1;
997	bar_addr &= 0xfffffff0UL;
998
999	resource->ResourceType = RS_TYPE_MEM;
1000	resource->MEMResource.MemBase = bar_addr;
1001	resource->MEMResource.MemSize = bar_size;
1002	resource->MEMResource.MemFlags = RS_MEM_EXCLUSIVE;
1003	}
1004
1005	ddprintf("BAR #%d: type = %s, addr = 0x%08lx, size = %ld\n", i,
1006	(resource->ResourceType == RS_TYPE_IO) ? "I/O" : "MEM",
1007	bar_addr, bar_size);
1008
1009	return((long) bar_size);
1010	}
1011
1012	/******************************************************************************
1013	* return vendor name for PCI vendor ID
1014	*/
1015	char *vendor_from_id(u16 id)
1016	{
1017
1018	switch(id) {
1019
1020	case PCI_VENDOR_ID_AL:
1021	return "Ali";
1022	case PCI_VENDOR_ID_AMD:
1023	case PCI_VENDOR_ID_ATI:
1024	return "AMD";
1025	case PCI_VENDOR_ID_AT:
1026	return "Allied Telesyn";
1027	case PCI_VENDOR_ID_ATT:
1028	return "ATT";
1029	case PCI_VENDOR_ID_CMD:
1030	return "CMD";
1031	case PCI_VENDOR_ID_CT:
1032	return "CT";
1033	case PCI_VENDOR_ID_INTEL:
1034	return "Intel";
1035	case PCI_VENDOR_ID_INITIO:
1036	return "Initio";
1037	case PCI_VENDOR_ID_JMICRON:
1038	return "JMicron";
1039	case PCI_VENDOR_ID_MARVELL:
1040	return "Marvell";
1041	case PCI_VENDOR_ID_NVIDIA:
1042	return "NVIDIA";
1043	case PCI_VENDOR_ID_PROMISE:
1044	return "PROMISE";
1045	case PCI_VENDOR_ID_SI:
1046	return "SiS";
1047	case PCI_VENDOR_ID_VIA:
1048	return "VIA";
1049	default:
1050	break;
1051	}
1052
1053	return "Generic";
1054
1055	}
1056
1057	/******************************************************************************
1058	* return a device name for a PCI device id
1059	* NOTE: this is as simple as can be, so don't call it twice in one statement.
1060	*/
1061	char *device_from_id(u16 device)
1062	{
1063	int i;
1064
1065	for (i = 0; pci_ids[i].vendor != 0; i++) {
1066
1067	if (pci_ids[i].device == device) {
1068	return pci_ids[i].chipname;
1069	}
1070
1071	}
1072
1073	return s_generic;
1074	}
1075
1076	/******************************************************************************
1077	* Return textual version of a resource manager error
1078	*/
1079	static char *rmerr(APIRET ret)
1080	{
1081	switch (ret) {
1082	case RMRC_SUCCESS:
1083	return("RMRC_SUCCESS");
1084	case RMRC_NOTINITIALIZED:
1085	return("RMRC_NOTINITIALIZED");
1086	case RMRC_BAD_DRIVERHANDLE:
1087	return("RMRC_BAD_DRIVERHANDLE");
1088	case RMRC_BAD_ADAPTERHANDLE:
1089	return("RMRC_BAD_ADAPTERHANDLE");
1090	case RMRC_BAD_DEVICEHANDLE:
1091	return("RMRC_BAD_DEVICEHANDLE");
1092	case RMRC_BAD_RESOURCEHANDLE:
1093	return("RMRC_BAD_RESOURCEHANDLE");
1094	case RMRC_BAD_LDEVHANDLE:
1095	return("RMRC_BAD_LDEVHANDLE");
1096	case RMRC_BAD_SYSNAMEHANDLE:
1097	return("RMRC_BAD_SYSNAMEHANDLE");
1098	case RMRC_BAD_DEVHELP:
1099	return("RMRC_BAD_DEVHELP");
1100	case RMRC_NULL_POINTER:
1101	return("RMRC_NULL_POINTER");
1102	case RMRC_NULL_STRINGS:
1103	return("RMRC_NULL_STRINGS");
1104	case RMRC_BAD_VERSION:
1105	return("RMRC_BAD_VERSION");
1106	case RMRC_RES_ALREADY_CLAIMED:
1107	return("RMRC_RES_ALREADY_CLAIMED");
1108	case RMRC_DEV_ALREADY_CLAIMED:
1109	return("RMRC_DEV_ALREADY_CLAIMED");
1110	case RMRC_INVALID_PARM_VALUE:
1111	return("RMRC_INVALID_PARM_VALUE");
1112	case RMRC_OUT_OF_MEMORY:
1113	return("RMRC_OUT_OF_MEMORY");
1114	case RMRC_SEARCH_FAILED:
1115	return("RMRC_SEARCH_FAILED");
1116	case RMRC_BUFFER_TOO_SMALL:
1117	return("RMRC_BUFFER_TOO_SMALL");
1118	case RMRC_GENERAL_FAILURE:
1119	return("RMRC_GENERAL_FAILURE");
1120	case RMRC_IRQ_ENTRY_ILLEGAL:
1121	return("RMRC_IRQ_ENTRY_ILLEGAL");
1122	case RMRC_NOT_IMPLEMENTED:
1123	return("RMRC_NOT_IMPLEMENTED");
1124	case RMRC_NOT_INSTALLED:
1125	return("RMRC_NOT_INSTALLED");
1126	case RMRC_BAD_DETECTHANDLE:
1127	return("RMRC_BAD_DETECTHANDLE");
1128	case RMRC_BAD_RMHANDLE:
1129	return("RMRC_BAD_RMHANDLE");
1130	case RMRC_BAD_FLAGS:
1131	return("RMRC_BAD_FLAGS");
1132	case RMRC_NO_DETECTED_DATA:
1133	return("RMRC_NO_DETECTED_DATA");
1134	default:
1135	return("RMRC_UNKOWN");
1136	}
1137	}

Note: See TracBrowser for help on using the repository browser.

Download in other formats: