source: trunk/src/os2ahci/pci.c@ 122

Last change on this file since 122 was 122, checked in by Markus Thielen, 14 years ago
  • added support for /q switch (#7)
  • added cv#printf macros to support verbosity setting from command line
File size: 43.5 KB
Line 
1/******************************************************************************
2 * PCI.c - PCI constants and detection code for os2ahci driver
3 *
4 * Copyright (c) 2011 thi.guten Software Development
5 * Copyright (c) 2011 Mensys B.V.
6 *
7 * Authors: Christian Mueller, Markus Thielen
8 *
9 * Parts copied from/inspired by the Linux AHCI driver;
10 * those parts are (c) Linux AHCI/ATA maintainers
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */
26
27#include "os2ahci.h"
28
29/* -------------------------- macros and constants ------------------------- */
30
31/* offset of PCI base address register (BAR) in the PCI config space */
32#define PCI_BAR(reg) (UCHAR) (0x10 + (reg) * sizeof(u32))
33
34/******************************************************************************
35 * OEMHLP constants for PCI access
36 */
37#define GENERIC_IOCTL 0x10
38#define OH_CATEGORY 0x00
39#define OH_FUNC_PCI 0x0b
40
41/* subfunctions */
42#define OH_BIOS_INFO 0x00
43#define OH_FIND_DEVICE 0x01
44#define OH_FIND_CLASS 0x02
45#define OH_READ_CONFIG 0x03
46#define OH_WRITE_CONFIG 0x04
47
48/* return codes */
49#define OH_SUCCESS 0x00
50#define OH_NOT_SUPPORTED 0x81
51#define OH_BAD_VENDOR 0x83
52#define OH_NOT_FOUND 0x86
53#define OH_BAD_REGISTER 0x87
54
55/* ------------------------ typedefs and structures ------------------------ */
56
57/******************************************************************************
58 * OEMHLP IOCtl parameter union. The parameter area is generally used as input
59 * to the OEMHLP IOCtl calls.
60 */
61typedef union {
62
63 /* query PCI BIOS information" */
64 struct {
65 UCHAR subfunction;
66 } bios_info;
67
68 /* find PCI device */
69 struct {
70 UCHAR subfunction;
71 USHORT device;
72 USHORT vendor;
73 UCHAR index;
74 } find_device;
75
76 /* find PCI class code */
77 struct {
78 UCHAR subfunction;
79 ULONG class;
80 UCHAR index;
81 } find_class;
82
83 /* read PCI configuration space */
84 struct {
85 UCHAR subfunction;
86 UCHAR bus;
87 UCHAR dev_func;
88 UCHAR reg;
89 UCHAR size;
90 } read_config;
91
92 /* write PCI configuration space */
93 struct {
94 UCHAR subfunction;
95 UCHAR bus;
96 UCHAR dev_func;
97 UCHAR reg;
98 UCHAR size;
99 ULONG data;
100 } write_config;
101
102} OH_PARM;
103
104/******************************************************************************
105 * OEMHLP IOCtl data union. The data area is generally used as output from the
106 * OEMHLP IOCtl calls.
107 */
108typedef union {
109
110 /* query PCI BIOS information" */
111 struct {
112 UCHAR rc;
113 UCHAR hw_mech;
114 UCHAR major_version;
115 UCHAR minor_version;
116 UCHAR last_bus;
117 } bios_info;
118
119 /* find PCI device */
120 struct {
121 UCHAR rc;
122 UCHAR bus;
123 UCHAR dev_func;
124 } find_device;
125
126 /* find PCI class code */
127 struct {
128 UCHAR rc;
129 UCHAR bus;
130 UCHAR dev_func;
131 } find_class;
132
133 /* read PCI confguration space */
134 struct {
135 UCHAR rc;
136 ULONG data;
137 } read_config;
138
139 /* write PCI confguration space */
140 struct {
141 UCHAR rc;
142 } write_config;
143
144} OH_DATA;
145
146/* -------------------------- function prototypes -------------------------- */
147
148static void add_pci_device (PCI_ID *pci_id, OH_DATA _far *data);
149static UCHAR pci_read_conf (UCHAR bus, UCHAR dev_func, UCHAR indx,
150 UCHAR size, ULONG _far *val);
151static UCHAR pci_write_conf (UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
152 ULONG val);
153static int oemhlp_call (UCHAR subfunction, OH_PARM _far *parm,
154 OH_DATA _far *data);
155static long bar_resource (UCHAR bus, UCHAR dev_func,
156 RESOURCESTRUCT _far *resource, int i);
157static char *rmerr (APIRET ret);
158
159/* ------------------------ global/static variables ------------------------ */
160
161/******************************************************************************
162 * chipset/controller name strings
163 */
164static char chip_esb2[] = "ESB2";
165static char chip_ich8[] = "ICH8";
166static char chip_ich8m[] = "ICH8M";
167static char chip_ich9[] = "ICH9";
168static char chip_ich9m[] = "ICH9M";
169static char chip_ich10[] = "ICH10";
170static char chip_pchahci[] = "PCH AHCI";
171static char chip_pchraid[] = "PCH RAID";
172static char chip_tolapai[] = "Tolapai";
173static char chip_sb600[] = "SB600";
174static char chip_sb700[] = "SB700/800";
175static char chip_vt8251[] = "VT8251";
176static char chip_mcp65[] = "MCP65";
177static char chip_mcp67[] = "MCP67";
178static char chip_mcp73[] = "MCP73";
179static char chip_mcp77[] = "MCP77";
180static char chip_mcp79[] = "MCP79";
181static char chip_mcp89[] = "MCP689";
182static char chip_sis968[] = "968";
183
184static char s_generic[] = "Generic";
185
186
187
188/******************************************************************************
189 * PCI vendor and device IDs for known AHCI adapters. Copied from the Linux
190 * AHCI driver.
191 */
192
193PCI_ID pci_ids[] = {
194
195 /* Intel
196 * NOTE: ICH5 controller does NOT support AHCI, so we do
197 * not add it here! */
198 { PCI_VDEVICE(INTEL, 0x2652), board_ahci, "ICH6" }, /* ICH6 */
199 { PCI_VDEVICE(INTEL, 0x2653), board_ahci, "ICH6M" }, /* ICH6M */
200 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci, "ICH7" }, /* ICH7 */
201 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci, "ICH7M" }, /* ICH7M */
202 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci, "ICH7R" }, /* ICH7R */
203 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr, "ULiM5288" }, /* ULi M5288 */
204 { PCI_VDEVICE(INTEL, 0x2681), board_ahci, chip_esb2 }, /* ESB2 */
205 { PCI_VDEVICE(INTEL, 0x2682), board_ahci, chip_esb2 }, /* ESB2 */
206 { PCI_VDEVICE(INTEL, 0x2683), board_ahci, chip_esb2 }, /* ESB2 */
207 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci, "ICH7MDH" }, /* ICH7-M DH */
208 { PCI_VDEVICE(INTEL, 0x2821), board_ahci, chip_ich8 }, /* ICH8 */
209 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf, chip_ich8 }, /* ICH8 */
210 { PCI_VDEVICE(INTEL, 0x2824), board_ahci, chip_ich8 }, /* ICH8 */
211 { PCI_VDEVICE(INTEL, 0x2829), board_ahci, chip_ich8m }, /* ICH8M */
212 { PCI_VDEVICE(INTEL, 0x282a), board_ahci, chip_ich8m }, /* ICH8M */
213 { PCI_VDEVICE(INTEL, 0x2922), board_ahci, chip_ich9 }, /* ICH9 */
214 { PCI_VDEVICE(INTEL, 0x2923), board_ahci, chip_ich9 }, /* ICH9 */
215 { PCI_VDEVICE(INTEL, 0x2924), board_ahci, chip_ich9 }, /* ICH9 */
216 { PCI_VDEVICE(INTEL, 0x2925), board_ahci, chip_ich9 }, /* ICH9 */
217 { PCI_VDEVICE(INTEL, 0x2927), board_ahci, chip_ich9 }, /* ICH9 */
218 { PCI_VDEVICE(INTEL, 0x2929), board_ahci, chip_ich9m }, /* ICH9M */
219 { PCI_VDEVICE(INTEL, 0x292a), board_ahci, chip_ich9m }, /* ICH9M */
220 { PCI_VDEVICE(INTEL, 0x292b), board_ahci, chip_ich9m }, /* ICH9M */
221 { PCI_VDEVICE(INTEL, 0x292c), board_ahci, chip_ich9m }, /* ICH9M */
222 { PCI_VDEVICE(INTEL, 0x292f), board_ahci, chip_ich9m }, /* ICH9M */
223 { PCI_VDEVICE(INTEL, 0x294d), board_ahci, chip_ich9 }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x294e), board_ahci, chip_ich9m }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x502a), board_ahci, chip_tolapai }, /* Tolapai */
226 { PCI_VDEVICE(INTEL, 0x502b), board_ahci, chip_tolapai }, /* Tolapai */
227 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci, chip_ich10 }, /* ICH10 */
228 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci, chip_ich10 }, /* ICH10 */
229 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci, chip_ich10 }, /* ICH10 */
230 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci, chip_pchahci }, /* PCH AHCI */
231 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci, chip_pchahci }, /* PCH AHCI */
232 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci, chip_pchraid }, /* PCH RAID */
233 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci, chip_pchraid }, /* PCH RAID */
234 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci, chip_pchahci }, /* PCH AHCI */
235 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci, chip_pchraid }, /* PCH RAID */
236 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci, chip_pchraid }, /* PCH RAID */
237 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci, chip_pchahci }, /* PCH AHCI */
238
239 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
240 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
241 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffffL, board_ahci_ign_iferr, "360" },
242
243 /* ATI */
244 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600, chip_sb600 }, /* ATI SB600 */
245 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
246 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
247 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
248 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
249 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
250 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
251
252 /* AMD */
253 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
254 /* AMD is using RAID class only for ahci controllers */
255 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
256 PCI_CLASS_STORAGE_RAID << 8, 0xffffffL, board_ahci, "Hudson2" },
257
258 /* VIA */
259 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251, chip_vt8251 }, /* VIA VT8251 */
260 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251, chip_vt8251 }, /* VIA VT8251 */
261
262 /* NVIDIA */
263 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
264 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
265 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
266 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
267 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
268 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
269 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
270 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
271 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
272 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
273 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
274 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
275 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
276 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
277 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
278 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
279 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
280 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
281 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
282 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
283 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq, chip_mcp67 }, /* Linux ID */
284 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
285 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
286 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
287 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
288 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
289 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
290 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
291 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
292 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
293 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
294 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
295 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
296 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci, chip_mcp77 }, /* MCP77 */
297 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci, chip_mcp77 }, /* MCP77 */
298 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci, chip_mcp77 }, /* MCP77 */
299 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci, chip_mcp77 }, /* MCP77 */
300 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci, chip_mcp77 }, /* MCP77 */
301 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci, chip_mcp77 }, /* MCP77 */
302 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci, chip_mcp77 }, /* MCP77 */
303 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci, chip_mcp77 }, /* MCP77 */
304 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci, chip_mcp77 }, /* MCP77 */
305 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci, chip_mcp77 }, /* MCP77 */
306 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci, chip_mcp77 }, /* MCP77 */
307 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci, chip_mcp77 }, /* MCP77 */
308 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci, chip_mcp79 }, /* MCP79 */
309 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci, chip_mcp79 }, /* MCP79 */
310 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci, chip_mcp79 }, /* MCP79 */
311 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci, chip_mcp79 }, /* MCP79 */
312 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci, chip_mcp79 }, /* MCP79 */
313 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci, chip_mcp79 }, /* MCP79 */
314 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci, chip_mcp79 }, /* MCP79 */
315 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci, chip_mcp79 }, /* MCP79 */
316 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci, chip_mcp79 }, /* MCP79 */
317 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci, chip_mcp79 }, /* MCP79 */
318 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci, chip_mcp79 }, /* MCP79 */
319 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci, chip_mcp79 }, /* MCP79 */
320 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci, chip_mcp89 }, /* MCP89 */
321 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci, chip_mcp89 }, /* MCP89 */
322 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci, chip_mcp89 }, /* MCP89 */
323 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci, chip_mcp89 }, /* MCP89 */
324 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci, chip_mcp89 }, /* MCP89 */
325 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci, chip_mcp89 }, /* MCP89 */
326 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci, chip_mcp89 }, /* MCP89 */
327 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci, chip_mcp89 }, /* MCP89 */
328 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci, chip_mcp89 }, /* MCP89 */
329 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci, chip_mcp89 }, /* MCP89 */
330 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci, chip_mcp89 }, /* MCP89 */
331 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci, chip_mcp89 }, /* MCP89 */
332
333 /* SiS */
334 { PCI_VDEVICE(SI, 0x1184), board_ahci, "966" }, /* SiS 966 */
335 { PCI_VDEVICE(SI, 0x1185), board_ahci, chip_sis968 }, /* SiS 968 */
336 { PCI_VDEVICE(SI, 0x0186), board_ahci, chip_sis968 }, /* SiS 968 */
337
338 /* Marvell */
339 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv, "6145" }, /* 6145 */
340 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv, "6121" }, /* 6121 */
341
342 /* Promise */
343 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci, "PDC42819" }, /* PDC42819 */
344
345 /* Generic, PCI class code for AHCI */
346 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
347 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffffL, board_ahci, s_generic },
348
349 /* end of list, including a few slots to define custom adapters (10) */
350 { 0, 0, 0, 0, 0, 0, 0, NULL },
351 { 0, 0, 0, 0, 0, 0, 0, NULL },
352 { 0, 0, 0, 0, 0, 0, 0, NULL },
353 { 0, 0, 0, 0, 0, 0, 0, NULL },
354 { 0, 0, 0, 0, 0, 0, 0, NULL },
355 { 0, 0, 0, 0, 0, 0, 0, NULL },
356 { 0, 0, 0, 0, 0, 0, 0, NULL },
357 { 0, 0, 0, 0, 0, 0, 0, NULL },
358 { 0, 0, 0, 0, 0, 0, 0, NULL },
359 { 0, 0, 0, 0, 0, 0, 0, NULL },
360
361 { 0, 0, 0, 0, 0, 0, 0, NULL }
362};
363
364/******************************************************************************
365 * OEMHLP$ is used by OS/2 to provide access to OEM-specific machine resources
366 * like PCI BIOS access. We're using this to enumerate the PCI bus. Due to
367 * BIOS bugs, it may be necessary to use I/O operations for this purpose but
368 * so far I think this is only relevant for rather old PCs and SATA is not
369 * expected to be a priority on those machines.
370 */
371static IDCTABLE oemhlp; /* OEMHLP$ IDC entry point */
372
373/* ----------------------------- start of code ----------------------------- */
374
375/******************************************************************************
376 * Add specified PCI vendor and device ID to the list of supported AHCI
377 * controllers. Please note that the last slot in pci_ids needs to remain
378 * empty because it's used as end marker.
379 */
380int add_pci_id(u16 vendor, u16 device)
381{
382 int max_slot = sizeof(pci_ids) / sizeof(*pci_ids) - 2;
383 int i;
384
385 /* search for last used slot in 'pci_ids' */
386 for (i = max_slot; i >= 0 && pci_ids[i].vendor == 0; i--);
387 if (i >= max_slot) {
388 /* all slots in use */
389 return(-1);
390 }
391
392 /* use slot after the last used slot */
393 i++;
394 pci_ids[i].vendor = vendor;
395 pci_ids[i].device = device;
396 pci_ids[i].board = board_ahci;
397 pci_ids[i].chipname = s_generic;
398 return(0);
399}
400
401/******************************************************************************
402 * Scan PCI bus using OEMHLP$ IOCTLs and build adapter list.
403 */
404void scan_pci_bus(void)
405{
406 OH_PARM parm;
407 OH_DATA data;
408 UCHAR index;
409 UCHAR rc;
410 int ad_indx = 0;
411 int i;
412 int n;
413
414 ddprintf("scanning PCI bus...\n");
415
416 /* verify that we have a PCI system */
417 memset(&parm, 0x00, sizeof(parm));
418 if (oemhlp_call(OH_BIOS_INFO, &parm, &data) != OH_SUCCESS) {
419 cprintf("%s: couldn't get PCI BIOS information\n", drv_name);
420 return;
421 }
422
423 /* Go through the list of PCI IDs and search for each device
424 *
425 * NOTES:
426 *
427 * - When searching via class code, the OEMHLP$ interface doesn't allow
428 * setting a bitmask to look for individual portions of class code,
429 * subclass code and programming interface. However, all bitmasks in the
430 * PCI list currently use 0xffffff, thus this should not be a problem at
431 * this point in time.
432 *
433 * - Scanning via OEMHLP$ seems rather slow, at least in the virtual
434 * machine I'm currenly using to test this driver. Thus, class code
435 * scans are preferred unless the option "-t" (thorough_scan) has been
436 * specified. The assumption is that most, if not all, modern AHCI
437 * adapters have the correct class code (PCI_CLASS_STORAGE_SATA_AHCI).
438 */
439 for (i = 0; pci_ids[i].vendor != 0; i++) {
440 index = 0;
441 do {
442 if (pci_ids[i].device == PCI_ANY_ID || pci_ids[i].vendor == PCI_ANY_ID) {
443 /* look for class code */
444 memset(&parm, 0x00, sizeof(parm));
445 parm.find_class.class = pci_ids[i].class;
446 parm.find_class.index = index;
447 rc = oemhlp_call(OH_FIND_CLASS, &parm, &data);
448
449 } else if (thorough_scan) {
450 /* look for this specific vendor and device ID */
451 memset(&parm, 0x00, sizeof(parm));
452 parm.find_device.device = pci_ids[i].device;
453 parm.find_device.vendor = pci_ids[i].vendor;
454 parm.find_device.index = index;
455 rc = oemhlp_call(OH_FIND_DEVICE, &parm, &data);
456
457 } else {
458 rc = OH_NOT_FOUND;
459 }
460
461 if (rc == OH_SUCCESS) {
462 /* found a device */
463 int already_found = 0;
464
465 /* increment index for next loop */
466 if (++index > 180) {
467 /* something's wrong here... */
468 return;
469 }
470
471 /* check whether we already found this device */
472 for (n = 0; n < ad_info_cnt; n++) {
473 if (ad_infos[n].bus == data.find_device.bus &&
474 ad_infos[n].dev_func == data.find_device.dev_func) {
475 /* this device has already been found (e.g. via thorough scan) */
476 already_found = 1;
477 break;
478 }
479 }
480
481 if (already_found || (ad_ignore & (1U << ad_indx++))) {
482 /* ignore this device; it has either already been found via a
483 * thorough scan or has been specified to be ignored via command
484 * line option */
485 continue;
486 }
487
488 /* add this PCI device to ad_infos[] */
489 add_pci_device(pci_ids + i, &data);
490 }
491
492 } while (rc == OH_SUCCESS);
493 }
494}
495
496/******************************************************************************
497 * Enable interrupt generation. PCI 2.3 added a bit which allows disabling
498 * interrupt generation for a device. This function clears the corresponding
499 * bit in the configuration space command register.
500 */
501int pci_enable_int(UCHAR bus, UCHAR dev_func)
502{
503 ULONG tmp;
504
505 if (pci_read_conf (bus, dev_func, 4, sizeof(u32), &tmp) != OH_SUCCESS ||
506 pci_write_conf(bus, dev_func, 4, sizeof(u32), tmp & ~(1UL << 10)) != OH_SUCCESS) {
507 return(-1);
508 }
509 return(0);
510}
511
512/******************************************************************************
513 * Hack to set up proper IRQ mappings in the emulated PIIX3 ISA bridge in
514 * VirtualBox (for some reason, the first mapped IRQ is 0x80 without this
515 * hack).
516 */
517void pci_hack_virtualbox(void)
518{
519 ULONG irq = 0;
520
521 if (pci_read_conf(0, 0x08, 0x60, 1, &irq) == OH_SUCCESS && irq == 0x80) {
522 /* set IRQ for first device/func to 11 */
523 dprintf("hacking virtualbox PIIX3 PCI to ISA bridge IRQ mapping\n");
524 irq = ad_infos[0].irq;
525 pci_write_conf(0, 0x08, 0x60, 1, irq);
526 }
527}
528
529/******************************************************************************
530 * Add a single PCI device to the list of adapters.
531 */
532static void add_pci_device(PCI_ID *pci_id, OH_DATA _far *data)
533{
534 char rc_list_buf[sizeof(AHRESOURCE) + sizeof(HRESOURCE) * 15];
535 AHRESOURCE _far *rc_list = (AHRESOURCE _far *) rc_list_buf;
536 RESOURCESTRUCT resource;
537 ADAPTERSTRUCT adapter;
538 ADJUNCT adj;
539 AD_INFO *ad_info;
540 APIRET ret;
541 UCHAR bus = data->find_class.bus;
542 UCHAR dev_func = data->find_class.dev_func;
543 ULONG val;
544 SEL gdt[PORT_DMA_BUF_SEGS + 1];
545 char tmp[40];
546 u16 device;
547 u16 vendor;
548 u32 class;
549 int irq;
550 int pin;
551 int i;
552
553 /*****************************************************************************
554 * Part 1: Get further information about the device to be added; PCI ID...
555 */
556 if (pci_read_conf(bus, dev_func, 0x00, sizeof(ULONG), &val) != OH_SUCCESS) {
557 return;
558 }
559 device = (u16) (val >> 16);
560 vendor = (u16) (val & 0xffff);
561
562 /* ... and class code */
563 if (pci_read_conf(bus, dev_func, 0x08, sizeof(ULONG), &val) != OH_SUCCESS) {
564 return;
565 }
566 class = (u32) (val >> 8);
567
568 if (pci_id->device == PCI_ANY_ID) {
569 /* We found this device in a wildcard search. There are two possible
570 * reasons which require a different handling:
571 *
572 * 1) This device uses a non-standard PCI class and has been identified
573 * with the corresponding class in pci_ids[] (e.g. the entry
574 * PCI_VENDOR_ID_JMICRON), but there is a vendor ID in pci_ids[]. In
575 * this case, we need to verify that the vendor is correct (see
576 * comments regarding OEMHLP limitations in 'scan_pci_bus()')
577 *
578 * 2) This device was identified using a generic PCI class for AHCI
579 * adapters such as PCI_CLASS_STORAGE_SATA_AHCI and we need to map
580 * the device and vendor ID to the corresponding index in pci_ids[]
581 * if there is such an entry; the index passed to this function will
582 * be the generic class-based index which is fine as long as there's
583 * not special treatment required as indicated by the board_*
584 * constants in pci_ids[]...
585 *
586 * The main reason for this kludge is that it seems as if OEMHLP$
587 * is rather slow searching for PCI devices, adding around 30s
588 * to the boot time when scanning for individual AHCI PCI IDs. Thus,
589 * the OS2AHCI driver avoids this kind of scan in favor of a class-
590 * based scan (unless overridden with the "/T" option).
591 */
592 if (pci_id->vendor != PCI_ANY_ID) {
593 /* case 1: the vendor is known but we found the PCI device using a class
594 * search; verify vendor matches the one in pci_ids[]
595 */
596 if (pci_id->vendor != vendor) {
597 /* vendor doesn't match */
598 return;
599 }
600
601 } else {
602 /* case 2: we found this device using a generic class search; if the
603 * device/vendor is listed in pci_ids[], use this entry in favor of the
604 * one passed in 'pci_id'
605 */
606 for (i = 0; pci_ids[i].vendor != 0; i++) {
607 if (pci_ids[i].device == device && pci_ids[i].vendor == vendor) {
608 pci_id = pci_ids + i;
609 break;
610 }
611 }
612 }
613 }
614
615 /* found a supported AHCI device */
616 cvvprintf("found AHCI device: %s %s (%04x:%04x)\n"
617 " class:0x%06lx bus:%d devfunc:0x%02x\n",
618 vendor_from_id(vendor), device_from_id(device),
619 vendor, device,
620 class, bus, dev_func);
621
622 /* make sure we got room in the adapter information array */
623 if (ad_info_cnt >= MAX_AD - 1) {
624 cprintf("%s: too many AHCI devices\n", drv_name);
625 return;
626 }
627
628 /****************************************************************************
629 * Part 2: Determine resource requirements and allocate resources with the
630 * OS/2 resource manager. While doing so, some of the entries of the
631 * corresponding slot in the AD_INFO array, namely resource manager
632 * handles, are initialized so we need prepare the slot.
633 *
634 * NOTE: While registering resources with the resource manager, each new
635 * resource is added to the corresponding rc_list.hResource[] slot.
636 * rc_list is used further down to associate resources to adapters
637 * when the adapter itself is registered with the OS/2 resource
638 * manager.
639 */
640 ad_info = ad_infos + ad_info_cnt;
641 memset(ad_info, 0x00, sizeof(*ad_info));
642 rc_list->NumResource = 0;
643
644 /* Register IRQ with resource manager
645 *
646 * NOTE: We rely on the IRQ number saved in the PCI config space by the PCI
647 * BIOS. There's no reliable way to find out the IRQ number in any
648 * other way unless we start using message-driven interrupts (which
649 * is out of scope for the time being).
650 */
651 if (pci_read_conf(bus, dev_func, 0x3c, sizeof(u32), &val) != OH_SUCCESS) {
652 return;
653 }
654 irq = (int) (val & 0xff);
655 pin = (int) ((val >> 8) & 0xff);
656
657 memset(&resource, 0x00, sizeof(resource));
658 resource.ResourceType = RS_TYPE_IRQ;
659 resource.IRQResource.IRQLevel = irq;
660 resource.IRQResource.PCIIrqPin = pin;
661 resource.IRQResource.IRQFlags = RS_IRQ_SHARED;
662
663 ret = RMAllocResource(rm_drvh, &ad_info->rm_irq, &resource);
664 if (ret != RMRC_SUCCESS) {
665 cprintf("%s: couldn't register IRQ %d (rc = %s)\n", drv_name, irq, rmerr(ret));
666 return;
667 }
668 rc_list->hResource[rc_list->NumResource++] = ad_info->rm_irq;
669
670 /* Allocate all I/O and MMIO addresses offered by this device. In theory,
671 * we need only BAR #5, the AHCI MMIO BAR, but in order to prevent any
672 * other driver from hijacking our device and accessing it via legacy
673 * registers we'll reserve anything we can find.
674 */
675 for (i = 0; i < sizeof(ad_info->rm_bars) / sizeof(*ad_info->rm_bars); i++) {
676 long len = bar_resource(bus, dev_func, &resource, i);
677
678 if (len < 0) {
679 /* something went wrong */
680 goto add_pci_fail;
681 }
682 if (len == 0) {
683 /* this BAR is unused */
684 continue;
685 }
686
687 if (i == AHCI_PCI_BAR) {
688 if (resource.ResourceType != RS_TYPE_MEM) {
689 cprintf("%s: BAR #5 must be an MMIO region\n", drv_name);
690 goto add_pci_fail;
691 }
692 /* save this BAR's address as MMIO address */
693 ad_info->mmio_phys = resource.MEMResource.MemBase;
694 ad_info->mmio_size = resource.MEMResource.MemSize;
695 }
696
697 /* register [MM]IO region with resource manager */
698 ret = RMAllocResource(rm_drvh, ad_info->rm_bars + i, &resource);
699 if (ret != RMRC_SUCCESS) {
700 cprintf("%s: couldn't register [MM]IO region (rc = %s)\n",
701 drv_name, rmerr(ret));
702 goto add_pci_fail;
703 }
704 rc_list->hResource[rc_list->NumResource++] = ad_info->rm_bars[i];
705 }
706
707 if (ad_info->mmio_phys == 0) {
708 cprintf("%s: couldn't determine MMIO base address\n", drv_name);
709 goto add_pci_fail;
710 }
711
712 /****************************************************************************
713 * Part 3: Fill in the remaining fields in the AD_INFO slot and allocate
714 * memory and GDT selectors for the adapter. Finally, register the adapter
715 * itself with the OS/2 resource manager
716 */
717 ad_info->pci = pci_ids + i;
718 ad_info->bus = bus;
719 ad_info->dev_func = dev_func;
720 ad_info->irq = irq;
721
722 /* allocate memory for port-specific DMA scratch buffers */
723 if (DevHelp_AllocPhys((long) AHCI_PORT_PRIV_DMA_SZ * AHCI_MAX_PORTS,
724 MEMTYPE_ABOVE_1M, &ad_info->dma_buf_phys) != 0) {
725 cprintf("%s: couldn't allocate DMA scratch buffers for AHCI ports\n", drv_name);
726 ad_info->dma_buf_phys = 0;
727 goto add_pci_fail;
728 }
729
730 /* allocate GDT selectors for memory-mapped I/O and DMA scratch buffers */
731 if (DevHelp_AllocGDTSelector(gdt, PORT_DMA_BUF_SEGS + 1) != 0) {
732 cprintf("%s: couldn't allocate GDT selectors\n", drv_name);
733 memset(gdt, 0x00, sizeof(gdt));
734 goto add_pci_fail;
735 }
736
737 /* map MMIO address to first GDT selector */
738 if (DevHelp_PhysToGDTSelector(ad_info->mmio_phys,
739 (USHORT) ad_info->mmio_size, gdt[0]) != 0) {
740 cprintf("%s: couldn't map MMIO address to GDT selector\n", drv_name);
741 goto add_pci_fail;
742 }
743
744 /* map DMA scratch buffers to remaining GDT selectors */
745 for (i = 0; i < PORT_DMA_BUF_SEGS; i++) {
746 ULONG addr = ad_info->dma_buf_phys + i * PORT_DMA_SEG_SIZE;
747 USHORT len = AHCI_PORT_PRIV_DMA_SZ * PORT_DMA_BUFS_PER_SEG;
748
749 if (DevHelp_PhysToGDTSelector(addr, len, gdt[i+1]) != 0) {
750 cprintf("%s: couldn't map DMA scratch buffer to GDT selector\n", drv_name);
751 goto add_pci_fail;
752 }
753 }
754
755 /* fill in MMIO and DMA scratch buffer addresses in adapter info */
756 ad_info->mmio = (u8 _far *) ((u32) gdt[0] << 16);
757 for (i = 0; i < PORT_DMA_BUF_SEGS; i++) {
758 ad_info->dma_buf[i] = (u8 _far *) ((u32) gdt[i+1] << 16);
759 }
760
761 /* register adapter with resource manager */
762 memset(&adj, 0x00, sizeof(adj));
763 adj.pNextAdj = NULL;
764 adj.AdjLength = sizeof(adj);
765 adj.AdjType = ADJ_ADAPTER_NUMBER;
766 adj.Adapter_Number = ad_info_cnt;
767
768 memset(&adapter, 0x00, sizeof(adapter));
769 sprintf(tmp, "AHCI_%d Controller", ad_info_cnt);
770 adapter.AdaptDescriptName = tmp;
771 adapter.AdaptFlags = 0;
772 adapter.BaseType = AS_BASE_MSD;
773 adapter.SubType = AS_SUB_IDE;
774 adapter.InterfaceType = AS_INTF_GENERIC;
775 adapter.HostBusType = AS_HOSTBUS_PCI;
776 adapter.HostBusWidth = AS_BUSWIDTH_32BIT;
777 adapter.pAdjunctList = &adj;
778
779 ret = RMCreateAdapter(rm_drvh, &ad_info->rm_adh, &adapter, NULL, rc_list);
780 if (ret != RMRC_SUCCESS) {
781 cprintf("%s: couldn't register adapter (rc = %s)\n", drv_name, rmerr(ret));
782 goto add_pci_fail;
783 }
784
785 /* Successfully added the adapter and reserved its resources; the adapter
786 * is still under BIOS control so we're not going to do anything else at
787 * this point.
788 */
789 ad_info_cnt++;
790 return;
791
792add_pci_fail:
793 /* something went wrong; try to clean up as far as possible */
794 for (i = 0; i < sizeof(ad_info->rm_bars) / sizeof(*ad_info->rm_bars); i++) {
795 if (ad_info->rm_bars[i] != 0) {
796 RMDeallocResource(rm_drvh, ad_info->rm_bars[i]);
797 }
798 }
799 if (ad_info->rm_irq != 0) {
800 RMDeallocResource(rm_drvh, ad_info->rm_irq);
801 }
802 for (i = 0; i < sizeof(gdt) / sizeof(*gdt); i++) {
803 if (gdt[i] != 0) {
804 DevHelp_FreeGDTSelector(gdt[i]);
805 }
806 }
807 if (ad_info->dma_buf_phys != 0) {
808 DevHelp_FreePhys(ad_info->dma_buf_phys);
809 }
810}
811
812/******************************************************************************
813 * Read PCI configuration space register
814 */
815static UCHAR pci_read_conf(UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
816 ULONG _far *val)
817{
818 OH_PARM parm;
819 OH_DATA data;
820 UCHAR rc;
821
822 memset(&parm, 0x00, sizeof(parm));
823 parm.read_config.bus = bus;
824 parm.read_config.dev_func = dev_func;
825 parm.read_config.reg = indx;
826 parm.read_config.size = size;
827 if ((rc = oemhlp_call(OH_READ_CONFIG, &parm, &data) != OH_SUCCESS)) {
828 cprintf("%s: couldn't read config space (bus = %d, dev_func = 0x%02x, indx = 0x%02x, rc = %d)\n",
829 drv_name, bus, dev_func, indx, rc);
830 return(rc);
831 }
832
833 *val = data.read_config.data;
834 return(OH_SUCCESS);
835}
836
837/******************************************************************************
838 * Write PCI configuration space register
839 */
840static UCHAR pci_write_conf(UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
841 ULONG val)
842{
843 OH_PARM parm;
844 OH_DATA data;
845 UCHAR rc;
846
847 memset(&parm, 0x00, sizeof(parm));
848 parm.write_config.bus = bus;
849 parm.write_config.dev_func = dev_func;
850 parm.write_config.reg = indx;
851 parm.write_config.size = size;
852 parm.write_config.data = val;
853
854 if ((rc = oemhlp_call(OH_WRITE_CONFIG, &parm, &data) != OH_SUCCESS)) {
855 cprintf("%s: couldn't write config space (bus = %d, dev_func = 0x%02x, indx = 0x%02x, rc = %d)\n",
856 drv_name, bus, dev_func, indx, rc);
857 return(rc);
858 }
859
860 return(OH_SUCCESS);
861}
862/******************************************************************************
863 * Call OEMHLP$ IDC entry point with the specified IOCtl parameter and data
864 * packets.
865 */
866static int oemhlp_call(UCHAR subfunction, OH_PARM _far *parm,
867 OH_DATA _far *data)
868{
869 void (_far *func)(void);
870 RP_GENIOCTL ioctl;
871 unsigned short prot_idc_ds;
872
873 if (oemhlp.ProtIDCEntry == NULL || oemhlp.ProtIDC_DS == 0) {
874 /* attach to OEMHLP$ device driver */
875 if (DevHelp_AttachDD("OEMHLP$ ", (NPBYTE) &oemhlp) ||
876 oemhlp.ProtIDCEntry == NULL ||
877 oemhlp.ProtIDC_DS == 0) {
878 cprintf("%s: couldn't attach to OEMHLP$\n", drv_name);
879 return(OH_NOT_SUPPORTED);
880 }
881 }
882
883 /* store subfuntion in first byte of pararameter packet */
884 parm->bios_info.subfunction = subfunction;
885 memset(data, 0x00, sizeof(*data));
886
887 /* assemble IOCtl request */
888 memset(&ioctl, 0x00, sizeof(ioctl));
889 ioctl.rph.Len = sizeof(ioctl);
890 ioctl.rph.Unit = 0;
891 ioctl.rph.Cmd = GENERIC_IOCTL;
892 ioctl.rph.Status = 0;
893
894 ioctl.Category = OH_CATEGORY;
895 ioctl.Function = OH_FUNC_PCI;
896 ioctl.ParmPacket = (PUCHAR) parm;
897 ioctl.DataPacket = (PUCHAR) data;
898 ioctl.ParmLen = sizeof(*parm);
899 ioctl.DataLen = sizeof(*data);
900
901 /* Call OEMHLP's IDC routine. Before doing so, we need to assign the address
902 * to be called to a stack variable because the inter-device driver calling
903 * convention forces us to set DS to the device driver's data segment and ES
904 * to the segment of the request packet.
905 */
906 func = oemhlp.ProtIDCEntry;
907
908 /* The WATCOM compiler does not support struct references in inline
909 * assembler code, so we pass it in a stack variable
910 */
911 prot_idc_ds = oemhlp.ProtIDC_DS;
912
913 _asm {
914 push ds;
915 push es;
916 push bx;
917 push si;
918 push di;
919
920 push ss
921 pop es
922 lea bx, ioctl;
923 mov ds, prot_idc_ds;
924 call dword ptr [func];
925
926 pop di;
927 pop si;
928 pop bx;
929 pop es;
930 pop ds;
931 }
932
933 dddphex(parm, sizeof(*parm), "oemhlp_parm: ");
934 dddphex(data, sizeof(*data), "oemhlp_data: ");
935
936 if (ioctl.rph.Status & STERR) {
937 return(OH_NOT_SUPPORTED);
938 }
939 return(data->bios_info.rc);
940}
941
942/******************************************************************************
943 * Prepare a resource structure for a PCI Base Address Register (BAR). This
944 * basically means the type, address and range of the I/O address space. It
945 * returns the length of the address range as a signed long to allow the caller
946 * to differentiate between error conditions (< 0), unused BARs (0) or valid
947 * bars (> 0).
948 *
949 * NOTE: In order to do this, we need to temporarily write 0xffffffff to
950 * the MMIO base address register (BAR), read back the resulting value
951 * and check the 0 bits from the right end, masking the lower 2 (I/O) or
952 * 4 (MMIO) bits. After doing this, we must restore the original value
953 * set up by the BIOS.
954 *
955 * 31 4 3 2 1 0
956 * -------------------------------------------------------------------
957 * base address P T T I
958 * P = prefetchable
959 * T = type (0 = any 32 bit, 1 = <1M, 2 = 64 bit)
960 * I = I/O (1) or memory (0)
961 */
962static long bar_resource(UCHAR bus, UCHAR dev_func,
963 RESOURCESTRUCT _far *resource, int i)
964{
965 u32 bar_addr = 0;
966 u32 bar_size = 0;
967
968 /* temporarily write 1s to this BAR to determine the address range */
969 if (pci_read_conf (bus, dev_func, PCI_BAR(i), sizeof(u32), &bar_addr) != OH_SUCCESS ||
970 pci_write_conf(bus, dev_func, PCI_BAR(i), sizeof(u32), ~(0UL)) != OH_SUCCESS ||
971 pci_read_conf (bus, dev_func, PCI_BAR(i), sizeof(u32), &bar_size) != OH_SUCCESS ||
972 pci_write_conf(bus, dev_func, PCI_BAR(i), sizeof(u32), bar_addr) != OH_SUCCESS) {
973
974 cprintf("%s: couldn't determine [MM]IO size\n", drv_name);
975 if (bar_addr != 0) {
976 pci_write_conf(bus, dev_func, PCI_BAR(i), sizeof(u32), bar_addr);
977 }
978 return(-1);
979 }
980
981 if (bar_size == 0 || bar_size == 0xffffffffUL) {
982 /* bar not implemented or device not working properly */
983 return(0);
984 }
985
986 /* prepare resource allocation structure */
987 memset(resource, 0x00, sizeof(*resource));
988 if (bar_addr & 1) {
989 bar_size = ~(bar_size & 0xfffffffcUL) + 1;
990 bar_size &= 0xffffUL; /* I/O address space is 16 bits on x86 */
991 bar_addr &= 0xfffcUL;
992
993 resource->ResourceType = RS_TYPE_IO;
994 resource->IOResource.BaseIOPort = bar_addr;
995 resource->IOResource.NumIOPorts = bar_size;
996 resource->IOResource.IOFlags = RS_IO_EXCLUSIVE;
997 resource->IOResource.IOAddressLines = 16;
998
999 } else {
1000 bar_size = ~(bar_size & 0xfffffff0UL) + 1;
1001 bar_addr &= 0xfffffff0UL;
1002
1003 resource->ResourceType = RS_TYPE_MEM;
1004 resource->MEMResource.MemBase = bar_addr;
1005 resource->MEMResource.MemSize = bar_size;
1006 resource->MEMResource.MemFlags = RS_MEM_EXCLUSIVE;
1007 }
1008
1009 ddprintf("BAR #%d: type = %s, addr = 0x%08lx, size = %ld\n", i,
1010 (resource->ResourceType == RS_TYPE_IO) ? "I/O" : "MEM",
1011 bar_addr, bar_size);
1012
1013 return((long) bar_size);
1014}
1015
1016/******************************************************************************
1017 * return vendor name for PCI vendor ID
1018 */
1019char *vendor_from_id(u16 id)
1020{
1021
1022 switch(id) {
1023
1024 case PCI_VENDOR_ID_AL:
1025 return "Ali";
1026 case PCI_VENDOR_ID_AMD:
1027 case PCI_VENDOR_ID_ATI:
1028 return "AMD";
1029 case PCI_VENDOR_ID_AT:
1030 return "Allied Telesyn";
1031 case PCI_VENDOR_ID_ATT:
1032 return "ATT";
1033 case PCI_VENDOR_ID_CMD:
1034 return "CMD";
1035 case PCI_VENDOR_ID_CT:
1036 return "CT";
1037 case PCI_VENDOR_ID_INTEL:
1038 return "Intel";
1039 case PCI_VENDOR_ID_INITIO:
1040 return "Initio";
1041 case PCI_VENDOR_ID_JMICRON:
1042 return "JMicron";
1043 case PCI_VENDOR_ID_MARVELL:
1044 return "Marvell";
1045 case PCI_VENDOR_ID_NVIDIA:
1046 return "NVIDIA";
1047 case PCI_VENDOR_ID_PROMISE:
1048 return "PROMISE";
1049 case PCI_VENDOR_ID_SI:
1050 return "SiS";
1051 case PCI_VENDOR_ID_VIA:
1052 return "VIA";
1053 default:
1054 break;
1055 }
1056
1057 return "Generic";
1058
1059}
1060
1061/******************************************************************************
1062 * return a device name for a PCI device id
1063 * NOTE: this is as simple as can be, so don't call it twice in one statement.
1064 */
1065char *device_from_id(u16 device)
1066{
1067 int i;
1068
1069 for (i = 0; pci_ids[i].vendor != 0; i++) {
1070
1071 if (pci_ids[i].device == device) {
1072 return pci_ids[i].chipname;
1073 }
1074
1075 }
1076
1077 return s_generic;
1078}
1079
1080/******************************************************************************
1081 * Return textual version of a resource manager error
1082 */
1083static char *rmerr(APIRET ret)
1084{
1085 switch (ret) {
1086 case RMRC_SUCCESS:
1087 return("RMRC_SUCCESS");
1088 case RMRC_NOTINITIALIZED:
1089 return("RMRC_NOTINITIALIZED");
1090 case RMRC_BAD_DRIVERHANDLE:
1091 return("RMRC_BAD_DRIVERHANDLE");
1092 case RMRC_BAD_ADAPTERHANDLE:
1093 return("RMRC_BAD_ADAPTERHANDLE");
1094 case RMRC_BAD_DEVICEHANDLE:
1095 return("RMRC_BAD_DEVICEHANDLE");
1096 case RMRC_BAD_RESOURCEHANDLE:
1097 return("RMRC_BAD_RESOURCEHANDLE");
1098 case RMRC_BAD_LDEVHANDLE:
1099 return("RMRC_BAD_LDEVHANDLE");
1100 case RMRC_BAD_SYSNAMEHANDLE:
1101 return("RMRC_BAD_SYSNAMEHANDLE");
1102 case RMRC_BAD_DEVHELP:
1103 return("RMRC_BAD_DEVHELP");
1104 case RMRC_NULL_POINTER:
1105 return("RMRC_NULL_POINTER");
1106 case RMRC_NULL_STRINGS:
1107 return("RMRC_NULL_STRINGS");
1108 case RMRC_BAD_VERSION:
1109 return("RMRC_BAD_VERSION");
1110 case RMRC_RES_ALREADY_CLAIMED:
1111 return("RMRC_RES_ALREADY_CLAIMED");
1112 case RMRC_DEV_ALREADY_CLAIMED:
1113 return("RMRC_DEV_ALREADY_CLAIMED");
1114 case RMRC_INVALID_PARM_VALUE:
1115 return("RMRC_INVALID_PARM_VALUE");
1116 case RMRC_OUT_OF_MEMORY:
1117 return("RMRC_OUT_OF_MEMORY");
1118 case RMRC_SEARCH_FAILED:
1119 return("RMRC_SEARCH_FAILED");
1120 case RMRC_BUFFER_TOO_SMALL:
1121 return("RMRC_BUFFER_TOO_SMALL");
1122 case RMRC_GENERAL_FAILURE:
1123 return("RMRC_GENERAL_FAILURE");
1124 case RMRC_IRQ_ENTRY_ILLEGAL:
1125 return("RMRC_IRQ_ENTRY_ILLEGAL");
1126 case RMRC_NOT_IMPLEMENTED:
1127 return("RMRC_NOT_IMPLEMENTED");
1128 case RMRC_NOT_INSTALLED:
1129 return("RMRC_NOT_INSTALLED");
1130 case RMRC_BAD_DETECTHANDLE:
1131 return("RMRC_BAD_DETECTHANDLE");
1132 case RMRC_BAD_RMHANDLE:
1133 return("RMRC_BAD_RMHANDLE");
1134 case RMRC_BAD_FLAGS:
1135 return("RMRC_BAD_FLAGS");
1136 case RMRC_NO_DETECTED_DATA:
1137 return("RMRC_NO_DETECTED_DATA");
1138 default:
1139 return("RMRC_UNKOWN");
1140 }
1141}
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