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source: trunk/src/os2ahci/pci.c@ 108

Last change on this file since 108 was 108, checked in by Markus Thielen, 14 years ago
fix for #1
File size: 43.6 KB

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1	/******************************************************************************
2	* PCI.c - PCI constants and detection code for os2ahci driver
3	*
4	* Copyright (c) 2011 thi.guten Software Development
5	* Copyright (c) 2011 Mensys B.V.
6	*
7	* Authors: Christian Mueller, Markus Thielen
8	*
9	* Parts copied from/inspired by the Linux AHCI driver;
10	* those parts are (c) Linux AHCI/ATA maintainers
11	*
12	* This program is free software; you can redistribute it and/or modify
13	* it under the terms of the GNU General Public License as published by
14	* the Free Software Foundation; either version 2 of the License, or
15	* (at your option) any later version.
16	*
17	* This program is distributed in the hope that it will be useful,
18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20	* GNU General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, write to the Free Software
24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25	*/
26
27	#include "os2ahci.h"
28
29	/* -------------------------- macros and constants ------------------------- */
30
31	/* offset of PCI base address register (BAR) in the PCI config space */
32	#define PCI_BAR(reg) (UCHAR) (0x10 + (reg) * sizeof(u32))
33
34	/******************************************************************************
35	* OEMHLP constants for PCI access
36	*/
37	#define GENERIC_IOCTL 0x10
38	#define OH_CATEGORY 0x00
39	#define OH_FUNC_PCI 0x0b
40
41	/* subfunctions */
42	#define OH_BIOS_INFO 0x00
43	#define OH_FIND_DEVICE 0x01
44	#define OH_FIND_CLASS 0x02
45	#define OH_READ_CONFIG 0x03
46	#define OH_WRITE_CONFIG 0x04
47
48	/* return codes */
49	#define OH_SUCCESS 0x00
50	#define OH_NOT_SUPPORTED 0x81
51	#define OH_BAD_VENDOR 0x83
52	#define OH_NOT_FOUND 0x86
53	#define OH_BAD_REGISTER 0x87
54
55	/* ------------------------ typedefs and structures ------------------------ */
56
57	/******************************************************************************
58	* OEMHLP IOCtl parameter union. The parameter area is generally used as input
59	* to the OEMHLP IOCtl calls.
60	*/
61	typedef union {
62
63	/* query PCI BIOS information" */
64	struct {
65	UCHAR subfunction;
66	} bios_info;
67
68	/* find PCI device */
69	struct {
70	UCHAR subfunction;
71	USHORT device;
72	USHORT vendor;
73	UCHAR index;
74	} find_device;
75
76	/* find PCI class code */
77	struct {
78	UCHAR subfunction;
79	ULONG class;
80	UCHAR index;
81	} find_class;
82
83	/* read PCI configuration space */
84	struct {
85	UCHAR subfunction;
86	UCHAR bus;
87	UCHAR dev_func;
88	UCHAR reg;
89	UCHAR size;
90	} read_config;
91
92	/* write PCI configuration space */
93	struct {
94	UCHAR subfunction;
95	UCHAR bus;
96	UCHAR dev_func;
97	UCHAR reg;
98	UCHAR size;
99	ULONG data;
100	} write_config;
101
102	} OH_PARM;
103
104	/******************************************************************************
105	* OEMHLP IOCtl data union. The data area is generally used as output from the
106	* OEMHLP IOCtl calls.
107	*/
108	typedef union {
109
110	/* query PCI BIOS information" */
111	struct {
112	UCHAR rc;
113	UCHAR hw_mech;
114	UCHAR major_version;
115	UCHAR minor_version;
116	UCHAR last_bus;
117	} bios_info;
118
119	/* find PCI device */
120	struct {
121	UCHAR rc;
122	UCHAR bus;
123	UCHAR dev_func;
124	} find_device;
125
126	/* find PCI class code */
127	struct {
128	UCHAR rc;
129	UCHAR bus;
130	UCHAR dev_func;
131	} find_class;
132
133	/* read PCI confguration space */
134	struct {
135	UCHAR rc;
136	ULONG data;
137	} read_config;
138
139	/* write PCI confguration space */
140	struct {
141	UCHAR rc;
142	} write_config;
143
144	} OH_DATA;
145
146	/* -------------------------- function prototypes -------------------------- */
147
148	static void add_pci_device (PCI_ID pci_id, OH_DATA _far data);
149	static UCHAR pci_read_conf (UCHAR bus, UCHAR dev_func, UCHAR indx,
150	UCHAR size, ULONG _far *val);
151	static UCHAR pci_write_conf (UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
152	ULONG val);
153	static int oemhlp_call (UCHAR subfunction, OH_PARM _far *parm,
154	OH_DATA _far *data);
155	static long bar_resource (UCHAR bus, UCHAR dev_func,
156	RESOURCESTRUCT _far *resource, int i);
157	static char *rmerr (APIRET ret);
158
159	/* ------------------------ global/static variables ------------------------ */
160
161	/******************************************************************************
162	* chipset/controller name strings
163	*/
164	static char chip_esb2[] = "ESB2";
165	static char chip_ich8[] = "ICH8";
166	static char chip_ich8m[] = "ICH8M";
167	static char chip_ich9[] = "ICH9";
168	static char chip_ich9m[] = "ICH9M";
169	static char chip_ich10[] = "ICH10";
170	static char chip_pchahci[] = "PCH AHCI";
171	static char chip_pchraid[] = "PCH RAID";
172	static char chip_tolapai[] = "Tolapai";
173	static char chip_sb600[] = "SB600";
174	static char chip_sb700[] = "SB700/800";
175	static char chip_vt8251[] = "VT8251";
176	static char chip_mcp65[] = "MCP65";
177	static char chip_mcp67[] = "MCP67";
178	static char chip_mcp73[] = "MCP73";
179	static char chip_mcp77[] = "MCP77";
180	static char chip_mcp79[] = "MCP79";
181	static char chip_mcp89[] = "MCP689";
182	static char chip_sis968[] = "968";
183
184	static char s_generic[] = "Generic";
185
186	/******************************************************************************
187	* other strings
188	*/
189	static char s_already_claimed[] = "Warning: device already claimed by another driver.\n";
190
191
192
193	/******************************************************************************
194	* PCI vendor and device IDs for known AHCI adapters. Copied from the Linux
195	* AHCI driver.
196	*/
197
198	PCI_ID pci_ids[] = {
199
200	/* Intel
201	* NOTE: ICH5 controller does NOT support AHCI, so we do
202	* not add it here! */
203	{ PCI_VDEVICE(INTEL, 0x2652), board_ahci, "ICH6" }, /* ICH6 */
204	{ PCI_VDEVICE(INTEL, 0x2653), board_ahci, "ICH6M" }, /* ICH6M */
205	{ PCI_VDEVICE(INTEL, 0x27c1), board_ahci, "ICH7" }, /* ICH7 */
206	{ PCI_VDEVICE(INTEL, 0x27c5), board_ahci, "ICH7M" }, /* ICH7M */
207	{ PCI_VDEVICE(INTEL, 0x27c3), board_ahci, "ICH7R" }, /* ICH7R */
208	{ PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr, "ULiM5288" }, /* ULi M5288 */
209	{ PCI_VDEVICE(INTEL, 0x2681), board_ahci, chip_esb2 }, /* ESB2 */
210	{ PCI_VDEVICE(INTEL, 0x2682), board_ahci, chip_esb2 }, /* ESB2 */
211	{ PCI_VDEVICE(INTEL, 0x2683), board_ahci, chip_esb2 }, /* ESB2 */
212	{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci, "ICH7MDH" }, /* ICH7-M DH */
213	{ PCI_VDEVICE(INTEL, 0x2821), board_ahci, chip_ich8 }, /* ICH8 */
214	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf, chip_ich8 }, /* ICH8 */
215	{ PCI_VDEVICE(INTEL, 0x2824), board_ahci, chip_ich8 }, /* ICH8 */
216	{ PCI_VDEVICE(INTEL, 0x2829), board_ahci, chip_ich8m }, /* ICH8M */
217	{ PCI_VDEVICE(INTEL, 0x282a), board_ahci, chip_ich8m }, /* ICH8M */
218	{ PCI_VDEVICE(INTEL, 0x2922), board_ahci, chip_ich9 }, /* ICH9 */
219	{ PCI_VDEVICE(INTEL, 0x2923), board_ahci, chip_ich9 }, /* ICH9 */
220	{ PCI_VDEVICE(INTEL, 0x2924), board_ahci, chip_ich9 }, /* ICH9 */
221	{ PCI_VDEVICE(INTEL, 0x2925), board_ahci, chip_ich9 }, /* ICH9 */
222	{ PCI_VDEVICE(INTEL, 0x2927), board_ahci, chip_ich9 }, /* ICH9 */
223	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci, chip_ich9m }, /* ICH9M */
224	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci, chip_ich9m }, /* ICH9M */
225	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci, chip_ich9m }, /* ICH9M */
226	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci, chip_ich9m }, /* ICH9M */
227	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci, chip_ich9m }, /* ICH9M */
228	{ PCI_VDEVICE(INTEL, 0x294d), board_ahci, chip_ich9 }, /* ICH9 */
229	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci, chip_ich9m }, /* ICH9M */
230	{ PCI_VDEVICE(INTEL, 0x502a), board_ahci, chip_tolapai }, /* Tolapai */
231	{ PCI_VDEVICE(INTEL, 0x502b), board_ahci, chip_tolapai }, /* Tolapai */
232	{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci, chip_ich10 }, /* ICH10 */
233	{ PCI_VDEVICE(INTEL, 0x3a22), board_ahci, chip_ich10 }, /* ICH10 */
234	{ PCI_VDEVICE(INTEL, 0x3a25), board_ahci, chip_ich10 }, /* ICH10 */
235	{ PCI_VDEVICE(INTEL, 0x3b22), board_ahci, chip_pchahci }, /* PCH AHCI */
236	{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci, chip_pchahci }, /* PCH AHCI */
237	{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci, chip_pchraid }, /* PCH RAID */
238	{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci, chip_pchraid }, /* PCH RAID */
239	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci, chip_pchahci }, /* PCH AHCI */
240	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci, chip_pchraid }, /* PCH RAID */
241	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci, chip_pchraid }, /* PCH RAID */
242	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci, chip_pchahci }, /* PCH AHCI */
243
244	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
245	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
246	PCI_CLASS_STORAGE_SATA_AHCI, 0xffffffL, board_ahci_ign_iferr, "360" },
247
248	/* ATI */
249	{ PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600, chip_sb600 }, /* ATI SB600 */
250	{ PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
251	{ PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
252	{ PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
253	{ PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
254	{ PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
255	{ PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700, chip_sb700 }, /* ATI SB700/800 */
256
257	/* AMD */
258	{ PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
259	/* AMD is using RAID class only for ahci controllers */
260	{ PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
261	PCI_CLASS_STORAGE_RAID << 8, 0xffffffL, board_ahci, "Hudson2" },
262
263	/* VIA */
264	{ PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251, chip_vt8251 }, /* VIA VT8251 */
265	{ PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251, chip_vt8251 }, /* VIA VT8251 */
266
267	/* NVIDIA */
268	{ PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
269	{ PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
270	{ PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
271	{ PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
272	{ PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
273	{ PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
274	{ PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
275	{ PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65, chip_mcp65 }, /* MCP65 */
276	{ PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
277	{ PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
278	{ PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
279	{ PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
280	{ PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
281	{ PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
282	{ PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
283	{ PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
284	{ PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
285	{ PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
286	{ PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
287	{ PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq, chip_mcp67 }, /* MCP67 */
288	{ PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq, chip_mcp67 }, /* Linux ID */
289	{ PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
290	{ PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
291	{ PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
292	{ PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
293	{ PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
294	{ PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
295	{ PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
296	{ PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
297	{ PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
298	{ PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
299	{ PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
300	{ PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq, chip_mcp73 }, /* MCP73 */
301	{ PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci, chip_mcp77 }, /* MCP77 */
302	{ PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci, chip_mcp77 }, /* MCP77 */
303	{ PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci, chip_mcp77 }, /* MCP77 */
304	{ PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci, chip_mcp77 }, /* MCP77 */
305	{ PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci, chip_mcp77 }, /* MCP77 */
306	{ PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci, chip_mcp77 }, /* MCP77 */
307	{ PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci, chip_mcp77 }, /* MCP77 */
308	{ PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci, chip_mcp77 }, /* MCP77 */
309	{ PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci, chip_mcp77 }, /* MCP77 */
310	{ PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci, chip_mcp77 }, /* MCP77 */
311	{ PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci, chip_mcp77 }, /* MCP77 */
312	{ PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci, chip_mcp77 }, /* MCP77 */
313	{ PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci, chip_mcp79 }, /* MCP79 */
314	{ PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci, chip_mcp79 }, /* MCP79 */
315	{ PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci, chip_mcp79 }, /* MCP79 */
316	{ PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci, chip_mcp79 }, /* MCP79 */
317	{ PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci, chip_mcp79 }, /* MCP79 */
318	{ PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci, chip_mcp79 }, /* MCP79 */
319	{ PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci, chip_mcp79 }, /* MCP79 */
320	{ PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci, chip_mcp79 }, /* MCP79 */
321	{ PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci, chip_mcp79 }, /* MCP79 */
322	{ PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci, chip_mcp79 }, /* MCP79 */
323	{ PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci, chip_mcp79 }, /* MCP79 */
324	{ PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci, chip_mcp79 }, /* MCP79 */
325	{ PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci, chip_mcp89 }, /* MCP89 */
326	{ PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci, chip_mcp89 }, /* MCP89 */
327	{ PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci, chip_mcp89 }, /* MCP89 */
328	{ PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci, chip_mcp89 }, /* MCP89 */
329	{ PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci, chip_mcp89 }, /* MCP89 */
330	{ PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci, chip_mcp89 }, /* MCP89 */
331	{ PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci, chip_mcp89 }, /* MCP89 */
332	{ PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci, chip_mcp89 }, /* MCP89 */
333	{ PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci, chip_mcp89 }, /* MCP89 */
334	{ PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci, chip_mcp89 }, /* MCP89 */
335	{ PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci, chip_mcp89 }, /* MCP89 */
336	{ PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci, chip_mcp89 }, /* MCP89 */
337
338	/* SiS */
339	{ PCI_VDEVICE(SI, 0x1184), board_ahci, "966" }, /* SiS 966 */
340	{ PCI_VDEVICE(SI, 0x1185), board_ahci, chip_sis968 }, /* SiS 968 */
341	{ PCI_VDEVICE(SI, 0x0186), board_ahci, chip_sis968 }, /* SiS 968 */
342
343	/* Marvell */
344	{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv, "6145" }, /* 6145 */
345	{ PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv, "6121" }, /* 6121 */
346
347	/* Promise */
348	{ PCI_VDEVICE(PROMISE, 0x3f20), board_ahci, "PDC42819" }, /* PDC42819 */
349
350	/* Generic, PCI class code for AHCI */
351	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
352	PCI_CLASS_STORAGE_SATA_AHCI, 0xffffffL, board_ahci, s_generic },
353
354	/* end of list, including a few slots to define custom adapters (10) */
355	{ 0, 0, 0, 0, 0, 0, 0, NULL },
356	{ 0, 0, 0, 0, 0, 0, 0, NULL },
357	{ 0, 0, 0, 0, 0, 0, 0, NULL },
358	{ 0, 0, 0, 0, 0, 0, 0, NULL },
359	{ 0, 0, 0, 0, 0, 0, 0, NULL },
360	{ 0, 0, 0, 0, 0, 0, 0, NULL },
361	{ 0, 0, 0, 0, 0, 0, 0, NULL },
362	{ 0, 0, 0, 0, 0, 0, 0, NULL },
363	{ 0, 0, 0, 0, 0, 0, 0, NULL },
364	{ 0, 0, 0, 0, 0, 0, 0, NULL },
365
366	{ 0, 0, 0, 0, 0, 0, 0, NULL }
367	};
368
369	/******************************************************************************
370	* OEMHLP$ is used by OS/2 to provide access to OEM-specific machine resources
371	* like PCI BIOS access. We're using this to enumerate the PCI bus. Due to
372	* BIOS bugs, it may be necessary to use I/O operations for this purpose but
373	* so far I think this is only relevant for rather old PCs and SATA is not
374	* expected to be a priority on those machines.
375	*/
376	static IDCTABLE oemhlp; /* OEMHLP$ IDC entry point */
377
378	/* ----------------------------- start of code ----------------------------- */
379
380	/******************************************************************************
381	* Add specified PCI vendor and device ID to the list of supported AHCI
382	* controllers. Please note that the last slot in pci_ids needs to remain
383	* empty because it's used as end marker.
384	*/
385	int add_pci_id(u16 vendor, u16 device)
386	{
387	int max_slot = sizeof(pci_ids) / sizeof(*pci_ids) - 2;
388	int i;
389
390	/* search for last used slot in 'pci_ids' */
391	for (i = max_slot; i >= 0 && pci_ids[i].vendor == 0; i--);
392	if (i >= max_slot) {
393	/* all slots in use */
394	return(-1);
395	}
396
397	/* use slot after the last used slot */
398	i++;
399	pci_ids[i].vendor = vendor;
400	pci_ids[i].device = device;
401	pci_ids[i].board = board_ahci;
402	pci_ids[i].chipname = s_generic;
403	return(0);
404	}
405
406	/******************************************************************************
407	* Scan PCI bus using OEMHLP$ IOCTLs and build adapter list.
408	*/
409	void scan_pci_bus(void)
410	{
411	OH_PARM parm;
412	OH_DATA data;
413	UCHAR index;
414	UCHAR rc;
415	int ad_indx = 0;
416	int i;
417	int n;
418
419	ddprintf("scanning PCI bus...\n");
420
421	/* verify that we have a PCI system */
422	memset(&parm, 0x00, sizeof(parm));
423	if (oemhlp_call(OH_BIOS_INFO, &parm, &data) != OH_SUCCESS) {
424	cprintf("couldn't get PCI BIOS information\n");
425	return;
426	}
427
428	/* Go through the list of PCI IDs and search for each device
429	*
430	* NOTES:
431	*
432	* - When searching via class code, the OEMHLP$ interface doesn't allow
433	* setting a bitmask to look for individual portions of class code,
434	* subclass code and programming interface. However, all bitmasks in the
435	* PCI list currently use 0xffffff, thus this should not be a problem at
436	* this point in time.
437	*
438	* - Scanning via OEMHLP$ seems rather slow, at least in the virtual
439	* machine I'm currenly using to test this driver. Thus, class code
440	* scans are preferred unless the option "-t" (thorough_scan) has been
441	* specified. The assumption is that most, if not all, modern AHCI
442	* adapters have the correct class code (PCI_CLASS_STORAGE_SATA_AHCI).
443	*/
444	for (i = 0; pci_ids[i].vendor != 0; i++) {
445	index = 0;
446	do {
447	if (pci_ids[i].device == PCI_ANY_ID \|\| pci_ids[i].vendor == PCI_ANY_ID) {
448	/* look for class code */
449	memset(&parm, 0x00, sizeof(parm));
450	parm.find_class.class = pci_ids[i].class;
451	parm.find_class.index = index;
452	rc = oemhlp_call(OH_FIND_CLASS, &parm, &data);
453
454	} else if (thorough_scan) {
455	/* look for this specific vendor and device ID */
456	memset(&parm, 0x00, sizeof(parm));
457	parm.find_device.device = pci_ids[i].device;
458	parm.find_device.vendor = pci_ids[i].vendor;
459	parm.find_device.index = index;
460	rc = oemhlp_call(OH_FIND_DEVICE, &parm, &data);
461
462	} else {
463	rc = OH_NOT_FOUND;
464	}
465
466	if (rc == OH_SUCCESS) {
467	/* found a device */
468	int already_found = 0;
469
470	/* increment index for next loop */
471	if (++index > 180) {
472	/* something's wrong here... */
473	return;
474	}
475
476	/* check whether we already found this device */
477	for (n = 0; n < ad_info_cnt; n++) {
478	if (ad_infos[n].bus == data.find_device.bus &&
479	ad_infos[n].dev_func == data.find_device.dev_func) {
480	/* this device has already been found (e.g. via thorough scan) */
481	already_found = 1;
482	break;
483	}
484	}
485
486	if (already_found \|\| (ad_ignore & (1U << ad_indx++))) {
487	/* ignore this device; it has either already been found via a
488	* thorough scan or has been specified to be ignored via command
489	* line option */
490	continue;
491	}
492
493	/* add this PCI device to ad_infos[] */
494	add_pci_device(pci_ids + i, &data);
495	}
496
497	} while (rc == OH_SUCCESS);
498	}
499	}
500
501	/******************************************************************************
502	* Enable interrupt generation. PCI 2.3 added a bit which allows disabling
503	* interrupt generation for a device. This function clears the corresponding
504	* bit in the configuration space command register.
505	*/
506	int pci_enable_int(UCHAR bus, UCHAR dev_func)
507	{
508	ULONG tmp;
509
510	if (pci_read_conf (bus, dev_func, 4, sizeof(u32), &tmp) != OH_SUCCESS \|\|
511	pci_write_conf(bus, dev_func, 4, sizeof(u32), tmp & ~(1UL << 10)) != OH_SUCCESS) {
512	return(-1);
513	}
514	return(0);
515	}
516
517	/******************************************************************************
518	* Hack to set up proper IRQ mappings in the emulated PIIX3 ISA bridge in
519	* VirtualBox (for some reason, the first mapped IRQ is 0x80 without this
520	* hack).
521	*/
522	void pci_hack_virtualbox(void)
523	{
524	ULONG irq = 0;
525
526	if (pci_read_conf(0, 0x08, 0x60, 1, &irq) == OH_SUCCESS && irq == 0x80) {
527	/* set IRQ for first device/func to 11 */
528	dprintf("hacking virtualbox PIIX3 PCI to ISA bridge IRQ mapping\n");
529	irq = ad_infos[0].irq;
530	pci_write_conf(0, 0x08, 0x60, 1, irq);
531	}
532	}
533
534	/******************************************************************************
535	* Add a single PCI device to the list of adapters.
536	*/
537	static void add_pci_device(PCI_ID pci_id, OH_DATA _far data)
538	{
539	char rc_list_buf[sizeof(AHRESOURCE) + sizeof(HRESOURCE) * 15];
540	AHRESOURCE _far rc_list = (AHRESOURCE _far ) rc_list_buf;
541	RESOURCESTRUCT resource;
542	ADAPTERSTRUCT adapter;
543	ADJUNCT adj;
544	AD_INFO *ad_info;
545	APIRET ret;
546	UCHAR bus = data->find_class.bus;
547	UCHAR dev_func = data->find_class.dev_func;
548	ULONG val;
549	SEL gdt[PORT_DMA_BUF_SEGS + 1];
550	char tmp[40];
551	u16 device;
552	u16 vendor;
553	u32 class;
554	int irq;
555	int pin;
556	int i;
557
558	/*****************************************************************************
559	* Part 1: Get further information about the device to be added; PCI ID...
560	*/
561	if (pci_read_conf(bus, dev_func, 0x00, sizeof(ULONG), &val) != OH_SUCCESS) {
562	return;
563	}
564	device = (u16) (val >> 16);
565	vendor = (u16) (val & 0xffff);
566
567	/* ... and class code */
568	if (pci_read_conf(bus, dev_func, 0x08, sizeof(ULONG), &val) != OH_SUCCESS) {
569	return;
570	}
571	class = (u32) (val >> 8);
572
573	if (pci_id->device == PCI_ANY_ID) {
574	/* We found this device in a wildcard search. There are two possible
575	* reasons which require a different handling:
576	*
577	* 1) This device uses a non-standard PCI class and has been identified
578	* with the corresponding class in pci_ids[] (e.g. the entry
579	* PCI_VENDOR_ID_JMICRON), but there is a vendor ID in pci_ids[]. In
580	* this case, we need to verify that the vendor is correct (see
581	* comments regarding OEMHLP limitations in 'scan_pci_bus()')
582	*
583	* 2) This device was identified using a generic PCI class for AHCI
584	* adapters such as PCI_CLASS_STORAGE_SATA_AHCI and we need to map
585	* the device and vendor ID to the corresponding index in pci_ids[]
586	* if there is such an entry; the index passed to this function will
587	* be the generic class-based index which is fine as long as there's
588	* not special treatment required as indicated by the board_*
589	* constants in pci_ids[]...
590	*
591	* The main reason for this kludge is that it seems as if OEMHLP$
592	* is rather slow searching for PCI devices, adding around 30s
593	* to the boot time when scanning for individual AHCI PCI IDs. Thus,
594	* the OS2AHCI driver avoids this kind of scan in favor of a class-
595	* based scan (unless overridden with the "/T" option).
596	*/
597	if (pci_id->vendor != PCI_ANY_ID) {
598	/* case 1: the vendor is known but we found the PCI device using a class
599	* search; verify vendor matches the one in pci_ids[]
600	*/
601	if (pci_id->vendor != vendor) {
602	/* vendor doesn't match */
603	return;
604	}
605
606	} else {
607	/* case 2: we found this device using a generic class search; if the
608	* device/vendor is listed in pci_ids[], use this entry in favor of the
609	* one passed in 'pci_id'
610	*/
611	for (i = 0; pci_ids[i].vendor != 0; i++) {
612	if (pci_ids[i].device == device && pci_ids[i].vendor == vendor) {
613	pci_id = pci_ids + i;
614	break;
615	}
616	}
617	}
618	}
619
620	/* found a supported AHCI device */
621	if (verbosity > 0) {
622	cprintf("found AHCI device: %s %s (%04x:%04x)\n"
623	" class:0x%06lx bus:%d devfunc:0x%02x\n",
624	vendor_from_id(vendor), device_from_id(device),
625	vendor, device,
626	class, bus, dev_func);
627	}
628
629	/* make sure we got room in the adapter information array */
630	if (ad_info_cnt >= MAX_AD - 1) {
631	cprintf("error: too many AHCI devices\n");
632	return;
633	}
634
635	/****************************************************************************
636	* Part 2: Determine resource requirements and allocate resources with the
637	* OS/2 resource manager. While doing so, some of the entries of the
638	* corresponding slot in the AD_INFO array, namely resource manager
639	* handles, are initialized so we need prepare the slot.
640	*
641	* NOTE: While registering resources with the resource manager, each new
642	* resource is added to the corresponding rc_list.hResource[] slot.
643	* rc_list is used further down to associate resources to adapters
644	* when the adapter itself is registered with the OS/2 resource
645	* manager.
646	*/
647	ad_info = ad_infos + ad_info_cnt;
648	memset(ad_info, 0x00, sizeof(*ad_info));
649	rc_list->NumResource = 0;
650
651	/* Register IRQ with resource manager
652	*
653	* NOTE: We rely on the IRQ number saved in the PCI config space by the PCI
654	* BIOS. There's no reliable way to find out the IRQ number in any
655	* other way unless we start using message-driven interrupts (which
656	* is out of scope for the time being).
657	*/
658	if (pci_read_conf(bus, dev_func, 0x3c, sizeof(u32), &val) != OH_SUCCESS) {
659	return;
660	}
661	irq = (int) (val & 0xff);
662	pin = (int) ((val >> 8) & 0xff);
663
664	memset(&resource, 0x00, sizeof(resource));
665	resource.ResourceType = RS_TYPE_IRQ;
666	resource.IRQResource.IRQLevel = irq;
667	resource.IRQResource.PCIIrqPin = pin;
668	resource.IRQResource.IRQFlags = RS_IRQ_SHARED;
669
670	ret = RMAllocResource(rm_drvh, &ad_info->rm_irq, &resource);
671	if (ret != RMRC_SUCCESS) {
672	cprintf("error: couldn't register IRQ %d (rc = %s)\n", irq, rmerr(ret));
673	return;
674	}
675	rc_list->hResource[rc_list->NumResource++] = ad_info->rm_irq;
676
677	/* Allocate all I/O and MMIO addresses offered by this device. In theory,
678	* we need only BAR #5, the AHCI MMIO BAR, but in order to prevent any
679	* other driver from hijacking our device and accessing it via legacy
680	* registers we'll reserve anything we can find.
681	*/
682	for (i = 0; i < sizeof(ad_info->rm_bars) / sizeof(*ad_info->rm_bars); i++) {
683	long len = bar_resource(bus, dev_func, &resource, i);
684
685	if (len < 0) {
686	/* something went wrong */
687	goto add_pci_fail;
688	}
689	if (len == 0) {
690	/* this BAR is unused */
691	continue;
692	}
693
694	if (i == AHCI_PCI_BAR) {
695	if (resource.ResourceType != RS_TYPE_MEM) {
696	cprintf("error: BAR #5 must be an MMIO region\n");
697	goto add_pci_fail;
698	}
699	/* save this BAR's address as MMIO address */
700	ad_info->mmio_phys = resource.MEMResource.MemBase;
701	ad_info->mmio_size = resource.MEMResource.MemSize;
702	}
703
704	/* register [MM]IO region with resource manager */
705	ret = RMAllocResource(rm_drvh, ad_info->rm_bars + i, &resource);
706	if (ret != RMRC_SUCCESS) {
707	cprintf("error: couldn't register [MM]IO region (rc = %s)\n", rmerr(ret));
708	goto add_pci_fail;
709	}
710	rc_list->hResource[rc_list->NumResource++] = ad_info->rm_bars[i];
711	}
712
713	if (ad_info->mmio_phys == 0) {
714	cprintf("error: couldn't determine MMIO base address\n");
715	goto add_pci_fail;
716	}
717
718	/****************************************************************************
719	* Part 3: Fill in the remaining fields in the AD_INFO slot and allocate
720	* memory and GDT selectors for the adapter. Finally, register the adapter
721	* itself with the OS/2 resource manager
722	*/
723	ad_info->pci = pci_ids + i;
724	ad_info->bus = bus;
725	ad_info->dev_func = dev_func;
726	ad_info->irq = irq;
727
728	/* allocate memory for port-specific DMA scratch buffers */
729	if (DevHelp_AllocPhys((long) AHCI_PORT_PRIV_DMA_SZ * AHCI_MAX_PORTS,
730	MEMTYPE_ABOVE_1M, &ad_info->dma_buf_phys) != 0) {
731	cprintf("error: couldn't allocate DMA scratch buffers for AHCI ports\n");
732	ad_info->dma_buf_phys = 0;
733	goto add_pci_fail;
734	}
735
736	/* allocate GDT selectors for memory-mapped I/O and DMA scratch buffers */
737	if (DevHelp_AllocGDTSelector(gdt, PORT_DMA_BUF_SEGS + 1) != 0) {
738	cprintf("error: couldn't allocate GDT selectors\n");
739	memset(gdt, 0x00, sizeof(gdt));
740	goto add_pci_fail;
741	}
742
743	/* map MMIO address to first GDT selector */
744	if (DevHelp_PhysToGDTSelector(ad_info->mmio_phys,
745	(USHORT) ad_info->mmio_size, gdt[0]) != 0) {
746	cprintf("error: couldn't map MMIO address to GDT selector\n");
747	goto add_pci_fail;
748	}
749
750	/* map DMA scratch buffers to remaining GDT selectors */
751	for (i = 0; i < PORT_DMA_BUF_SEGS; i++) {
752	ULONG addr = ad_info->dma_buf_phys + i * PORT_DMA_SEG_SIZE;
753	USHORT len = AHCI_PORT_PRIV_DMA_SZ * PORT_DMA_BUFS_PER_SEG;
754
755	if (DevHelp_PhysToGDTSelector(addr, len, gdt[i+1]) != 0) {
756	cprintf("error: couldn't map DMA scratch buffer to GDT selector\n");
757	goto add_pci_fail;
758	}
759	}
760
761	/* fill in MMIO and DMA scratch buffer addresses in adapter info */
762	ad_info->mmio = (u8 _far *) ((u32) gdt[0] << 16);
763	for (i = 0; i < PORT_DMA_BUF_SEGS; i++) {
764	ad_info->dma_buf[i] = (u8 _far *) ((u32) gdt[i+1] << 16);
765	}
766
767	/* register adapter with resource manager */
768	memset(&adj, 0x00, sizeof(adj));
769	adj.pNextAdj = NULL;
770	adj.AdjLength = sizeof(adj);
771	adj.AdjType = ADJ_ADAPTER_NUMBER;
772	adj.Adapter_Number = ad_info_cnt;
773
774	memset(&adapter, 0x00, sizeof(adapter));
775	sprintf(tmp, "AHCI_%d Controller", ad_info_cnt);
776	adapter.AdaptDescriptName = tmp;
777	adapter.AdaptFlags = 0;
778	adapter.BaseType = AS_BASE_MSD;
779	adapter.SubType = AS_SUB_IDE;
780	adapter.InterfaceType = AS_INTF_GENERIC;
781	adapter.HostBusType = AS_HOSTBUS_PCI;
782	adapter.HostBusWidth = AS_BUSWIDTH_32BIT;
783	adapter.pAdjunctList = &adj;
784
785	ret = RMCreateAdapter(rm_drvh, &ad_info->rm_adh, &adapter, NULL, rc_list);
786	if (ret != RMRC_SUCCESS) {
787	cprintf("error: couldn't register adapter (rc = %s)\n", rmerr(ret));
788	goto add_pci_fail;
789	}
790
791	/* Successfully added the adapter and reserved its resources; the adapter
792	* is still under BIOS control so we're not going to do anything else at
793	* this point.
794	*/
795	ad_info_cnt++;
796	return;
797
798	add_pci_fail:
799	/* something went wrong; try to clean up as far as possible */
800	for (i = 0; i < sizeof(ad_info->rm_bars) / sizeof(*ad_info->rm_bars); i++) {
801	if (ad_info->rm_bars[i] != 0) {
802	RMDeallocResource(rm_drvh, ad_info->rm_bars[i]);
803	}
804	}
805	if (ad_info->rm_irq != 0) {
806	RMDeallocResource(rm_drvh, ad_info->rm_irq);
807	}
808	for (i = 0; i < sizeof(gdt) / sizeof(*gdt); i++) {
809	if (gdt[i] != 0) {
810	DevHelp_FreeGDTSelector(gdt[i]);
811	}
812	}
813	if (ad_info->dma_buf_phys != 0) {
814	DevHelp_FreePhys(ad_info->dma_buf_phys);
815	}
816	}
817
818	/******************************************************************************
819	* Read PCI configuration space register
820	*/
821	static UCHAR pci_read_conf(UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
822	ULONG _far *val)
823	{
824	OH_PARM parm;
825	OH_DATA data;
826	UCHAR rc;
827
828	memset(&parm, 0x00, sizeof(parm));
829	parm.read_config.bus = bus;
830	parm.read_config.dev_func = dev_func;
831	parm.read_config.reg = indx;
832	parm.read_config.size = size;
833	if ((rc = oemhlp_call(OH_READ_CONFIG, &parm, &data) != OH_SUCCESS)) {
834	cprintf("error: couldn't read config space (bus = %d, dev_func = 0x%02x, indx = 0x%02x, rc = %d)\n",
835	bus, dev_func, indx, rc);
836	return(rc);
837	}
838
839	*val = data.read_config.data;
840	return(OH_SUCCESS);
841	}
842
843	/******************************************************************************
844	* Write PCI configuration space register
845	*/
846	static UCHAR pci_write_conf(UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
847	ULONG val)
848	{
849	OH_PARM parm;
850	OH_DATA data;
851	UCHAR rc;
852
853	memset(&parm, 0x00, sizeof(parm));
854	parm.write_config.bus = bus;
855	parm.write_config.dev_func = dev_func;
856	parm.write_config.reg = indx;
857	parm.write_config.size = size;
858	parm.write_config.data = val;
859
860	if ((rc = oemhlp_call(OH_WRITE_CONFIG, &parm, &data) != OH_SUCCESS)) {
861	cprintf("error: couldn't write config space (bus = %d, dev_func = 0x%02x, indx = 0x%02x, rc = %d)\n",
862	bus, dev_func, indx, rc);
863	return(rc);
864	}
865
866	return(OH_SUCCESS);
867	}
868	/******************************************************************************
869	* Call OEMHLP$ IDC entry point with the specified IOCtl parameter and data
870	* packets.
871	*/
872	static int oemhlp_call(UCHAR subfunction, OH_PARM _far *parm,
873	OH_DATA _far *data)
874	{
875	void (_far *func)(void);
876	RP_GENIOCTL ioctl;
877	unsigned short prot_idc_ds;
878
879	if (oemhlp.ProtIDCEntry == NULL \|\| oemhlp.ProtIDC_DS == 0) {
880	/* attach to OEMHLP$ device driver */
881	if (DevHelp_AttachDD("OEMHLP$ ", (NPBYTE) &oemhlp) \|\|
882	oemhlp.ProtIDCEntry == NULL \|\|
883	oemhlp.ProtIDC_DS == 0) {
884	cprintf("couldn't attach to OEMHLP$\n");
885	return(OH_NOT_SUPPORTED);
886	}
887	}
888
889	/* store subfuntion in first byte of pararameter packet */
890	parm->bios_info.subfunction = subfunction;
891	memset(data, 0x00, sizeof(*data));
892
893	/* assemble IOCtl request */
894	memset(&ioctl, 0x00, sizeof(ioctl));
895	ioctl.rph.Len = sizeof(ioctl);
896	ioctl.rph.Unit = 0;
897	ioctl.rph.Cmd = GENERIC_IOCTL;
898	ioctl.rph.Status = 0;
899
900	ioctl.Category = OH_CATEGORY;
901	ioctl.Function = OH_FUNC_PCI;
902	ioctl.ParmPacket = (PUCHAR) parm;
903	ioctl.DataPacket = (PUCHAR) data;
904	ioctl.ParmLen = sizeof(*parm);
905	ioctl.DataLen = sizeof(*data);
906
907	/* Call OEMHLP's IDC routine. Before doing so, we need to assign the address
908	* to be called to a stack variable because the inter-device driver calling
909	* convention forces us to set DS to the device driver's data segment and ES
910	* to the segment of the request packet.
911	*/
912	func = oemhlp.ProtIDCEntry;
913
914	/* The WATCOM compiler does not support struct references in inline
915	* assembler code, so we pass it in a stack variable
916	*/
917	prot_idc_ds = oemhlp.ProtIDC_DS;
918
919	_asm {
920	push ds;
921	push es;
922	push bx;
923	push si;
924	push di;
925
926	push ss
927	pop es
928	lea bx, ioctl;
929	mov ds, prot_idc_ds;
930	call dword ptr [func];
931
932	pop di;
933	pop si;
934	pop bx;
935	pop es;
936	pop ds;
937	}
938
939	dddphex(parm, sizeof(*parm), "oemhlp_parm: ");
940	dddphex(data, sizeof(*data), "oemhlp_data: ");
941
942	if (ioctl.rph.Status & STERR) {
943	return(OH_NOT_SUPPORTED);
944	}
945	return(data->bios_info.rc);
946	}
947
948	/******************************************************************************
949	* Prepare a resource structure for a PCI Base Address Register (BAR). This
950	* basically means the type, address and range of the I/O address space. It
951	* returns the length of the address range as a signed long to allow the caller
952	* to differentiate between error conditions (< 0), unused BARs (0) or valid
953	* bars (> 0).
954	*
955	* NOTE: In order to do this, we need to temporarily write 0xffffffff to
956	* the MMIO base address register (BAR), read back the resulting value
957	* and check the 0 bits from the right end, masking the lower 2 (I/O) or
958	* 4 (MMIO) bits. After doing this, we must restore the original value
959	* set up by the BIOS.
960	*
961	* 31 4 3 2 1 0
962	* -------------------------------------------------------------------
963	* base address P T T I
964	* P = prefetchable
965	* T = type (0 = any 32 bit, 1 = <1M, 2 = 64 bit)
966	* I = I/O (1) or memory (0)
967	*/
968	static long bar_resource(UCHAR bus, UCHAR dev_func,
969	RESOURCESTRUCT _far *resource, int i)
970	{
971	u32 bar_addr = 0;
972	u32 bar_size = 0;
973
974	/* temporarily write 1s to this BAR to determine the address range */
975	if (pci_read_conf (bus, dev_func, PCI_BAR(i), sizeof(u32), &bar_addr) != OH_SUCCESS \|\|
976	pci_write_conf(bus, dev_func, PCI_BAR(i), sizeof(u32), ~(0UL)) != OH_SUCCESS \|\|
977	pci_read_conf (bus, dev_func, PCI_BAR(i), sizeof(u32), &bar_size) != OH_SUCCESS \|\|
978	pci_write_conf(bus, dev_func, PCI_BAR(i), sizeof(u32), bar_addr) != OH_SUCCESS) {
979
980	cprintf("error: couldn't determine [MM]IO size\n");
981	if (bar_addr != 0) {
982	pci_write_conf(bus, dev_func, PCI_BAR(i), sizeof(u32), bar_addr);
983	}
984	return(-1);
985	}
986
987	if (bar_size == 0 \|\| bar_size == 0xffffffffUL) {
988	/* bar not implemented or device not working properly */
989	return(0);
990	}
991
992	/* prepare resource allocation structure */
993	memset(resource, 0x00, sizeof(*resource));
994	if (bar_addr & 1) {
995	bar_size = ~(bar_size & 0xfffffffcUL) + 1;
996	bar_size &= 0xffffUL; /* I/O address space is 16 bits on x86 */
997	bar_addr &= 0xfffcUL;
998
999	resource->ResourceType = RS_TYPE_IO;
1000	resource->IOResource.BaseIOPort = bar_addr;
1001	resource->IOResource.NumIOPorts = bar_size;
1002	resource->IOResource.IOFlags = RS_IO_EXCLUSIVE;
1003	resource->IOResource.IOAddressLines = 16;
1004
1005	} else {
1006	bar_size = ~(bar_size & 0xfffffff0UL) + 1;
1007	bar_addr &= 0xfffffff0UL;
1008
1009	resource->ResourceType = RS_TYPE_MEM;
1010	resource->MEMResource.MemBase = bar_addr;
1011	resource->MEMResource.MemSize = bar_size;
1012	resource->MEMResource.MemFlags = RS_MEM_EXCLUSIVE;
1013	}
1014
1015	ddprintf("BAR #%d: type = %s, addr = 0x%08lx, size = %ld\n", i,
1016	(resource->ResourceType == RS_TYPE_IO) ? "I/O" : "MEM",
1017	bar_addr, bar_size);
1018
1019	return((long) bar_size);
1020	}
1021
1022	/******************************************************************************
1023	* return vendor name for PCI vendor ID
1024	*/
1025	char *vendor_from_id(u16 id)
1026	{
1027
1028	switch(id) {
1029
1030	case PCI_VENDOR_ID_AL:
1031	return "Ali";
1032	case PCI_VENDOR_ID_AMD:
1033	case PCI_VENDOR_ID_ATI:
1034	return "AMD";
1035	case PCI_VENDOR_ID_AT:
1036	return "Allied Telesyn";
1037	case PCI_VENDOR_ID_ATT:
1038	return "ATT";
1039	case PCI_VENDOR_ID_CMD:
1040	return "CMD";
1041	case PCI_VENDOR_ID_CT:
1042	return "CT";
1043	case PCI_VENDOR_ID_INTEL:
1044	return "Intel";
1045	case PCI_VENDOR_ID_INITIO:
1046	return "Initio";
1047	case PCI_VENDOR_ID_JMICRON:
1048	return "JMicron";
1049	case PCI_VENDOR_ID_MARVELL:
1050	return "Marvell";
1051	case PCI_VENDOR_ID_NVIDIA:
1052	return "NVIDIA";
1053	case PCI_VENDOR_ID_PROMISE:
1054	return "PROMISE";
1055	case PCI_VENDOR_ID_SI:
1056	return "SiS";
1057	case PCI_VENDOR_ID_VIA:
1058	return "VIA";
1059	default:
1060	break;
1061	}
1062
1063	return "Generic";
1064
1065	}
1066
1067	/******************************************************************************
1068	* return a device name for a PCI device id
1069	* NOTE: this is as simple as can be, so don't call it twice in one statement.
1070	*/
1071	char *device_from_id(u16 device)
1072	{
1073	int i;
1074
1075	for (i = 0; pci_ids[i].vendor != 0; i++) {
1076
1077	if (pci_ids[i].device == device) {
1078	return pci_ids[i].chipname;
1079	}
1080
1081	}
1082
1083	return s_generic;
1084	}
1085
1086	/******************************************************************************
1087	* Return textual version of a resource manager error
1088	*/
1089	static char *rmerr(APIRET ret)
1090	{
1091	switch (ret) {
1092	case RMRC_SUCCESS:
1093	return("RMRC_SUCCESS");
1094	case RMRC_NOTINITIALIZED:
1095	return("RMRC_NOTINITIALIZED");
1096	case RMRC_BAD_DRIVERHANDLE:
1097	return("RMRC_BAD_DRIVERHANDLE");
1098	case RMRC_BAD_ADAPTERHANDLE:
1099	return("RMRC_BAD_ADAPTERHANDLE");
1100	case RMRC_BAD_DEVICEHANDLE:
1101	return("RMRC_BAD_DEVICEHANDLE");
1102	case RMRC_BAD_RESOURCEHANDLE:
1103	return("RMRC_BAD_RESOURCEHANDLE");
1104	case RMRC_BAD_LDEVHANDLE:
1105	return("RMRC_BAD_LDEVHANDLE");
1106	case RMRC_BAD_SYSNAMEHANDLE:
1107	return("RMRC_BAD_SYSNAMEHANDLE");
1108	case RMRC_BAD_DEVHELP:
1109	return("RMRC_BAD_DEVHELP");
1110	case RMRC_NULL_POINTER:
1111	return("RMRC_NULL_POINTER");
1112	case RMRC_NULL_STRINGS:
1113	return("RMRC_NULL_STRINGS");
1114	case RMRC_BAD_VERSION:
1115	return("RMRC_BAD_VERSION");
1116	case RMRC_RES_ALREADY_CLAIMED:
1117	return("RMRC_RES_ALREADY_CLAIMED");
1118	case RMRC_DEV_ALREADY_CLAIMED:
1119	return("RMRC_DEV_ALREADY_CLAIMED");
1120	case RMRC_INVALID_PARM_VALUE:
1121	return("RMRC_INVALID_PARM_VALUE");
1122	case RMRC_OUT_OF_MEMORY:
1123	return("RMRC_OUT_OF_MEMORY");
1124	case RMRC_SEARCH_FAILED:
1125	return("RMRC_SEARCH_FAILED");
1126	case RMRC_BUFFER_TOO_SMALL:
1127	return("RMRC_BUFFER_TOO_SMALL");
1128	case RMRC_GENERAL_FAILURE:
1129	return("RMRC_GENERAL_FAILURE");
1130	case RMRC_IRQ_ENTRY_ILLEGAL:
1131	return("RMRC_IRQ_ENTRY_ILLEGAL");
1132	case RMRC_NOT_IMPLEMENTED:
1133	return("RMRC_NOT_IMPLEMENTED");
1134	case RMRC_NOT_INSTALLED:
1135	return("RMRC_NOT_INSTALLED");
1136	case RMRC_BAD_DETECTHANDLE:
1137	return("RMRC_BAD_DETECTHANDLE");
1138	case RMRC_BAD_RMHANDLE:
1139	return("RMRC_BAD_RMHANDLE");
1140	case RMRC_BAD_FLAGS:
1141	return("RMRC_BAD_FLAGS");
1142	case RMRC_NO_DETECTED_DATA:
1143	return("RMRC_NO_DETECTED_DATA");
1144	default:
1145	return("RMRC_UNKOWN");
1146	}
1147	}

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