source: trunk/src/os2ahci/os2ahci.h@ 78

Last change on this file since 78 was 77, checked in by chris, 15 years ago
  • Further fixes to automatic ATAPI sense handling, now supporting sense buffers larger than 64 bytes if requested by initiator (cdrecord wanted 96 bytes)
  • Separate, and internally handled, spinlock for libc malloc/free calls to reduce chances of memory corruption if somebody forgets to get the driver-level spinlock before calling malloc/free. There was no real problem with that, just some awkward code fragments which look much better now.
  • Link power management implemented
  • More generic support for adapter/port options so all of them can now have a global, adapter or port scope
  • Generic support for inverting driver options (i.e. turn them off with '!')
  • Thorough PCI scan is now the default; the reason it wasn't so far was a delay in Virtualbox but that was never a problem on real hardware
  • SCSI emulation for ATAPI devices; this can be enabled on global, adapter or port scope
File size: 23.3 KB
Line 
1/******************************************************************************
2 * os2ahci.h - main header file for os2ahci driver
3 *
4 * Copyright (c) 2010 Christian Mueller. Parts copied from/inspired by the
5 * Linux AHCI driver; those parts are (c) Linux AHCI/ATA maintainers
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/* ----------------------------- include files ----------------------------- */
23
24/* IMPORTANT NOTE: The DDK headers require tight structure packing and this
25 * is controlled via compiler parameters. Thus, all stuctures in os2ahci.sys
26 * are expected to be byte-aligned without the need of explicit pragma pack()
27 * directives. Where possible, the structures are layed out such that words
28 * and dwords are aligned at least on 2-byte boundaries.
29 */
30
31#define INCL_NOPMAPI
32#define INCL_DOSINFOSEG
33#define INCL_NO_SCB
34#define INCL_DOSERRORS
35#include <os2.h>
36#include <dos.h>
37#include <bseerr.h>
38#include <dskinit.h>
39#include <scb.h>
40
41#include <devhdr.h>
42#include <iorb.h>
43#include <strat2.h>
44#include <reqpkt.h>
45
46#ifdef __WATCOMC__
47/* include WATCOM specific DEVHELP stubs */
48#include <devhelp.h>
49#else
50#include <dhcalls.h>
51#endif
52
53#include <addcalls.h>
54#include <rmcalls.h>
55#include <devclass.h>
56#include <devcmd.h>
57#include <rmbase.h>
58
59#include "ahci.h"
60#include "version.h"
61
62/* -------------------------- macros and constants ------------------------- */
63
64#define MAX_AD 8 /* maximum number of adapters */
65
66/* Timer pool size. In theory, we need one timer per outstanding command plus
67 * a few miscellaneous timers but it's unlikely we'll ever have outstanding
68 * commands on all devices on all ports on all apapters -- this would be
69 * 8 * 32 * 32 = 8192 outstanding commands on a maximum of 8 * 32 * 15 = 3840
70 * devices and that's a bit of an exaggeration. It should be more than enough
71 * to have 128 timers.
72 */
73#define TIMER_COUNT 128
74#define TIMER_POOL_SIZE (sizeof(ADD_TIMER_POOL) + \
75 TIMER_COUNT * sizeof(ADD_TIMER_DATA))
76
77/* default command timeout (can be overwritten in the IORB) */
78#define DEFAULT_TIMEOUT 30000
79
80/* max/min macros */
81#define max(a, b) (a) > (b) ? (a) : (b)
82#define min(a, b) (a) < (b) ? (a) : (b)
83
84/* debug output macros */
85#define dprintf if (debug > 0) printf
86#define dphex if (debug > 0) phex
87#define ddprintf if (debug > 1) printf
88#define ddphex if (debug > 1) phex
89#define dddprintf if (debug > 2) printf
90#define dddphex if (debug > 2) phex
91
92/* adapter number from AD_INFO pointer; mainly for dprintf() purposes */
93#define ad_no(ai) (((u16) ai - (u16) ad_infos) / sizeof(*ai))
94
95/* Convert far function address into NPFN (the DDK needs this all over the
96 * place and just casting to NPFN will produce a "segment lost in conversion"
97 * warning. Since casting to a u32 is a bit nasty for function pointers and
98 * might have to be revised for different compilers, we'll use a central
99 * macro for this crap.
100 */
101#define mk_NPFN(func) (NPFN) (u32) (func)
102
103/* stdarg.h macros with explicit far pointers
104 *
105 * NOTE: The compiler pushes fixed arguments with 16 bits minimum, thus
106 * the last fixed argument (i.e. the one passed to va_start) must
107 * have at least 16 bits. Otherwise, the address calculation in
108 * va_start() will fail.
109 */
110typedef char _far *va_list;
111#define va_start(va, last) va = (va_list) (&last + 1)
112#define va_arg(va, type) ((type _far *) (va += sizeof(type)))[-1]
113#define va_end(va) va = 0
114
115/* ctype macros */
116#define isupper(ch) ((ch) >= 'A' && (ch) <= 'Z')
117#define tolower(ch) (isupper(ch) ? (ch) + ('a' - 'A') : (ch))
118
119/* stddef macros */
120#define offsetof(s, e) ((u16) &((s *) 0)->e)
121
122/* SMP spinlock compatibility macros for older DDKs using CLI/STI */
123#ifndef OS2AHCI_SMP
124#define DevHelp_CreateSpinLock(p_sph) *(p_sph) = 0
125#define DevHelp_FreeSpinLock(sph) 0
126
127#define DevHelp_AquireSpinLock(sph) if ((sph) != 0) \
128 panic("recursive spinlock"); \
129 (sph) = disable()
130
131#define DevHelp_ReleaseSpinLock(sph) if (sph) { \
132 (sph) = 0; \
133 enable(); \
134 }
135#endif
136
137/* shortcut macros */
138#define spin_lock(sl) DevHelp_AquireSpinLock(sl)
139#define spin_unlock(sl) DevHelp_ReleaseSpinLock(sl)
140
141/* Get AHCI port MMIO base from AD_INFO and port number. For the time being,
142 * MMIO addresses are assumed to be valid 16:16 pointers which implies
143 * that one GDT selector is allocated per adapter.
144 */
145#define port_base(ai, p) ((u8 _far *) (ai)->mmio + 0x100 + (p) * 0x80)
146
147/* Get address of port-specific DMA scratch buffer. The total size of all DMA
148 * buffers required for 32 ports exceeds 65536 bytes, thus we need multiple
149 * GDT selectors to access all port DMA scratch buffers and some logic to map
150 * a port number to the corresponding DMA scratch buffer address.
151 */
152#define PORT_DMA_BUFS_PER_SEG ((size_t) (65536UL / AHCI_PORT_PRIV_DMA_SZ))
153#define PORT_DMA_BUF_SEGS ((AHCI_MAX_PORTS + PORT_DMA_BUFS_PER_SEG - 1) \
154 / PORT_DMA_BUFS_PER_SEG)
155#define PORT_DMA_SEG_SIZE ((u32) PORT_DMA_BUFS_PER_SEG * \
156 (u32) AHCI_PORT_PRIV_DMA_SZ)
157
158#define port_dma_base(ai, p) \
159 ((AHCI_PORT_DMA _far *) ((ai)->dma_buf[(p) / PORT_DMA_BUFS_PER_SEG] + \
160 ((p) % PORT_DMA_BUFS_PER_SEG) * AHCI_PORT_PRIV_DMA_SZ))
161
162#define port_dma_base_phys(ai, p) \
163 ((ai)->dma_buf_phys + (u32) (p) * AHCI_PORT_PRIV_DMA_SZ)
164
165/* Convert an SATA adapter/port/device address into a 16-bit IORB unit handle
166 * (and the other way round). The mapping looks like this:
167 *
168 * mapping comment
169 * -----------------------------------------------------------------------
170 * 4 bits for the adapter current max is 8 adapters
171 * 4 bits for the port AHCI spec defines up to 32 ports
172 * 4 bits for the device SATA spec defines up to 15 devices behind PMP
173 */
174#define iorb_unit(a, p, d) ((((u16) (a) & 0x0fU) << 8) | \
175 (((u16) (p) & 0x0fU) << 4) | \
176 (((u16) (d) & 0x0fU)))
177#define iorb_unit_adapter(iorb) (((u16) (iorb)->UnitHandle >> 8) & 0x07U)
178#define iorb_unit_port(iorb) (((u16) (iorb)->UnitHandle >> 4) & 0x0fU)
179#define iorb_unit_device(iorb) ((u16) (iorb)->UnitHandle & 0x0fU)
180
181/*******************************************************************************
182 * Convenience macros for IORB processing functions
183 */
184/* is this IORB on driver or port level? */
185#define iorb_driver_level(iorb) ((iorb)->CommandCode == IOCC_CONFIGURATION)
186
187/* is this IORB to be inserted at the beginnig of the IORB queue? */
188#define iorb_priority(iorb) ((iorb)->CommandCode == IOCC_DEVICE_CONTROL && \
189 (iorb)->CommandModifier == IOCM_ABORT))
190
191/* access IORB ADD workspace */
192#define add_workspace(iorb) ((ADD_WORKSPACE _far *) &(iorb)->ADDWorkSpace)
193
194
195
196/******************************************************************************
197 * PCI generic IDs and macros
198 */
199#define PCI_ANY_ID 0xffffU
200#define PCI_VDEVICE(vendor, device) PCI_VENDOR_ID_##vendor, (device), \
201 PCI_ANY_ID, PCI_ANY_ID, 0, 0
202
203/******************************************************************************
204 * PCI vendor IDs for AHCI adapters known to this driver (copied from Linux
205 * pci_ids.h)
206 */
207#define PCI_VENDOR_ID_AL 0x10b9
208#define PCI_VENDOR_ID_AMD 0x1022
209#define PCI_VENDOR_ID_AT 0x1259
210#define PCI_VENDOR_ID_ATI 0x1002
211#define PCI_VENDOR_ID_ATT 0x11c1
212#define PCI_VENDOR_ID_CMD 0x1095
213#define PCI_VENDOR_ID_CT 0x102c
214#define PCI_VENDOR_ID_INTEL 0x8086
215#define PCI_VENDOR_ID_INITIO 0x1101
216#define PCI_VENDOR_ID_JMICRON 0x197B
217#define PCI_VENDOR_ID_MARVELL 0x11ab
218#define PCI_VENDOR_ID_NVIDIA 0x10de
219#define PCI_VENDOR_ID_PROMISE 0x105a
220#define PCI_VENDOR_ID_SI 0x1039
221#define PCI_VENDOR_ID_VIA 0x1106
222
223/******************************************************************************
224 * PCI class IDs we're interested in (copied from Linux pci_ids.h)
225 */
226#define PCI_BASE_CLASS_STORAGE 0x01
227#define PCI_CLASS_STORAGE_SCSI 0x0100
228#define PCI_CLASS_STORAGE_IDE 0x0101
229#define PCI_CLASS_STORAGE_FLOPPY 0x0102
230#define PCI_CLASS_STORAGE_IPI 0x0103
231#define PCI_CLASS_STORAGE_RAID 0x0104
232#define PCI_CLASS_STORAGE_SATA 0x0106
233#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
234#define PCI_CLASS_STORAGE_SAS 0x0107
235#define PCI_CLASS_STORAGE_OTHER 0x0180
236
237/******************************************************************************
238 * ANSI color code constants
239 */
240#define ANSI_CLR_BRIGHT "\x1b[1m"
241#define ANSI_CLR_RED "\x1b[31m"
242#define ANSI_CLR_GREEN "\x1b[32m"
243#define ANSI_CLR_BLUE "\x1b[34m"
244#define ANSI_CLR_CYAN "\x1b[36m"
245#define ANSI_CLR_WHITE "\x1b[37m"
246#define ANSI_RESET "\x1b[0m"
247
248/* ------------------------ typedefs and structures ------------------------ */
249
250typedef unsigned int size_t;
251
252/* PCI device information structure; this is used both for scanning and for
253 * identification purposes in 'AD_INFO'; based on the Linux pci_device_id
254 * structure but hard-wired to use board_* constants for 'driver_data'
255 */
256typedef struct {
257 u16 vendor; /* PCI device vendor/manufacturer */
258 u16 device; /* PCI device ID inside vendor scope */
259 u16 subvendor; /* subsystem vendor (unused so far) */
260 u16 subdevice; /* subsystem device (unused so far) */
261 u32 class; /* PCI device class */
262 u32 class_mask; /* bits to match when scanning for 'class' */
263 u32 board; /* AHCI controller board type (board_* constants) */
264 char *chipname; /* human readable chip ID string */
265} PCI_ID;
266
267/* IORB queue; since IORB queues are updated at interrupt time, the
268 * corresponding pointers (not the data they point to) need to be volatile.
269 */
270typedef struct {
271 IORBH _far *volatile root; /* root of request list */
272 IORBH _far *volatile tail; /* tail of request list */
273} IORB_QUEUE;
274
275/* port information structure */
276typedef struct {
277 IORB_QUEUE iorb_queue; /* IORB queue for this port */
278 unsigned dev_max : 4; /* maximum device number on this port (0-15) */
279 unsigned cmd_slot : 5; /* current command slot index (using round-
280 * robin indexes to prevent starvation) */
281
282 volatile u32 ncq_cmds; /* bitmap for NCQ commands issued */
283 volatile u32 reg_cmds; /* bitmap for regular commands issued */
284
285 struct {
286 unsigned allocated : 1; /* if != 0, device is allocated */
287 unsigned present : 1; /* if != 0, device is present */
288 unsigned lba48 : 1; /* if != 0, device supports 48-bit LBA */
289 unsigned atapi : 1; /* if != 0, this is an ATAPI device */
290 unsigned atapi_16 : 1; /* if != 0, device suports 16-byte cmds */
291 unsigned removable : 1; /* if != 0, device has removable media */
292 unsigned dev_type : 5; /* device type (UIB_TYPE_* in iorb.h) */
293 unsigned ncq_max : 5; /* maximum tag number for queued commands */
294 UNITINFO _far *unit_info; /* pointer to modified unit info */
295 } devs[15];
296} P_INFO;
297
298/* adapter information structure */
299typedef struct {
300 PCI_ID *pci; /* pointer to corresponding PCI ID */
301
302 unsigned port_max : 5; /* maximum port number (0-31) */
303 unsigned cmd_max : 5; /* maximum cmd slot number (0-31) */
304 unsigned port_scan_done : 1; /* if != 0, port scan already done */
305 unsigned busy : 1; /* if != 0, adapter is busy */
306
307 u32 port_map; /* bitmap of active ports */
308
309 /* initial adapter configuration from BIOS */
310 u32 bios_config[HOST_CAP2 / sizeof(u32) + 1];
311
312 u32 cap; /* working copy of CAP register */
313 u32 cap2; /* working copy of CAP2 register */
314 u32 flags; /* adapter flags */
315
316 HRESOURCE rm_adh; /* resource handle for adapter */
317 HRESOURCE rm_mmio; /* resource handle for MMIO */
318 HRESOURCE rm_irq; /* resource handle for IRQ */
319
320 u8 bus; /* PCI bus number */
321 u8 dev_func; /* PCI device and function number */
322 u16 irq; /* interrupt number */
323
324 u32 mmio_phys; /* physical address of MMIO region */
325 u8 _far *mmio; /* pointer to this adapter's MMIO region */
326
327 u32 dma_buf_phys; /* physical address of DMA scratch buffer */
328 u8 _far *dma_buf[PORT_DMA_BUF_SEGS]; /* DMA scatch buffer */
329
330 P_INFO ports[AHCI_MAX_PORTS]; /* SATA ports on this adapter */
331} AD_INFO;
332
333/* ADD workspace in IORB (must not exceed 16 bytes) */
334typedef struct {
335 void (*ppfunc)(IORBH _far *iorb); /* post-processing function */
336 void *buf; /* response buffer (e.g. for identify cmds) */
337 ULONG timer; /* timer for timeout procesing */
338 USHORT blocks; /* number of blocks to be transferred */
339 unsigned processing : 1; /* IORB is being processd */
340 unsigned idempotent : 1; /* IORB is idempotent (can be retried) */
341 unsigned queued_hw : 1; /* IORB has been queued to hardware */
342 unsigned no_ncq : 1; /* must not use native command queuing */
343 unsigned is_ncq : 1; /* should use native command queueing */
344 unsigned complete : 1; /* IORB has completed processing */
345 unsigned cmd_slot : 5; /* AHCI command slot for this IORB */
346} ADD_WORKSPACE;
347
348/* -------------------------- function prototypes -------------------------- */
349
350/* init.asm */
351extern u32 _cdecl readl (void _far *addr);
352extern u32 _cdecl writel (void _far *addr, u32 val);
353extern void _far * _cdecl memcpy (void _far *v_dst, void _far *v_src, int len);
354extern void _far * _cdecl memset (void _far *p, int ch, size_t len);
355extern void _cdecl _far restart_hook (void);
356extern void _cdecl _far reset_hook (void);
357extern void _cdecl _far engine_hook (void);
358
359/* os2ahci.c */
360extern USHORT init_drv (RPINITIN _far *req);
361extern USHORT gen_ioctl (RP_GENIOCTL _far *ioctl);
362extern USHORT exit_drv (int func);
363extern void _cdecl _far _loadds add_entry (IORBH _far *iorb);
364extern void trigger_engine (void);
365extern int trigger_engine_1 (void);
366extern void send_iorb (IORBH _far *iorb);
367extern void iocc_configuration (IORBH _far *iorb);
368extern void iocc_device_control (IORBH _far *iorb);
369extern void iocc_unit_control (IORBH _far *iorb);
370extern void iocm_device_table (IORBH _far *iorb);
371extern void iocc_geometry (IORBH _far *iorb);
372extern void iocc_execute_io (IORBH _far *iorb);
373extern void iocc_unit_status (IORBH _far *iorb);
374extern void iocc_adapter_passthru (IORBH _far *iorb);
375extern void iorb_queue_add (IORB_QUEUE _far *queue, IORBH _far *iorb);
376extern int iorb_queue_del (IORB_QUEUE _far *queue, IORBH _far *iorb);
377extern void iorb_seterr (IORBH _far *iorb, USHORT error_code);
378extern void iorb_done (IORBH _far *iorb);
379extern void iorb_complete (IORBH _far *iorb);
380extern void iorb_requeue (IORBH _far *iorb);
381extern void aws_free (ADD_WORKSPACE _far *aws);
382extern void lock_adapter (AD_INFO *ai);
383extern void unlock_adapter (AD_INFO *ai);
384extern void _cdecl _far timeout_callback (ULONG timer_handle, ULONG p1, ULONG p2);
385
386/* ahci.c */
387extern int ahci_save_bios_config (AD_INFO *ai);
388extern int ahci_restore_bios_config (AD_INFO *ai);
389extern int ahci_restore_initial_config (AD_INFO *ai);
390extern AHCI_PORT_CFG *ahci_save_port_config (AD_INFO *ai, int p);
391extern void ahci_restore_port_config (AD_INFO *ai, int p,
392 AHCI_PORT_CFG *pc);
393extern int ahci_enable_ahci (AD_INFO *ai);
394extern int ahci_scan_ports (AD_INFO *ai);
395extern int ahci_complete_init (AD_INFO *ai);
396extern int ahci_reset_port (AD_INFO *ai, int p, int ei);
397extern int ahci_start_port (AD_INFO *ai, int p, int ei);
398extern void ahci_start_fis_rx (AD_INFO *ai, int p);
399extern void ahci_start_engine (AD_INFO *ai, int p);
400extern int ahci_stop_port (AD_INFO *ai, int p);
401extern int ahci_stop_fis_rx (AD_INFO *ai, int p);
402extern int ahci_stop_engine (AD_INFO *ai, int p);
403extern int ahci_port_busy (AD_INFO *ai, int p);
404extern void ahci_exec_iorb (IORBH _far *iorb, int ncq_capable,
405 int (*func)(IORBH _far *, int));
406extern void ahci_exec_polled_iorb (IORBH _far *iorb,
407 int (*func)(IORBH _far *, int),
408 ULONG timeout);
409extern int ahci_exec_polled_cmd (AD_INFO *ai, int p, int d,
410 int timeout, int cmd, ...);
411extern int ahci_set_dev_idle (AD_INFO *ai, int p, int d, int idle);
412extern int ahci_flush_cache (AD_INFO *ai, int p, int d);
413
414extern int ahci_intr (u16 irq);
415extern void ahci_port_intr (AD_INFO *ai, int p);
416extern void ahci_error_intr (AD_INFO *ai, int p, u32 irq_stat);
417
418extern void ahci_get_geometry (IORBH _far *iorb);
419extern void ahci_unit_ready (IORBH _far *iorb);
420extern void ahci_read (IORBH _far *iorb);
421extern void ahci_verify (IORBH _far *iorb);
422extern void ahci_write (IORBH _far *iorb);
423extern void ahci_execute_cdb (IORBH _far *iorb);
424extern void ahci_execute_ata (IORBH _far *iorb);
425
426/* libc.c */
427extern void init_libc (void);
428extern void init_com (void);
429extern int vsprintf (char _far *buf, const char *fmt, va_list va);
430extern int sprintf (char _far *buf, const char *fmt, ...);
431extern void vfprintf (const char *fmt, va_list va);
432extern void _cdecl printf (const char *fmt, ...);
433extern void cprintf (const char *fmt, ...);
434extern void phex (const void _far *p, int len,
435 const char *fmt, ...);
436extern size_t strlen (const char _far *s);
437extern char _far *strcpy (char _far *dst, const char _far *src);
438extern int memcmp (void _far *p1, void _far *p2, size_t len);
439extern long strtol (const char _far *buf,
440 const char _far * _far *ep, int base);
441extern void *malloc (size_t len);
442extern void free (void *ptr);
443extern void mdelay_cal (void);
444extern void mdelay (u32 millies);
445extern void msleep (u32 millies);
446extern void panic (char *msg);
447extern int disable (void);
448extern void enable (void);
449
450/* pci.c */
451extern int add_pci_id (u16 vendor, u16 device);
452extern void scan_pci_bus (void);
453extern int pci_enable_int (UCHAR bus, UCHAR dev_func);
454extern void pci_hack_virtualbox(void);
455extern char *vendor_from_id (u16 vendor);
456extern char *device_from_id (u16 device);
457
458/* ctxhook.c */
459extern void _cdecl restart_ctxhook (ULONG parm);
460extern void _cdecl reset_ctxhook (ULONG parm);
461extern void _cdecl engine_ctxhook (ULONG parm);
462
463/* apm.c */
464extern void apm_init (void);
465extern void apm_suspend (void);
466extern void apm_resume (void);
467
468/* ioctl.c */
469extern USHORT ioctl_get_devlist (RP_GENIOCTL _far *ioctl);
470extern USHORT ioctl_passthrough (RP_GENIOCTL _far *ioctl);
471
472/* ---------------------------- global variables --------------------------- */
473
474extern char _cdecl end_of_data; /* label at the end of all data segments */
475extern void _cdecl _near end_of_code(); /* label at the end of all code segments */
476
477extern int debug; /* if != 0, print debug messages to COM1 */
478extern int thorough_scan; /* if != 0, perform thorough PCI scan */
479extern int init_reset; /* if != 0, reset ports during init */
480
481extern HDRIVER rm_drvh; /* resource manager driver handle */
482extern USHORT add_handle; /* adapter device driver handle */
483extern UCHAR timer_pool[]; /* timer pool */
484
485extern PCI_ID pci_ids[]; /* SATA adapter PCI IDs */
486extern ULONG drv_lock; /* driver-level spinlock */
487extern IORB_QUEUE driver_queue; /* driver-level IORB queue */
488extern AD_INFO ad_infos[]; /* adapter information list */
489extern int ad_info_cnt; /* number of entries in ad_infos[] */
490extern u16 ad_ignore; /* bitmap with adapters to be ignored */
491extern int init_complete; /* if != 0, initialization has completed */
492
493extern u16 com_base; /* debug COM port base address */
494
495/* port restart context hook and input data */
496extern ULONG restart_ctxhook_h;
497extern volatile u32 ports_to_restart[MAX_AD];
498
499/* port reset context hook and input data */
500extern ULONG reset_ctxhook_h;
501extern volatile u32 ports_to_reset[MAX_AD];
502extern IORB_QUEUE abort_queue;
503
504/* trigger engine context hook and input data */
505extern ULONG engine_ctxhook_h;
506
507/* apapter/port-specific options saved when parsing the command line */
508extern u8 emulate_scsi[MAX_AD][AHCI_MAX_PORTS];
509extern u8 disable_ncq[MAX_AD][AHCI_MAX_PORTS];
510extern u8 link_speed[MAX_AD][AHCI_MAX_PORTS];
511extern u8 link_power[MAX_AD][AHCI_MAX_PORTS];
512
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