source: trunk/src/os2ahci/os2ahci.h@ 209

Last change on this file since 209 was 209, checked in by David Azarewicz, 4 years ago

Debugging support changes.
File size: 23.7 KB
Line 
1/**
2 * os2ahci.h - main header file for os2ahci driver
3 *
4 * Copyright (c) 2011 thi.guten Software Development
5 * Copyright (c) 2011 Mensys B.V.
6 * Copyright (c) 2013-2021 David Azarewicz <david@88watts.net>
7 *
8 * Authors: Christian Mueller, Markus Thielen
9 *
10 * Parts copied from/inspired by the Linux AHCI driver;
11 * those parts are (c) Linux AHCI/ATA maintainers
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 */
27
28/* IMPORTANT NOTE: The DDK headers require tight structure packing and this
29 * is controlled via compiler parameters. Thus, all stuctures in os2ahci.add
30 * are expected to be byte-aligned without the need of explicit pragma pack()
31 * directives. Where possible, the structures are laid out such that words
32 * and dwords are aligned at least on 2-byte boundaries.
33 */
34
35/* Global feature defines
36 * DEBUG = enable debug logging routines to be compled in.
37 * LEGACY_APM = enable the legacy APM interface to be compiled in.
38 * Legacy APM support is not needed on eCS systems with ACPI and is more reliable without it enabled.
39 */
40//#define LEGACY_APM
41//#define DAZ_NEW_CODE
42
43#include "Dev32lib.h"
44#include "Dev32rmcalls.h"
45#include <Dev32iorb.h>
46#include "ahci.h"
47#include "ahci-idc.h"
48
49#define MAX_AD 8 /* maximum number of adapters */
50
51#define TIMER_COUNT 128
52
53/* default command timeout (can be overwritten in the IORB) */
54#define DEFAULT_TIMEOUT 30000
55
56/* Maximum number of retries for commands in the restart/reset context hooks.
57 *
58 * Please note that the corresponding variable in the ADD workspace is a bit
59 * field, thus increasing this value means increasing the size of the bit
60 * field. At the time of writing this comment the 'retries' variable was 2
61 * bits wide (i.e. a maximum number of 3 retries) and there was exactly one
62 * bit left before the ADD workspace structure would become too large...
63 */
64#define MAX_RETRIES 3
65
66#define DBG_ALWAYS 0x0000
67#define DBG_FUNCBEG 0x0001
68#define DBG_FUNCEND 0x0002
69#define DBG_ATTACH 0x0004
70#define DBG_DETAILED 0x0008
71#define DBG_INIT 0x0010
72#define DBG_SPECIAL 0x0020
73#define DBG_VERBOSE 0x0100
74#define DBG_ERROR_ALL 0x800000ff
75
76#define DBG_PREFIX "AHCI: "__func__
77
78/* debug output macros */
79#ifdef DEBUG
80#define DPRINTF(a,b,...) dprintf(a, b, ##__VA_ARGS__)
81#define DHEXDUMP(a,b,c,d,...) dHexDump(a, b, c, d, ##__VA_ARGS__)
82#define DUMP_HOST_REGS(l,a,b) {if (D32g_DbgLevel&l) ahci_dump_host_regs(a,b);}
83#define DUMP_PORT_REGS(l,a,b) {if (D32g_DbgLevel&l) ahci_dump_port_regs(a,b);}
84#else
85#define DPRINTF(a,b,...)
86#define DHEXDUMP(a,b,c,d,...)
87#define DUMP_HOST_REGS(l,a,b)
88#define DUMP_PORT_REGS(l,a,b)
89#endif
90
91/* adapter number from AD_INFO pointer; mainly for dprintf() purposes */
92#define ad_no(ai) ( ( (u32)ai - (u32)ad_infos ) / sizeof(*ai))
93
94#define MakeNear16PtrFromDiff(Base16, Base32, New32) \
95 ( ( CastFar16ToULONG(Base16) + ( (ULONG)(New32) - (ULONG)(Base32) ) ) & 0xffff)
96
97#define MakeFar16PtrFromDiff(Base16, Base32, New32) \
98 CastULONGToFar16(CastFar16ToULONG(Base16) + ((ULONG)(New32) - (ULONG)(Base32))))
99
100/* Takes the selector from the first parameter, and the offset specified
101 * in the second parameter, and returns a flat pointer
102 */
103extern void *MakeFlatFromNear16(void __far16 *, USHORT);
104#pragma aux MakeFlatFromNear16 = \
105 "mov ax, bx" \
106 "call Far16ToFlat" \
107 parm nomemory [eax] [bx] value [eax] modify nomemory exact [eax];
108
109/* stdarg.h macros with explicit far pointers */
110typedef char *va_list;
111#define va_start(va, last) va = (va_list) (&last + 1)
112#define va_arg(va, type) ((type *) (va += sizeof(type)))[-1]
113#define va_end(va) va = 0
114
115/* stddef macros */
116#define offsetof(s, e) ((u32)&((s *)0)->e)
117
118/* shortcut macros */
119#define spin_lock(sl) KernAcquireSpinLock(&sl)
120#define spin_unlock(sl) KernReleaseSpinLock(&sl)
121
122/* Get AHCI port MMIO base from AD_INFO and port number. */
123#define port_base(ai, p) ((u8 *) (ai)->mmio + 0x100 + (p) * 0x80)
124#define port_dma_base(ai, p) ((AHCI_PORT_DMA *) ((ai)->ports[(p)].dma_buf))
125#define port_dma_base_phys(ai, p) ((ai)->ports[p].dma_buf_phys)
126
127/* Convert an SATA adapter/port/device address into a 16-bit IORB unit handle
128 * (and the other way round). The mapping looks like this:
129 *
130 * mapping comment
131 * -----------------------------------------------------------------------
132 * 4 bits for the adapter current max is 8 adapters
133 * 4 bits for the port AHCI spec defines up to 32 ports
134 * 4 bits for the device SATA spec defines up to 15 devices behind PMP
135 */
136#define iorb_unit(a, p, d) ((((u16) (a) & 0x0fU) << 8) | \
137 (((u16) (p) & 0x0fU) << 4) | \
138 (((u16) (d) & 0x0fU)))
139#define iorb_unit_adapter(iorb) (((iorb)->UnitHandle >> 8) & 0x07)
140#define iorb_unit_port(iorb) (((iorb)->UnitHandle >> 4) & 0x0f)
141#define iorb_unit_device(iorb) ((iorb)->UnitHandle & 0x0f)
142
143/*******************************************************************************
144 * Convenience macros for IORB processing functions
145 */
146/* is this IORB on driver or port level? */
147#define iorb_driver_level(iorb) ((iorb)->CommandCode == IOCC_CONFIGURATION)
148
149/* is this IORB to be inserted at the beginnig of the IORB queue? */
150#define iorb_priority(iorb) ((iorb)->CommandCode == IOCC_DEVICE_CONTROL && \
151 (iorb)->CommandModifier == IOCM_ABORT))
152
153/* access IORB ADD workspace */
154#define add_workspace(iorb) ((ADD_WORKSPACE *) &(iorb)->ADDWorkSpace)
155
156
157
158/******************************************************************************
159 * PCI generic IDs and macros
160 */
161#define PCI_ANY_ID 0xffffU
162#define PCI_VDEVICE(vendor, device) PCI_VENDOR_ID_##vendor, (device), \
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0
164
165/******************************************************************************
166 * PCI vendor IDs for AHCI adapters known to this driver (copied from Linux
167 * pci_ids.h)
168 */
169#define PCI_VENDOR_ID_AL 0x10b9
170#define PCI_VENDOR_ID_AMD 0x1022
171#define PCI_VENDOR_ID_AT 0x1259
172#define PCI_VENDOR_ID_ATI 0x1002
173#define PCI_VENDOR_ID_ATT 0x11c1
174#define PCI_VENDOR_ID_CMD 0x1095
175#define PCI_VENDOR_ID_CT 0x102c
176#define PCI_VENDOR_ID_INTEL 0x8086
177#define PCI_VENDOR_ID_INITIO 0x1101
178#define PCI_VENDOR_ID_JMICRON 0x197B
179#define PCI_VENDOR_ID_MARVELL 0x11ab
180#define PCI_VENDOR_ID_NVIDIA 0x10de
181#define PCI_VENDOR_ID_PROMISE 0x105a
182#define PCI_VENDOR_ID_SI 0x1039
183#define PCI_VENDOR_ID_VIA 0x1106
184
185/******************************************************************************
186 * PCI class IDs we're interested in (copied from Linux pci_ids.h)
187 */
188#define PCI_BASE_CLASS_STORAGE 0x01
189#define PCI_CLASS_STORAGE_SCSI 0x0100
190#define PCI_CLASS_STORAGE_IDE 0x0101
191#define PCI_CLASS_STORAGE_FLOPPY 0x0102
192#define PCI_CLASS_STORAGE_IPI 0x0103
193#define PCI_CLASS_STORAGE_RAID 0x0104
194#define PCI_CLASS_STORAGE_SATA 0x0106
195#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
196#define PCI_CLASS_STORAGE_SAS 0x0107
197#define PCI_CLASS_STORAGE_OTHER 0x0180
198
199/******************************************************************************
200 * ANSI color code constants
201 */
202#define ANSI_CLR_BRIGHT "\x1b[1m"
203#define ANSI_CLR_RED "\x1b[31m"
204#define ANSI_CLR_GREEN "\x1b[32m"
205#define ANSI_CLR_BLUE "\x1b[34m"
206#define ANSI_CLR_CYAN "\x1b[36m"
207#define ANSI_CLR_WHITE "\x1b[37m"
208#define ANSI_RESET "\x1b[0m"
209
210
211/* ------------------------ typedefs and structures ------------------------ */
212
213/* PCI device information structure; this is used both for scanning and for
214 * identification purposes in 'AD_INFO'; based on the Linux pci_device_id
215 * structure but hard-wired to use board_* constants for 'driver_data'
216 */
217typedef struct {
218 u16 vendor; /* PCI device vendor/manufacturer */
219 u16 device; /* PCI device ID inside vendor scope */
220 u16 subvendor; /* subsystem vendor (unused so far) */
221 u16 subdevice; /* subsystem device (unused so far) */
222 u32 class; /* PCI device class */
223 u32 class_mask; /* bits to match when scanning for 'class' */
224 u32 board; /* AHCI controller board type (board_* constants) */
225 char *chipname; /* human readable chip ID string */
226} PCI_ID;
227
228/* IORB queue; since IORB queues are updated at interrupt time, the
229 * corresponding pointers (not the data they point to) need to be volatile.
230 */
231typedef struct {
232 IORBH FAR16DATA *volatile vRoot; /* root of request list */
233 IORBH FAR16DATA *volatile vTail; /* tail of request list */
234} IORB_QUEUE;
235
236typedef struct {
237 ULONG ulCylinders;
238 USHORT usHeadsPerCylinder;
239 USHORT usSectorsPerTrack;
240 ULONGLONG ullTotalSectors;
241 char *pMethod;
242} DEV_INFO;
243
244/* port information structure */
245typedef struct {
246 IORB_QUEUE iorb_queue; /* 00 IORB queue for this port */
247 unsigned dev_max : 4; /* 08 maximum device number on this port (0..AHCI_MAX_DEVS-1) */
248 unsigned cmd_slot : 5; /* current command slot index (using round-
249 * robin indexes to prevent starvation) */
250
251 volatile u32 ncq_cmds; /* 0c bitmap for NCQ commands issued */
252 volatile u32 reg_cmds; /* 10 bitmap for regular commands issued */
253 u32 dma_buf_phys; /* 14 physical address of DMA scratch buffer */
254 u8 *dma_buf; /* 18 DMA scatch buffers */
255 u32 unaligned_read_count;
256 u32 error_count;
257 u32 ulResetCount; /* added in 2.07 */
258
259 struct { /* 1c */
260 unsigned allocated :1; /* if != 0, device is allocated */
261 unsigned present :1; /* if != 0, device is present */
262 unsigned lba48 :1; /* if != 0, device supports 48-bit LBA */
263 unsigned atapi :1; /* if != 0, this is an ATAPI device */
264 unsigned atapi_16 :1; /* if != 0, device suports 16-byte cmds */
265 unsigned removable :1; /* if != 0, device has removable media */
266 unsigned dev_type :5; /* device type (UIB_TYPE_* in iorb.h) */
267 unsigned ncq_max :5; /* maximum tag number for queued commands */
268 unsigned ignored :1; /* if != 0, device is not MBR added in 2.06 */
269 UNITINFO *unit_info; /* pointer to modified unit info */
270 DEV_INFO dev_info;
271 char dev_name[AHCI_DEV_NAME_LEN];
272 } devs[AHCI_MAX_DEVS];
273} P_INFO;
274
275/* adapter information structure */
276typedef struct {
277 PCI_ID *pci; /* 00 pointer to corresponding PCI ID */
278
279 unsigned port_max : 5; /* 04 maximum port number (0..AHCI_MAX_PORTS-1) */
280 unsigned cmd_max : 5; /* maximum cmd slot number (0-31) */
281 unsigned port_scan_done : 1; /* if != 0, port scan already done */
282 unsigned busy : 1; /* if != 0, adapter is busy */
283 unsigned hw_ports : 6; /* number of ports as reported by the hardware */
284 unsigned int_set:1; /* interrupt has been set */
285
286 u32 port_map; /* 08 bitmap of active ports */
287 u16 pci_vendor; /* 0c */
288 u16 pci_device; /* 0e */
289
290 /* initial adapter configuration from BIOS */
291 u32 bios_config[HOST_CAP2 / sizeof(u32) + 1]; /* 10 0x24 / 4 + 1 = 0x0a dwords = 0x28 bytes*/
292
293 u32 cap; /* 38 working copy of CAP register */
294 u32 cap2; /* 3c working copy of CAP2 register */
295 u32 flags; /* 40 adapter flags */
296
297 HRESOURCE rm_adh; /* 44 resource handle for adapter */
298 HRESOURCE rm_bars[6]; /* 48 resource handle for MMIO and I/O BARs */
299
300 u16 bus_dev_func; /* 64 PCI bus number PCI device and function number */
301 u8 irq; /* 66 interrupt number */
302 u8 irq_pin; /* 67 irq pin */
303
304 u32 mmio_phys; /* 68 physical address of MMIO region */
305 u32 mmio_size; /* 6c size of MMIO region */
306 u8 *mmio; /* 70 pointer to this adapter's MMIO region */
307
308 P_INFO ports[AHCI_MAX_PORTS]; /* 74 SATA ports on this adapter */
309} AD_INFO;
310
311/* ADD workspace in IORB (must not exceed 16 bytes) */
312typedef struct {
313 void (*ppfunc)(IORBH FAR16DATA *vIorb, IORBH *pIorb); /* 00 post-processing function */
314 void *buf; /* 04 response buffer (e.g. for identify cmds) */
315 ULONG timer; /* 08 timer for timeout procesing */
316 USHORT blocks; /* 0c number of blocks to be transferred */
317 unsigned short processing :1; /* 0e IORB is being processd */
318 unsigned short idempotent :1; /* IORB is idempotent (can be retried) */
319 unsigned short fIs64bit :1; /* Transaction is a 64 bit operation */
320 unsigned short queued_hw :1; /* IORB has been queued to hardware */
321 unsigned short no_ncq :1; /* must not use native command queuing */
322 unsigned short is_ncq :1; /* should use native command queueing */
323 unsigned short complete :1; /* IORB has completed processing */
324 unsigned short unaligned :1; /* unaligned S/G; need to use transfer buffer */
325 unsigned short retries :2; /* number of retries for this command */
326 unsigned short cmd_slot :5; /* AHCI command slot for this IORB */
327} ADD_WORKSPACE; /* 10 */
328
329/* sg_memcpy() direction */
330typedef enum {
331 SG_TO_BUF, /* copy from S/G list to buffer */
332 BUF_TO_SG /* copy from buffer to S/G list */
333} SG_MEMCPY_DIRECTION;
334
335/* Define the size of a disk name. Disk Names are user defined names given to physical disk drives in the system. */
336#define DLA_TABLE_SIGNATURE1 0x424D5202L
337#define DLA_TABLE_SIGNATURE2 0x44464D50L
338#define DISK_NAME_SIZE 20
339
340typedef struct _DLA_Table_Sector { /* DTS */
341 ULONG DLA_Signature1; /* The magic signature (part 1) of a Drive Letter Assignment Table. */
342 ULONG DLA_Signature2; /* The magic signature (part 2) of a Drive Letter Assignment Table. */
343 ULONG DLA_CRC; /* The 32 bit CRC for this sector. Calculated assuming that this field and all unused space in the sector is 0. */
344 ULONG Disk_Serial_Number; /* The serial number assigned to this disk. */
345 ULONG Boot_Disk_Serial_Number;/* The serial number of the disk used to boot the system. This is for conflict resolution when multiple volumes
346 want the same drive letter. Since LVM.EXE will not let this situation happen, the only way to get this situation
347 is for the disk to have been altered by something other than LVM.EXE, or if a disk drive has been moved from one
348 machine to another. If the drive has been moved, then it should have a different Boot_Disk_Serial_Number. Thus,
349 we can tell which disk drive is the "foreign" drive and therefore reject its claim for the drive letter in question.
350 If we find that all of the claimaints have the same Boot_Disk_Serial_Number, then we must assign drive letters on
351 a first come, first serve basis. */
352 ULONG Install_Flags; /* Used by the Install program. */
353 ULONG Cylinders;
354 ULONG Heads_Per_Cylinder;
355 ULONG Sectors_Per_Track;
356 char Disk_Name[DISK_NAME_SIZE]; /* The name assigned to the disk containing this sector. */
357 UCHAR Reboot; /* For use by Install. Used to keep track of reboots initiated by install. */
358 BYTE Reserved[3]; /* Alignment. */
359 /* These are the four entries which correspond to the entries in the partition table. */
360} DLA_Table_Sector, *PDLA_Table_Sector;
361
362typedef struct _ahcistats_
363{
364 ULONG ulSize;
365 ULONG ulVersion;
366 ULONG ulTestCount3;
367 ULONG ulTestCount2;
368 ULONG ulTestCount1;
369} AHCISTATS;
370
371static inline unsigned long readl(void *a)
372{
373 return *(volatile unsigned long*)a;
374}
375
376static inline void writel(void *a, unsigned long v)
377{
378 *(volatile unsigned long*)a = v;
379}
380
381extern void shutdown_driver(void);
382
383/* os2ahci.c */
384extern USHORT init_drv(REQPACKET *req);
385extern USHORT gen_ioctl(REQPACKET *ioctl);
386extern USHORT char_dev_input(REQPACKET *rwrb);
387extern USHORT exit_drv(int func);
388extern USHORT sr_drv(int func);
389extern void add_entry(IORBH FAR16DATA *vIorb);
390extern void trigger_engine(void);
391extern int trigger_engine_1(void);
392extern void send_iorb(IORBH FAR16DATA *vIorb, IORBH *pIorb);
393extern void iocc_configuration (IORBH FAR16DATA *vIorb, IORBH *pIorb);
394extern void iocc_device_control(IORBH FAR16DATA *vIorb, IORBH *pIorb);
395extern void iocc_unit_control(IORBH FAR16DATA *vIorb, IORBH *pIorb);
396extern void iocm_device_table(IORBH FAR16DATA *vIorb, IORBH *pIorb);
397extern void iocc_geometry(IORBH FAR16DATA *vIorb, IORBH *pIorb);
398extern void iocc_execute_io(IORBH FAR16DATA *vIorb, IORBH *pIorb);
399extern void iocc_unit_status(IORBH FAR16DATA *vIorb, IORBH *pIorb);
400extern void iocc_adapter_passthru(IORBH FAR16DATA *vIorb, IORBH *pIorb);
401extern void iorb_queue_add(IORB_QUEUE *queue, IORBH FAR16DATA *vIorb, IORBH *pIorb);
402extern int iorb_queue_del(IORB_QUEUE *queue, IORBH FAR16DATA *vIorb);
403extern void iorb_seterr(IORBH *pIorb, USHORT error_code);
404extern void iorb_done(IORBH FAR16DATA *vIorb, IORBH *pIorb);
405extern void iorb_complete(IORBH FAR16DATA *vIorb, IORBH *pIorb);
406extern void iorb_requeue(IORBH *pIorb);
407extern void aws_free(ADD_WORKSPACE *aws);
408extern void lock_adapter(AD_INFO *ai);
409extern void unlock_adapter(AD_INFO *ai);
410extern void __syscall timeout_callback(ULONG timer_handle, ULONG p1);
411extern void __syscall reset_watchdog(ULONG timer_handle, ULONG p1);
412
413/* ahci.c */
414extern int ahci_config_caps(AD_INFO *ai);
415extern int ahci_save_bios_config(AD_INFO *ai);
416extern int ahci_restore_bios_config(AD_INFO *ai);
417extern int ahci_restore_initial_config(AD_INFO *ai);
418extern AHCI_PORT_CFG *ahci_save_port_config(AD_INFO *ai, int p);
419extern void ahci_restore_port_config(AD_INFO *ai, int p, AHCI_PORT_CFG *pc);
420extern int ahci_enable_ahci(AD_INFO *ai);
421extern int ahci_scan_ports(AD_INFO *ai);
422extern int ahci_complete_init(AD_INFO *ai);
423extern int ahci_reset_port(AD_INFO *ai, int p, int ei);
424extern int ahci_start_port(AD_INFO *ai, int p, int ei);
425extern void ahci_start_fis_rx(AD_INFO *ai, int p);
426extern void ahci_start_engine(AD_INFO *ai, int p);
427extern int ahci_stop_port(AD_INFO *ai, int p);
428extern int ahci_stop_fis_rx(AD_INFO *ai, int p);
429extern int ahci_stop_engine(AD_INFO *ai, int p);
430extern int ahci_port_busy(AD_INFO *ai, int p);
431extern void ahci_exec_iorb(IORBH FAR16DATA *vIorb, IORBH *pIorb, int ncq_capable, int (*func)(IORBH FAR16DATA *, IORBH *pIorb, int));
432extern void ahci_exec_polled_iorb(IORBH FAR16DATA *vIorb, IORBH *pIorb, int (*func)(IORBH FAR16DATA *, IORBH *pIorb, int), ULONG timeout);
433extern int ahci_exec_polled_cmd(AD_INFO *ai, int p, int d, int timeout, int cmd, ...);
434extern int ahci_set_dev_idle(AD_INFO *ai, int p, int d, int idle);
435extern int ahci_flush_cache(AD_INFO *ai, int p, int d);
436
437extern int ahci_intr(u32 irq);
438extern void ahci_port_intr(AD_INFO *ai, int p);
439extern void ahci_error_intr(AD_INFO *ai, int p, u32 irq_stat);
440
441extern void ahci_get_geometry(IORBH FAR16DATA *vIorb, IORBH *pIorb);
442extern void ahci_unit_ready(IORBH FAR16DATA *vIorb, IORBH *pIorb);
443extern void ahci_read(IORBH FAR16DATA *vIorb, IORBH *pIorb);
444extern void ahci_verify(IORBH FAR16DATA *vIorb, IORBH *pIorb);
445extern void ahci_write(IORBH FAR16DATA *vIorb, IORBH *pIorb);
446extern void ahci_execute_cdb(IORBH FAR16DATA *vIorb, IORBH *pIorb);
447extern void ahci_execute_ata(IORBH FAR16DATA *vIorb, IORBH *pIorb);
448extern void ahci_dump_host_regs(AD_INFO *ai, int bios_regs);
449extern void ahci_dump_port_regs(AD_INFO *ai, int p);
450extern int ahci_reset_controller(AD_INFO *ai);
451
452extern void sg_memcpy(SCATGATENTRY *sg_list, USHORT sg_cnt, ULONG sg_off, void *buf, USHORT len, SG_MEMCPY_DIRECTION dir);
453extern void panic(char *msg);
454
455/* trace.c */
456extern void build_user_info(void);
457
458/* pci.c */
459extern int add_pci_id(u16 vendor, u16 device);
460extern void scan_pci_bus(void);
461extern int pci_enable_int(USHORT BusDevFunc);
462extern void pci_hack_virtualbox(void);
463extern char *vendor_from_id(u16 vendor);
464extern char *device_from_id(u16 device);
465
466/* ctxhook.c */
467extern void _Syscall restart_ctxhook(ULONG parm);
468extern void _Syscall reset_ctxhook(ULONG parm);
469extern void _Syscall engine_ctxhook(ULONG parm);
470
471/* apm.c */
472extern void apm_init(void);
473extern void suspend(void);
474extern void resume(void);
475
476/* ioctl.c */
477extern USHORT ioctl_get_devlist(REQPACKET *ioctl);
478extern USHORT ioctl_passthrough(REQPACKET *ioctl);
479extern USHORT ioctl_gen_dsk(REQPACKET *ioctl);
480extern USHORT ioctl_smart(REQPACKET *ioctl);
481
482
483extern int thorough_scan; /* if != 0, perform thorough PCI scan */
484extern int init_reset; /* if != 0, reset ports during init */
485extern int force_write_cache; /* if != 0, force write cache */
486extern int iVerbose; /* if != 0, show some info during boot */
487extern int use_mbr_test;
488
489extern HDRIVER rm_drvh; /* resource manager driver handle */
490extern USHORT add_handle; /* adapter device driver handle */
491extern char drv_name[]; /* driver name as string ("OS2AHCI") */
492
493extern PCI_ID pci_ids[]; /* SATA adapter PCI IDs */
494extern SpinLock_t drv_lock; /* driver-level spinlock */
495extern ULONG com_lock; /* debug log spinlock */
496extern IORB_QUEUE driver_queue; /* driver-level IORB queue */
497extern AD_INFO ad_infos[]; /* adapter information list */
498extern int ad_info_cnt; /* number of entries in ad_infos[] */
499extern u16 ad_ignore; /* bitmap with adapters to be ignored */
500extern int init_complete; /* if != 0, initialization has completed */
501extern int suspended; /* indicates if the driver is suspended */
502extern int resume_sleep_flag;
503extern AHCISTATS AhciStats;
504
505/* port restart context hook and input data */
506extern ULONG restart_ctxhook_h;
507extern volatile u32 ports_to_restart[MAX_AD];
508
509/* port reset context hook and input data */
510extern ULONG reset_ctxhook_h;
511extern ULONG th_reset_watchdog;
512extern volatile u32 ports_to_reset[MAX_AD];
513extern IORB_QUEUE abort_queue;
514
515/* trigger engine context hook and input data */
516extern ULONG engine_ctxhook_h;
517
518/* apapter/port-specific options saved when parsing the command line */
519extern u8 emulate_scsi[MAX_AD][AHCI_MAX_PORTS];
520extern u8 enable_ncq[MAX_AD][AHCI_MAX_PORTS];
521extern u8 link_speed[MAX_AD][AHCI_MAX_PORTS];
522extern u8 link_power[MAX_AD][AHCI_MAX_PORTS];
523extern u8 track_size[MAX_AD][AHCI_MAX_PORTS];
524extern u8 port_ignore[MAX_AD][AHCI_MAX_PORTS];
525
526#ifdef DEBUG
527extern void DumpIorb(IORBH *pIorb);
528#endif
529
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