| 1 | /******************************************************************************
|
|---|
| 2 | * os2ahci.h - main header file for os2ahci driver
|
|---|
| 3 | *
|
|---|
| 4 | * Copyright (c) 2011 thi.guten Software Development
|
|---|
| 5 | * Copyright (c) 2011 Mensys B.V.
|
|---|
| 6 | *
|
|---|
| 7 | * Authors: Christian Mueller, Markus Thielen
|
|---|
| 8 | *
|
|---|
| 9 | * Parts copied from/inspired by the Linux AHCI driver;
|
|---|
| 10 | * those parts are (c) Linux AHCI/ATA maintainers
|
|---|
| 11 | *
|
|---|
| 12 | * This program is free software; you can redistribute it and/or modify
|
|---|
| 13 | * it under the terms of the GNU General Public License as published by
|
|---|
| 14 | * the Free Software Foundation; either version 2 of the License, or
|
|---|
| 15 | * (at your option) any later version.
|
|---|
| 16 | *
|
|---|
| 17 | * This program is distributed in the hope that it will be useful,
|
|---|
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|---|
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|---|
| 20 | * GNU General Public License for more details.
|
|---|
| 21 | *
|
|---|
| 22 | * You should have received a copy of the GNU General Public License
|
|---|
| 23 | * along with this program; if not, write to the Free Software
|
|---|
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|---|
| 25 | */
|
|---|
| 26 |
|
|---|
| 27 | /* ----------------------------- include files ----------------------------- */
|
|---|
| 28 |
|
|---|
| 29 | /* IMPORTANT NOTE: The DDK headers require tight structure packing and this
|
|---|
| 30 | * is controlled via compiler parameters. Thus, all stuctures in os2ahci.add
|
|---|
| 31 | * are expected to be byte-aligned without the need of explicit pragma pack()
|
|---|
| 32 | * directives. Where possible, the structures are laid out such that words
|
|---|
| 33 | * and dwords are aligned at least on 2-byte boundaries.
|
|---|
| 34 | */
|
|---|
| 35 |
|
|---|
| 36 | #define INCL_NOPMAPI
|
|---|
| 37 | #define INCL_DOSINFOSEG
|
|---|
| 38 | #define INCL_NO_SCB
|
|---|
| 39 | #define INCL_DOSERRORS
|
|---|
| 40 | #include <os2.h>
|
|---|
| 41 | #include <dos.h>
|
|---|
| 42 | #include <bseerr.h>
|
|---|
| 43 | #include <dskinit.h>
|
|---|
| 44 | #include <scb.h>
|
|---|
| 45 |
|
|---|
| 46 | #include <devhdr.h>
|
|---|
| 47 | #include <iorb.h>
|
|---|
| 48 | #include <strat2.h>
|
|---|
| 49 | #include <reqpkt.h>
|
|---|
| 50 |
|
|---|
| 51 | /* NOTE: (Rousseau)
|
|---|
| 52 | * The regular dhcalls.h from $(DDK)\base\h also works.
|
|---|
| 53 | * The devhelp.h from $(DDK)\base\h produces inline assembler errors.
|
|---|
| 54 | * The modified devhelp.h from ..\include works OK and is used because it
|
|---|
| 55 | * generates a slightly smaller driver image.
|
|---|
| 56 | */
|
|---|
| 57 | #ifdef __WATCOMC__
|
|---|
| 58 | /* include WATCOM specific DEVHELP stubs */
|
|---|
| 59 | #include <devhelp.h>
|
|---|
| 60 | #else
|
|---|
| 61 | #include <dhcalls.h>
|
|---|
| 62 | #endif
|
|---|
| 63 |
|
|---|
| 64 | #include <addcalls.h>
|
|---|
| 65 | #include <rmcalls.h>
|
|---|
| 66 | #include <devclass.h>
|
|---|
| 67 | #include <devcmd.h>
|
|---|
| 68 | #include <rmbase.h>
|
|---|
| 69 |
|
|---|
| 70 | #include "ahci.h"
|
|---|
| 71 | #include "ahci-idc.h"
|
|---|
| 72 |
|
|---|
| 73 | /* -------------------------- macros and constants ------------------------- */
|
|---|
| 74 |
|
|---|
| 75 | #define MAX_AD 8 /* maximum number of adapters */
|
|---|
| 76 |
|
|---|
| 77 | /* Timer pool size. In theory, we need one timer per outstanding command plus
|
|---|
| 78 | * a few miscellaneous timers but it's unlikely we'll ever have outstanding
|
|---|
| 79 | * commands on all devices on all ports on all apapters -- this would be
|
|---|
| 80 | * 8 * 32 * 32 = 8192 outstanding commands on a maximum of 8 * 32 * 15 = 3840
|
|---|
| 81 | * devices and that's a bit of an exaggeration. It should be more than enough
|
|---|
| 82 | * to have 128 timers.
|
|---|
| 83 | */
|
|---|
| 84 | #define TIMER_COUNT 128
|
|---|
| 85 | #define TIMER_POOL_SIZE (sizeof(ADD_TIMER_POOL) + \
|
|---|
| 86 | TIMER_COUNT * sizeof(ADD_TIMER_DATA))
|
|---|
| 87 |
|
|---|
| 88 | /* default command timeout (can be overwritten in the IORB) */
|
|---|
| 89 | #define DEFAULT_TIMEOUT 30000
|
|---|
| 90 |
|
|---|
| 91 | /* Maximum number of retries for commands in the restart/reset context hooks.
|
|---|
| 92 | *
|
|---|
| 93 | * Please note that the corresponding variable in the ADD workspace is a bit
|
|---|
| 94 | * field, thus increasing this value means increasing the size of the bit
|
|---|
| 95 | * field. At the time of writing this comment the 'retries' variable was 2
|
|---|
| 96 | * bits wide (i.e. a maximum number of 3 retries) and there was exactly one
|
|---|
| 97 | * bit left before the ADD workspace structure would become too large...
|
|---|
| 98 | */
|
|---|
| 99 | #define MAX_RETRIES 3
|
|---|
| 100 |
|
|---|
| 101 | /* max/min macros */
|
|---|
| 102 | #define max(a, b) (a) > (b) ? (a) : (b)
|
|---|
| 103 | #define min(a, b) (a) < (b) ? (a) : (b)
|
|---|
| 104 |
|
|---|
| 105 | /* debug output macros */
|
|---|
| 106 | #define dprintf if (debug > 0) printf
|
|---|
| 107 | #define dphex if (debug > 0) phex
|
|---|
| 108 | #define ddprintf if (debug > 1) printf
|
|---|
| 109 | #define ddphex if (debug > 1) phex
|
|---|
| 110 | #define dddprintf if (debug > 2) printf
|
|---|
| 111 | #define dddphex if (debug > 2) phex
|
|---|
| 112 |
|
|---|
| 113 | /* verbosity console print macros
|
|---|
| 114 | * (we use 'i' in ciprintf here to avoid name clash
|
|---|
| 115 | * with vprintf-like funcs)
|
|---|
| 116 | */
|
|---|
| 117 | #define ciprintf if (verbosity > 0) cprintf
|
|---|
| 118 | #define ciiprintf if (verbosity > 1) cprintf
|
|---|
| 119 |
|
|---|
| 120 | /* TRACE macros (for our internal ring buffer trace) */
|
|---|
| 121 | #define TRACE_ACTIVE (debug > 0 && com_base == 0)
|
|---|
| 122 |
|
|---|
| 123 | /* adapter number from AD_INFO pointer; mainly for dprintf() purposes */
|
|---|
| 124 | #define ad_no(ai) (((u16) ai - (u16) ad_infos) / sizeof(*ai))
|
|---|
| 125 |
|
|---|
| 126 | /* Convert far function address into NPFN (the DDK needs this all over the
|
|---|
| 127 | * place and just casting to NPFN will produce a "segment lost in conversion"
|
|---|
| 128 | * warning. Since casting to a u32 is a bit nasty for function pointers and
|
|---|
| 129 | * might have to be revised for different compilers, we'll use a central
|
|---|
| 130 | * macro for this crap.
|
|---|
| 131 | */
|
|---|
| 132 | #define mk_NPFN(func) (NPFN) (u32) (func)
|
|---|
| 133 |
|
|---|
| 134 | /* stdarg.h macros with explicit far pointers
|
|---|
| 135 | *
|
|---|
| 136 | * NOTE: The compiler pushes fixed arguments with 16 bits minimum, thus
|
|---|
| 137 | * the last fixed argument (i.e. the one passed to va_start) must
|
|---|
| 138 | * have at least 16 bits. Otherwise, the address calculation in
|
|---|
| 139 | * va_start() will fail.
|
|---|
| 140 | */
|
|---|
| 141 | typedef char _far *va_list;
|
|---|
| 142 | #define va_start(va, last) va = (va_list) (&last + 1)
|
|---|
| 143 | #define va_arg(va, type) ((type _far *) (va += sizeof(type)))[-1]
|
|---|
| 144 | #define va_end(va) va = 0
|
|---|
| 145 |
|
|---|
| 146 | /* ctype macros */
|
|---|
| 147 | #define isupper(ch) ((ch) >= 'A' && (ch) <= 'Z')
|
|---|
| 148 | #define tolower(ch) (isupper(ch) ? (ch) + ('a' - 'A') : (ch))
|
|---|
| 149 |
|
|---|
| 150 | /* stddef macros */
|
|---|
| 151 | #define offsetof(s, e) ((u16) &((s *) 0)->e)
|
|---|
| 152 |
|
|---|
| 153 | /* SMP spinlock compatibility macros for older DDKs using CLI/STI */
|
|---|
| 154 | #ifndef OS2AHCI_SMP
|
|---|
| 155 | #define DevHelp_CreateSpinLock(p_sph) *(p_sph) = 0
|
|---|
| 156 | #define DevHelp_FreeSpinLock(sph) 0
|
|---|
| 157 |
|
|---|
| 158 | #define DevHelp_AcquireSpinLock(sph) if ((sph) != 0) \
|
|---|
| 159 | panic("recursive spinlock"); \
|
|---|
| 160 | (sph) = disable()
|
|---|
| 161 |
|
|---|
| 162 | #define DevHelp_ReleaseSpinLock(sph) if (sph) { \
|
|---|
| 163 | (sph) = 0; \
|
|---|
| 164 | enable(); \
|
|---|
| 165 | }
|
|---|
| 166 | #endif
|
|---|
| 167 |
|
|---|
| 168 | /* shortcut macros */
|
|---|
| 169 | #define spin_lock(sl) DevHelp_AcquireSpinLock(sl)
|
|---|
| 170 | #define spin_unlock(sl) DevHelp_ReleaseSpinLock(sl)
|
|---|
| 171 |
|
|---|
| 172 | /* Get AHCI port MMIO base from AD_INFO and port number. For the time being,
|
|---|
| 173 | * MMIO addresses are assumed to be valid 16:16 pointers which implies
|
|---|
| 174 | * that one GDT selector is allocated per adapter.
|
|---|
| 175 | */
|
|---|
| 176 | #define port_base(ai, p) ((u8 _far *) (ai)->mmio + 0x100 + (p) * 0x80)
|
|---|
| 177 |
|
|---|
| 178 | /* Get address of port-specific DMA scratch buffer. The total size of all DMA
|
|---|
| 179 | * buffers required for 32 ports exceeds 65536 bytes, thus we need multiple
|
|---|
| 180 | * GDT selectors to access all port DMA scratch buffers and some logic to map
|
|---|
| 181 | * a port number to the corresponding DMA scratch buffer address.
|
|---|
| 182 | */
|
|---|
| 183 | #define PORT_DMA_BUFS_PER_SEG ((size_t) (65536UL / AHCI_PORT_PRIV_DMA_SZ))
|
|---|
| 184 | #define PORT_DMA_BUF_SEGS ((AHCI_MAX_PORTS + PORT_DMA_BUFS_PER_SEG - 1) \
|
|---|
| 185 | / PORT_DMA_BUFS_PER_SEG)
|
|---|
| 186 | #define PORT_DMA_SEG_SIZE ((u32) PORT_DMA_BUFS_PER_SEG * \
|
|---|
| 187 | (u32) AHCI_PORT_PRIV_DMA_SZ)
|
|---|
| 188 |
|
|---|
| 189 | #define port_dma_base(ai, p) \
|
|---|
| 190 | ((AHCI_PORT_DMA _far *) ((ai)->dma_buf[(p) / PORT_DMA_BUFS_PER_SEG] + \
|
|---|
| 191 | ((p) % PORT_DMA_BUFS_PER_SEG) * AHCI_PORT_PRIV_DMA_SZ))
|
|---|
| 192 |
|
|---|
| 193 | #define port_dma_base_phys(ai, p) \
|
|---|
| 194 | ((ai)->dma_buf_phys + (u32) (p) * AHCI_PORT_PRIV_DMA_SZ)
|
|---|
| 195 |
|
|---|
| 196 | /* Convert an SATA adapter/port/device address into a 16-bit IORB unit handle
|
|---|
| 197 | * (and the other way round). The mapping looks like this:
|
|---|
| 198 | *
|
|---|
| 199 | * mapping comment
|
|---|
| 200 | * -----------------------------------------------------------------------
|
|---|
| 201 | * 4 bits for the adapter current max is 8 adapters
|
|---|
| 202 | * 4 bits for the port AHCI spec defines up to 32 ports
|
|---|
| 203 | * 4 bits for the device SATA spec defines up to 15 devices behind PMP
|
|---|
| 204 | */
|
|---|
| 205 | #define iorb_unit(a, p, d) ((((u16) (a) & 0x0fU) << 8) | \
|
|---|
| 206 | (((u16) (p) & 0x0fU) << 4) | \
|
|---|
| 207 | (((u16) (d) & 0x0fU)))
|
|---|
| 208 | #define iorb_unit_adapter(iorb) (((u16) (iorb)->UnitHandle >> 8) & 0x07U)
|
|---|
| 209 | #define iorb_unit_port(iorb) (((u16) (iorb)->UnitHandle >> 4) & 0x0fU)
|
|---|
| 210 | #define iorb_unit_device(iorb) ((u16) (iorb)->UnitHandle & 0x0fU)
|
|---|
| 211 |
|
|---|
| 212 | /*******************************************************************************
|
|---|
| 213 | * Convenience macros for IORB processing functions
|
|---|
| 214 | */
|
|---|
| 215 | /* is this IORB on driver or port level? */
|
|---|
| 216 | #define iorb_driver_level(iorb) ((iorb)->CommandCode == IOCC_CONFIGURATION)
|
|---|
| 217 |
|
|---|
| 218 | /* is this IORB to be inserted at the beginnig of the IORB queue? */
|
|---|
| 219 | #define iorb_priority(iorb) ((iorb)->CommandCode == IOCC_DEVICE_CONTROL && \
|
|---|
| 220 | (iorb)->CommandModifier == IOCM_ABORT))
|
|---|
| 221 |
|
|---|
| 222 | /* access IORB ADD workspace */
|
|---|
| 223 | #define add_workspace(iorb) ((ADD_WORKSPACE _far *) &(iorb)->ADDWorkSpace)
|
|---|
| 224 |
|
|---|
| 225 |
|
|---|
| 226 |
|
|---|
| 227 | /******************************************************************************
|
|---|
| 228 | * PCI generic IDs and macros
|
|---|
| 229 | */
|
|---|
| 230 | #define PCI_ANY_ID 0xffffU
|
|---|
| 231 | #define PCI_VDEVICE(vendor, device) PCI_VENDOR_ID_##vendor, (device), \
|
|---|
| 232 | PCI_ANY_ID, PCI_ANY_ID, 0, 0
|
|---|
| 233 |
|
|---|
| 234 | /******************************************************************************
|
|---|
| 235 | * PCI vendor IDs for AHCI adapters known to this driver (copied from Linux
|
|---|
| 236 | * pci_ids.h)
|
|---|
| 237 | */
|
|---|
| 238 | #define PCI_VENDOR_ID_AL 0x10b9
|
|---|
| 239 | #define PCI_VENDOR_ID_AMD 0x1022
|
|---|
| 240 | #define PCI_VENDOR_ID_AT 0x1259
|
|---|
| 241 | #define PCI_VENDOR_ID_ATI 0x1002
|
|---|
| 242 | #define PCI_VENDOR_ID_ATT 0x11c1
|
|---|
| 243 | #define PCI_VENDOR_ID_CMD 0x1095
|
|---|
| 244 | #define PCI_VENDOR_ID_CT 0x102c
|
|---|
| 245 | #define PCI_VENDOR_ID_INTEL 0x8086
|
|---|
| 246 | #define PCI_VENDOR_ID_INITIO 0x1101
|
|---|
| 247 | #define PCI_VENDOR_ID_JMICRON 0x197B
|
|---|
| 248 | #define PCI_VENDOR_ID_MARVELL 0x11ab
|
|---|
| 249 | #define PCI_VENDOR_ID_NVIDIA 0x10de
|
|---|
| 250 | #define PCI_VENDOR_ID_PROMISE 0x105a
|
|---|
| 251 | #define PCI_VENDOR_ID_SI 0x1039
|
|---|
| 252 | #define PCI_VENDOR_ID_VIA 0x1106
|
|---|
| 253 |
|
|---|
| 254 | /******************************************************************************
|
|---|
| 255 | * PCI class IDs we're interested in (copied from Linux pci_ids.h)
|
|---|
| 256 | */
|
|---|
| 257 | #define PCI_BASE_CLASS_STORAGE 0x01
|
|---|
| 258 | #define PCI_CLASS_STORAGE_SCSI 0x0100
|
|---|
| 259 | #define PCI_CLASS_STORAGE_IDE 0x0101
|
|---|
| 260 | #define PCI_CLASS_STORAGE_FLOPPY 0x0102
|
|---|
| 261 | #define PCI_CLASS_STORAGE_IPI 0x0103
|
|---|
| 262 | #define PCI_CLASS_STORAGE_RAID 0x0104
|
|---|
| 263 | #define PCI_CLASS_STORAGE_SATA 0x0106
|
|---|
| 264 | #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
|
|---|
| 265 | #define PCI_CLASS_STORAGE_SAS 0x0107
|
|---|
| 266 | #define PCI_CLASS_STORAGE_OTHER 0x0180
|
|---|
| 267 |
|
|---|
| 268 | /******************************************************************************
|
|---|
| 269 | * ANSI color code constants
|
|---|
| 270 | */
|
|---|
| 271 | #define ANSI_CLR_BRIGHT "\x1b[1m"
|
|---|
| 272 | #define ANSI_CLR_RED "\x1b[31m"
|
|---|
| 273 | #define ANSI_CLR_GREEN "\x1b[32m"
|
|---|
| 274 | #define ANSI_CLR_BLUE "\x1b[34m"
|
|---|
| 275 | #define ANSI_CLR_CYAN "\x1b[36m"
|
|---|
| 276 | #define ANSI_CLR_WHITE "\x1b[37m"
|
|---|
| 277 | #define ANSI_RESET "\x1b[0m"
|
|---|
| 278 |
|
|---|
| 279 |
|
|---|
| 280 | /* ------------------------ typedefs and structures ------------------------ */
|
|---|
| 281 |
|
|---|
| 282 | typedef unsigned int size_t;
|
|---|
| 283 |
|
|---|
| 284 | /* PCI device information structure; this is used both for scanning and for
|
|---|
| 285 | * identification purposes in 'AD_INFO'; based on the Linux pci_device_id
|
|---|
| 286 | * structure but hard-wired to use board_* constants for 'driver_data'
|
|---|
| 287 | */
|
|---|
| 288 | typedef struct {
|
|---|
| 289 | u16 vendor; /* PCI device vendor/manufacturer */
|
|---|
| 290 | u16 device; /* PCI device ID inside vendor scope */
|
|---|
| 291 | u16 subvendor; /* subsystem vendor (unused so far) */
|
|---|
| 292 | u16 subdevice; /* subsystem device (unused so far) */
|
|---|
| 293 | u32 class; /* PCI device class */
|
|---|
| 294 | u32 class_mask; /* bits to match when scanning for 'class' */
|
|---|
| 295 | u32 board; /* AHCI controller board type (board_* constants) */
|
|---|
| 296 | char *chipname; /* human readable chip ID string */
|
|---|
| 297 | } PCI_ID;
|
|---|
| 298 |
|
|---|
| 299 | /* IORB queue; since IORB queues are updated at interrupt time, the
|
|---|
| 300 | * corresponding pointers (not the data they point to) need to be volatile.
|
|---|
| 301 | */
|
|---|
| 302 | typedef struct {
|
|---|
| 303 | IORBH _far *volatile root; /* root of request list */
|
|---|
| 304 | IORBH _far *volatile tail; /* tail of request list */
|
|---|
| 305 | } IORB_QUEUE;
|
|---|
| 306 |
|
|---|
| 307 | /* port information structure */
|
|---|
| 308 | typedef struct {
|
|---|
| 309 | IORB_QUEUE iorb_queue; /* IORB queue for this port */
|
|---|
| 310 | unsigned dev_max : 4; /* maximum device number on this port (0-15) */
|
|---|
| 311 | unsigned cmd_slot : 5; /* current command slot index (using round-
|
|---|
| 312 | * robin indexes to prevent starvation) */
|
|---|
| 313 |
|
|---|
| 314 | volatile u32 ncq_cmds; /* bitmap for NCQ commands issued */
|
|---|
| 315 | volatile u32 reg_cmds; /* bitmap for regular commands issued */
|
|---|
| 316 |
|
|---|
| 317 | struct {
|
|---|
| 318 | unsigned allocated : 1; /* if != 0, device is allocated */
|
|---|
| 319 | unsigned present : 1; /* if != 0, device is present */
|
|---|
| 320 | unsigned lba48 : 1; /* if != 0, device supports 48-bit LBA */
|
|---|
| 321 | unsigned atapi : 1; /* if != 0, this is an ATAPI device */
|
|---|
| 322 | unsigned atapi_16 : 1; /* if != 0, device suports 16-byte cmds */
|
|---|
| 323 | unsigned removable : 1; /* if != 0, device has removable media */
|
|---|
| 324 | unsigned dev_type : 5; /* device type (UIB_TYPE_* in iorb.h) */
|
|---|
| 325 | unsigned ncq_max : 5; /* maximum tag number for queued commands */
|
|---|
| 326 | UNITINFO _far *unit_info; /* pointer to modified unit info */
|
|---|
| 327 | } devs[15];
|
|---|
| 328 | } P_INFO;
|
|---|
| 329 |
|
|---|
| 330 | /* adapter information structure */
|
|---|
| 331 | typedef struct {
|
|---|
| 332 | PCI_ID *pci; /* pointer to corresponding PCI ID */
|
|---|
| 333 |
|
|---|
| 334 | unsigned port_max : 5; /* maximum port number (0-31) */
|
|---|
| 335 | unsigned cmd_max : 5; /* maximum cmd slot number (0-31) */
|
|---|
| 336 | unsigned port_scan_done : 1; /* if != 0, port scan already done */
|
|---|
| 337 | unsigned busy : 1; /* if != 0, adapter is busy */
|
|---|
| 338 |
|
|---|
| 339 | u32 port_map; /* bitmap of active ports */
|
|---|
| 340 |
|
|---|
| 341 | /* initial adapter configuration from BIOS */
|
|---|
| 342 | u32 bios_config[HOST_CAP2 / sizeof(u32) + 1];
|
|---|
| 343 |
|
|---|
| 344 | u32 cap; /* working copy of CAP register */
|
|---|
| 345 | u32 cap2; /* working copy of CAP2 register */
|
|---|
| 346 | u32 flags; /* adapter flags */
|
|---|
| 347 |
|
|---|
| 348 | HRESOURCE rm_adh; /* resource handle for adapter */
|
|---|
| 349 | HRESOURCE rm_bars[6]; /* resource handle for MMIO and I/O BARs */
|
|---|
| 350 | HRESOURCE rm_irq; /* resource handle for IRQ */
|
|---|
| 351 |
|
|---|
| 352 | u8 bus; /* PCI bus number */
|
|---|
| 353 | u8 dev_func; /* PCI device and function number */
|
|---|
| 354 | u16 irq; /* interrupt number */
|
|---|
| 355 |
|
|---|
| 356 | u32 mmio_phys; /* physical address of MMIO region */
|
|---|
| 357 | u32 mmio_size; /* size of MMIO region */
|
|---|
| 358 | u8 _far *mmio; /* pointer to this adapter's MMIO region */
|
|---|
| 359 |
|
|---|
| 360 | u32 dma_buf_phys; /* physical address of DMA scratch buffer */
|
|---|
| 361 | u8 _far *dma_buf[PORT_DMA_BUF_SEGS]; /* DMA scatch buffer */
|
|---|
| 362 |
|
|---|
| 363 | P_INFO ports[AHCI_MAX_PORTS]; /* SATA ports on this adapter */
|
|---|
| 364 | } AD_INFO;
|
|---|
| 365 |
|
|---|
| 366 | /* ADD workspace in IORB (must not exceed 16 bytes) */
|
|---|
| 367 | typedef struct {
|
|---|
| 368 | void (*ppfunc)(IORBH _far *iorb); /* post-processing function */
|
|---|
| 369 | void *buf; /* response buffer (e.g. for identify cmds) */
|
|---|
| 370 | ULONG timer; /* timer for timeout procesing */
|
|---|
| 371 | USHORT blocks; /* number of blocks to be transferred */
|
|---|
| 372 | unsigned processing : 1; /* IORB is being processd */
|
|---|
| 373 | unsigned idempotent : 1; /* IORB is idempotent (can be retried) */
|
|---|
| 374 | unsigned queued_hw : 1; /* IORB has been queued to hardware */
|
|---|
| 375 | unsigned no_ncq : 1; /* must not use native command queuing */
|
|---|
| 376 | unsigned is_ncq : 1; /* should use native command queueing */
|
|---|
| 377 | unsigned complete : 1; /* IORB has completed processing */
|
|---|
| 378 | unsigned unaligned : 1; /* unaligned S/G; need to use transfer buffer */
|
|---|
| 379 | unsigned retries : 2; /* number of retries for this command */
|
|---|
| 380 | unsigned cmd_slot : 5; /* AHCI command slot for this IORB */
|
|---|
| 381 | } ADD_WORKSPACE;
|
|---|
| 382 |
|
|---|
| 383 | /* sg_memcpy() direction */
|
|---|
| 384 | typedef enum {
|
|---|
| 385 | SG_TO_BUF, /* copy from S/G list to buffer */
|
|---|
| 386 | BUF_TO_SG /* copy from buffer to S/G list */
|
|---|
| 387 | } SG_MEMCPY_DIRECTION;
|
|---|
| 388 |
|
|---|
| 389 | /* -------------------------- function prototypes -------------------------- */
|
|---|
| 390 |
|
|---|
| 391 | /* init.asm */
|
|---|
| 392 | extern u32 _cdecl readl (void _far *addr);
|
|---|
| 393 | extern u32 _cdecl writel (void _far *addr, u32 val);
|
|---|
| 394 | extern void _far * _cdecl memcpy (void _far *v_dst, void _far *v_src, int len);
|
|---|
| 395 | extern void _far * _cdecl memset (void _far *p, int ch, size_t len);
|
|---|
| 396 | extern void _cdecl _far restart_hook (void);
|
|---|
| 397 | extern void _cdecl _far reset_hook (void);
|
|---|
| 398 | extern void _cdecl _far engine_hook (void);
|
|---|
| 399 | extern void _cdecl _far asm_krnl_exit (void);
|
|---|
| 400 |
|
|---|
| 401 | /* os2ahci.c */
|
|---|
| 402 | extern USHORT init_drv (RPINITIN _far *req);
|
|---|
| 403 | extern USHORT gen_ioctl (RP_GENIOCTL _far *ioctl);
|
|---|
| 404 | extern USHORT char_dev_input (RP_RWV _far *rwrb);
|
|---|
| 405 | extern USHORT exit_drv (int func);
|
|---|
| 406 | extern void _cdecl _far _loadds add_entry (IORBH _far *iorb);
|
|---|
| 407 | extern void trigger_engine (void);
|
|---|
| 408 | extern int trigger_engine_1 (void);
|
|---|
| 409 | extern void send_iorb (IORBH _far *iorb);
|
|---|
| 410 | extern void iocc_configuration (IORBH _far *iorb);
|
|---|
| 411 | extern void iocc_device_control (IORBH _far *iorb);
|
|---|
| 412 | extern void iocc_unit_control (IORBH _far *iorb);
|
|---|
| 413 | extern void iocm_device_table (IORBH _far *iorb);
|
|---|
| 414 | extern void iocc_geometry (IORBH _far *iorb);
|
|---|
| 415 | extern void iocc_execute_io (IORBH _far *iorb);
|
|---|
| 416 | extern void iocc_unit_status (IORBH _far *iorb);
|
|---|
| 417 | extern void iocc_adapter_passthru (IORBH _far *iorb);
|
|---|
| 418 | extern void iorb_queue_add (IORB_QUEUE _far *queue, IORBH _far *iorb);
|
|---|
| 419 | extern int iorb_queue_del (IORB_QUEUE _far *queue, IORBH _far *iorb);
|
|---|
| 420 | extern void iorb_seterr (IORBH _far *iorb, USHORT error_code);
|
|---|
| 421 | extern void iorb_done (IORBH _far *iorb);
|
|---|
| 422 | extern void iorb_complete (IORBH _far *iorb);
|
|---|
| 423 | extern void iorb_requeue (IORBH _far *iorb);
|
|---|
| 424 | extern void aws_free (ADD_WORKSPACE _far *aws);
|
|---|
| 425 | extern void lock_adapter (AD_INFO *ai);
|
|---|
| 426 | extern void unlock_adapter (AD_INFO *ai);
|
|---|
| 427 | extern void _cdecl _far timeout_callback (ULONG timer_handle, ULONG p1, ULONG p2);
|
|---|
| 428 | extern void _cdecl _far reset_watchdog (ULONG timer_handle, ULONG p1, ULONG p2);
|
|---|
| 429 |
|
|---|
| 430 | /* ahci.c */
|
|---|
| 431 | extern int ahci_save_bios_config (AD_INFO *ai);
|
|---|
| 432 | extern int ahci_restore_bios_config (AD_INFO *ai);
|
|---|
| 433 | extern int ahci_restore_initial_config (AD_INFO *ai);
|
|---|
| 434 | extern AHCI_PORT_CFG *ahci_save_port_config (AD_INFO *ai, int p);
|
|---|
| 435 | extern void ahci_restore_port_config (AD_INFO *ai, int p,
|
|---|
| 436 | AHCI_PORT_CFG *pc);
|
|---|
| 437 | extern int ahci_enable_ahci (AD_INFO *ai);
|
|---|
| 438 | extern int ahci_scan_ports (AD_INFO *ai);
|
|---|
| 439 | extern int ahci_complete_init (AD_INFO *ai);
|
|---|
| 440 | extern int ahci_reset_port (AD_INFO *ai, int p, int ei);
|
|---|
| 441 | extern int ahci_start_port (AD_INFO *ai, int p, int ei);
|
|---|
| 442 | extern void ahci_start_fis_rx (AD_INFO *ai, int p);
|
|---|
| 443 | extern void ahci_start_engine (AD_INFO *ai, int p);
|
|---|
| 444 | extern int ahci_stop_port (AD_INFO *ai, int p);
|
|---|
| 445 | extern int ahci_stop_fis_rx (AD_INFO *ai, int p);
|
|---|
| 446 | extern int ahci_stop_engine (AD_INFO *ai, int p);
|
|---|
| 447 | extern int ahci_port_busy (AD_INFO *ai, int p);
|
|---|
| 448 | extern void ahci_exec_iorb (IORBH _far *iorb, int ncq_capable,
|
|---|
| 449 | int (*func)(IORBH _far *, int));
|
|---|
| 450 | extern void ahci_exec_polled_iorb (IORBH _far *iorb,
|
|---|
| 451 | int (*func)(IORBH _far *, int),
|
|---|
| 452 | ULONG timeout);
|
|---|
| 453 | extern int ahci_exec_polled_cmd (AD_INFO *ai, int p, int d,
|
|---|
| 454 | int timeout, int cmd, ...);
|
|---|
| 455 | extern int ahci_set_dev_idle (AD_INFO *ai, int p, int d, int idle);
|
|---|
| 456 | extern int ahci_flush_cache (AD_INFO *ai, int p, int d);
|
|---|
| 457 |
|
|---|
| 458 | extern int ahci_intr (u16 irq);
|
|---|
| 459 | extern void ahci_port_intr (AD_INFO *ai, int p);
|
|---|
| 460 | extern void ahci_error_intr (AD_INFO *ai, int p, u32 irq_stat);
|
|---|
| 461 |
|
|---|
| 462 | extern void ahci_get_geometry (IORBH _far *iorb);
|
|---|
| 463 | extern void ahci_unit_ready (IORBH _far *iorb);
|
|---|
| 464 | extern void ahci_read (IORBH _far *iorb);
|
|---|
| 465 | extern void ahci_verify (IORBH _far *iorb);
|
|---|
| 466 | extern void ahci_write (IORBH _far *iorb);
|
|---|
| 467 | extern void ahci_execute_cdb (IORBH _far *iorb);
|
|---|
| 468 | extern void ahci_execute_ata (IORBH _far *iorb);
|
|---|
| 469 |
|
|---|
| 470 | /* libc.c */
|
|---|
| 471 | extern void init_libc (void);
|
|---|
| 472 | extern void init_com (void);
|
|---|
| 473 | extern int vsprintf (char _far *buf, const char *fmt, va_list va);
|
|---|
| 474 | extern int sprintf (char _far *buf, const char *fmt, ...);
|
|---|
| 475 | extern void vfprintf (const char *fmt, va_list va);
|
|---|
| 476 | extern void _cdecl printf (const char *fmt, ...);
|
|---|
| 477 | extern void _cdecl printf_nts (const char *fmt, ...);
|
|---|
| 478 | extern void cprintf (const char *fmt, ...);
|
|---|
| 479 | extern void phex (const void _far *p, int len, const char *fmt, ...);
|
|---|
| 480 | extern size_t strlen (const char _far *s);
|
|---|
| 481 | extern char _far *strcpy (char _far *dst, const char _far *src);
|
|---|
| 482 | extern int memcmp (void _far *p1, void _far *p2, size_t len);
|
|---|
| 483 | extern void sg_memcpy (SCATGATENTRY _far *sg_list, USHORT sg_cnt,
|
|---|
| 484 | ULONG sg_off, void _far *buf, USHORT len,
|
|---|
| 485 | SG_MEMCPY_DIRECTION dir);
|
|---|
| 486 | extern long strtol (const char _far *buf,
|
|---|
| 487 | const char _far * _far *ep, int base);
|
|---|
| 488 | extern void *malloc (size_t len);
|
|---|
| 489 | extern void free (void *ptr);
|
|---|
| 490 | extern ULONG virt_to_phys (void _far *ptr);
|
|---|
| 491 | extern void mdelay_cal (void);
|
|---|
| 492 | extern void mdelay (u32 millies);
|
|---|
| 493 | extern void msleep (u32 millies);
|
|---|
| 494 | extern void panic (char *msg);
|
|---|
| 495 | extern int disable (void);
|
|---|
| 496 | extern void enable (void);
|
|---|
| 497 |
|
|---|
| 498 | /* trace.c */
|
|---|
| 499 | extern void trace_init (void);
|
|---|
| 500 | extern void trace_exit (void);
|
|---|
| 501 | extern void trace_write (u8 _far *s, int len);
|
|---|
| 502 | extern u16 trace_read (u8 _far *buf, u16 cb_buf);
|
|---|
| 503 | //NOT_USED extern u16 trace_bytes_avail(void);
|
|---|
| 504 | extern u16 trace_char_dev(RP_RWV _far *rwrb);
|
|---|
| 505 |
|
|---|
| 506 | /* pci.c */
|
|---|
| 507 | extern int add_pci_id (u16 vendor, u16 device);
|
|---|
| 508 | extern void scan_pci_bus (void);
|
|---|
| 509 | extern int pci_enable_int (UCHAR bus, UCHAR dev_func);
|
|---|
| 510 | extern void pci_hack_virtualbox(void);
|
|---|
| 511 | extern char *vendor_from_id (u16 vendor);
|
|---|
| 512 | extern char *device_from_id (u16 device);
|
|---|
| 513 | UCHAR pci_read_conf (UCHAR bus, UCHAR dev_func, UCHAR indx,
|
|---|
| 514 | UCHAR size, ULONG _far *val);
|
|---|
| 515 | UCHAR pci_write_conf (UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
|
|---|
| 516 | ULONG val);
|
|---|
| 517 |
|
|---|
| 518 | /* ctxhook.c */
|
|---|
| 519 | extern void _cdecl restart_ctxhook (ULONG parm);
|
|---|
| 520 | extern void _cdecl reset_ctxhook (ULONG parm);
|
|---|
| 521 | extern void _cdecl engine_ctxhook (ULONG parm);
|
|---|
| 522 |
|
|---|
| 523 | /* apm.c */
|
|---|
| 524 | extern void apm_init (void);
|
|---|
| 525 | extern void apm_suspend (void);
|
|---|
| 526 | extern void apm_resume (void);
|
|---|
| 527 |
|
|---|
| 528 | /* ioctl.c */
|
|---|
| 529 | extern USHORT ioctl_get_devlist (RP_GENIOCTL _far *ioctl);
|
|---|
| 530 | extern USHORT ioctl_passthrough (RP_GENIOCTL _far *ioctl);
|
|---|
| 531 | extern USHORT ioctl_gen_dsk (RP_GENIOCTL _far *ioctl);
|
|---|
| 532 | extern USHORT ioctl_smart (RP_GENIOCTL _far *ioctl);
|
|---|
| 533 |
|
|---|
| 534 |
|
|---|
| 535 | /* ---------------------------- global variables --------------------------- */
|
|---|
| 536 |
|
|---|
| 537 | extern char _cdecl end_of_data; /* label at the end of all data segments */
|
|---|
| 538 | extern void _cdecl _near end_of_code(); /* label at the end of all code segments */
|
|---|
| 539 |
|
|---|
| 540 | extern int debug; /* if != 0, print debug messages to COM1 */
|
|---|
| 541 | extern int thorough_scan; /* if != 0, perform thorough PCI scan */
|
|---|
| 542 | extern int init_reset; /* if != 0, reset ports during init */
|
|---|
| 543 | extern int force_write_cache; /* if != 0, force write cache */
|
|---|
| 544 | extern int verbosity; /* if != 0, show some info during boot */
|
|---|
| 545 |
|
|---|
| 546 | extern HDRIVER rm_drvh; /* resource manager driver handle */
|
|---|
| 547 | extern USHORT add_handle; /* adapter device driver handle */
|
|---|
| 548 | extern UCHAR timer_pool[]; /* timer pool */
|
|---|
| 549 | extern char drv_name[]; /* driver name as string ("OS2AHCI") */
|
|---|
| 550 |
|
|---|
| 551 | extern PCI_ID pci_ids[]; /* SATA adapter PCI IDs */
|
|---|
| 552 | extern ULONG drv_lock; /* driver-level spinlock */
|
|---|
| 553 | extern ULONG com_lock; /* debug log spinlock */
|
|---|
| 554 | extern IORB_QUEUE driver_queue; /* driver-level IORB queue */
|
|---|
| 555 | extern AD_INFO ad_infos[]; /* adapter information list */
|
|---|
| 556 | extern int ad_info_cnt; /* number of entries in ad_infos[] */
|
|---|
| 557 | extern u16 ad_ignore; /* bitmap with adapters to be ignored */
|
|---|
| 558 | extern int init_complete; /* if != 0, initialization has completed */
|
|---|
| 559 |
|
|---|
| 560 | extern u16 com_base; /* debug COM port base address */
|
|---|
| 561 |
|
|---|
| 562 | /* port restart context hook and input data */
|
|---|
| 563 | extern ULONG restart_ctxhook_h;
|
|---|
| 564 | extern volatile u32 ports_to_restart[MAX_AD];
|
|---|
| 565 |
|
|---|
| 566 | /* port reset context hook and input data */
|
|---|
| 567 | extern ULONG reset_ctxhook_h;
|
|---|
| 568 | extern ULONG th_reset_watchdog;
|
|---|
| 569 | extern volatile u32 ports_to_reset[MAX_AD];
|
|---|
| 570 | extern IORB_QUEUE abort_queue;
|
|---|
| 571 |
|
|---|
| 572 | /* trigger engine context hook and input data */
|
|---|
| 573 | extern ULONG engine_ctxhook_h;
|
|---|
| 574 |
|
|---|
| 575 | /* apapter/port-specific options saved when parsing the command line */
|
|---|
| 576 | extern u8 emulate_scsi[MAX_AD][AHCI_MAX_PORTS];
|
|---|
| 577 | extern u8 enable_ncq[MAX_AD][AHCI_MAX_PORTS];
|
|---|
| 578 | extern u8 link_speed[MAX_AD][AHCI_MAX_PORTS];
|
|---|
| 579 | extern u8 link_power[MAX_AD][AHCI_MAX_PORTS];
|
|---|
| 580 | extern u8 track_size[MAX_AD][AHCI_MAX_PORTS];
|
|---|
| 581 |
|
|---|
