| 1 | /**
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| 2 | * ahci.h - AHCI-specific constants for os2ahci.h
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| 3 | *
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| 4 | * Copyright (c) 2011 thi.guten Software Development
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| 5 | * Copyright (c) 2011 Mensys B.V.
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| 6 | * Copyright (c) 2013-2021 David Azarewicz <david@88watts.net>
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| 7 | *
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| 8 | * Authors: Christian Mueller, Markus Thielen
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| 9 | *
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| 10 | * Parts copied from/inspired by the Linux AHCI driver;
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| 11 | * those parts are (c) Linux AHCI/ATA maintainers
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| 12 | *
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| 13 | * This program is free software; you can redistribute it and/or modify
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| 14 | * it under the terms of the GNU General Public License as published by
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| 15 | * the Free Software Foundation; either version 2 of the License, or
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| 16 | * (at your option) any later version.
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| 17 | *
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| 18 | * This program is distributed in the hope that it will be useful,
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| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 21 | * GNU General Public License for more details.
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| 22 | *
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| 23 | * You should have received a copy of the GNU General Public License
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| 24 | * along with this program; if not, write to the Free Software
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| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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| 26 | */
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| 27 |
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| 28 |
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| 29 | /******************************************************************************
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| 30 | * device prefix strings for Resource Manager
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| 31 | */
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| 32 | #define RM_HD_PREFIX "HD_(%d,%d) "
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| 33 | #define RM_HD_PREFIX_LEN (sizeof(RM_HD_PREFIX) - 1)
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| 34 | #define RM_CD_PREFIX "CD_(%d,%d) "
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| 35 | #define RM_CD_PREFIX_LEN (sizeof(RM_CD_PREFIX) - 1)
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| 36 | #define RM_TAPE_PREFIX "TAPE_(%d,%d) "
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| 37 | #define RM_TAPE_PREFIX_LEN (sizeof(RM_TAPE_PREFIX) - 1)
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| 38 | #define RM_MAX_PREFIX_LEN RM_TAPE_PREFIX_LEN
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| 39 |
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| 40 | /******************************************************************************
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| 41 | * AHCI flags and constants; those were initially copied from the Linux AHCI
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| 42 | * driver but converted to macros because enums are 16 bits for OS/2 drivers
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| 43 | * (unless we use KEE and a 32-bit compiler, which we don't)
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| 44 | *
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| 45 | * Changes from the Linux source:
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| 46 | *
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| 47 | * - reduced AHCI_MAX_SG from 168 to 48 because the port-specific DMA scratch
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| 48 | * buffer needs to be less than 64K to allow mapping the whole DMA area to a
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| 49 | * 16-bit memory segment
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| 50 | *
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| 51 | * - added AHCI_MAX_SG_ELEMENT_LEN constant
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| 52 | *
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| 53 | * - replaced much of the top-level size/offset math with real structs and
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| 54 | * corresponding sizeof() directives.
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| 55 | */
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| 56 | #define AHCI_PCI_BAR 5
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| 57 | #define AHCI_MAX_PORTS 16 /* Spec says 32, but we only support 16 */
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| 58 | #define AHCI_MAX_DEVS 1 /* was 8. we only support 1 drive per port */
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| 59 | #define AHCI_MAX_SG 48 /* hardware max is 64K */
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| 60 | #define AHCI_MAX_SG_ELEMENT_LEN (1UL << 22)
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| 61 | #define AHCI_MAX_CMDS 32
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| 62 | #define AHCI_RX_FIS_SZ 256
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| 63 | #define AHCI_DEV_NAME_LEN 40
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| 64 |
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| 65 | /* port-specific DMA scratch buffer aligned to 1024 bytes */
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| 66 | //DAZ #define AHCI_PORT_PRIV_DMA_SZ (((sizeof(AHCI_PORT_DMA) + 1023U) / 1024U) * 1024U)
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| 67 | #define AHCI_PORT_PRIV_DMA_SZ sizeof(AHCI_PORT_DMA)
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| 68 |
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| 69 | #define AHCI_IRQ_ON_SG (1UL << 31)
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| 70 | #define AHCI_CMD_ATAPI (1UL << 5)
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| 71 | #define AHCI_CMD_WRITE (1UL << 6)
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| 72 | #define AHCI_CMD_PREFETCH (1UL << 7)
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| 73 | #define AHCI_CMD_RESET (1UL << 8)
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| 74 | #define AHCI_CMD_CLR_BUSY (1UL << 10)
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| 75 |
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| 76 | #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
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| 77 | #define RX_FIS_SDB 0x58 /* offset of SDB FIS data */
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| 78 | #define RX_FIS_UNK 0x60 /* offset of Unknown FIS data */
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| 79 |
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| 80 | #define board_ahci 0
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| 81 | #define board_ahci_vt8251 1
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| 82 | #define board_ahci_ign_iferr 2
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| 83 | #define board_ahci_sb600 3
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| 84 | #define board_ahci_mv 4
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| 85 | #define board_ahci_sb700 5 /* for SB700 and SB800 */
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| 86 | #define board_ahci_mcp65 6
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| 87 | #define board_ahci_nopmp 7
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| 88 | #define board_ahci_yesncq 8
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| 89 | #define board_ahci_nosntf 9
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| 90 |
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| 91 | /* global controller registers */
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| 92 | #define HOST_CAP 0x00 /* host capabilities */
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| 93 | #define HOST_CTL 0x04 /* global host control */
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| 94 | #define HOST_IRQ_STAT 0x08 /* interrupt status */
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| 95 | #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
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| 96 | #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
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| 97 | #define HOST_CCC 0x14 /* Command Completion Coalescing Control */
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| 98 | #define HOST_CCC_PORTS 0x18 /* CCC ports */
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| 99 | #define HOST_EM_LOC 0x1c /* Enclosure Management location */
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| 100 | #define HOST_EM_CTL 0x20 /* Enclosure Management Control */
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| 101 | #define HOST_CAP2 0x24 /* host capabilities, extended */
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| 102 | #define HOST_BOHC 0x28 /* BIOS hand off control and status */
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| 103 |
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| 104 | /* HOST_CTL bits */
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| 105 | #define HOST_RESET (1UL << 0) /* reset controller; self-clear */
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| 106 | #define HOST_IRQ_EN (1UL << 1) /* global IRQ enable */
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| 107 | #define HOST_AHCI_EN (1UL << 31) /* AHCI enabled */
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| 108 |
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| 109 | /* HOST_CAP bits */
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| 110 | #define HOST_CAP_SXS (1UL << 5) /* Supports External SATA */
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| 111 | #define HOST_CAP_EMS (1UL << 6) /* Enclosure Management support */
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| 112 | #define HOST_CAP_CCC (1UL << 7) /* Command Completion Coalescing */
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| 113 | #define HOST_CAP_PART (1UL << 13) /* Partial state capable */
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| 114 | #define HOST_CAP_SSC (1UL << 14) /* Slumber state capable */
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| 115 | #define HOST_CAP_PIO_MULTI (1UL << 15) /* PIO multiple DRQ support */
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| 116 | #define HOST_CAP_FBS (1UL << 16) /* FIS-based switching support */
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| 117 | #define HOST_CAP_PMP (1UL << 17) /* Port Multiplier support */
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| 118 | #define HOST_CAP_ONLY (1UL << 18) /* Supports AHCI mode only */
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| 119 | #define HOST_CAP_CLO (1UL << 24) /* Command List Override support */
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| 120 | #define HOST_CAP_LED (1UL << 25) /* Supports activity LED */
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| 121 | #define HOST_CAP_ALPM (1UL << 26) /* Aggressive Link PM support */
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| 122 | #define HOST_CAP_SSS (1UL << 27) /* Staggered Spin-up */
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| 123 | #define HOST_CAP_MPS (1UL << 28) /* Mechanical presence switch */
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| 124 | #define HOST_CAP_SNTF (1UL << 29) /* SNotification register */
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| 125 | #define HOST_CAP_NCQ (1UL << 30) /* Native Command Queueing */
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| 126 | #define HOST_CAP_64 (1UL << 31) /* PCI DAC (64-bit DMA) support */
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| 127 |
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| 128 | /* HOST_CAP2 bits */
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| 129 | #define HOST_CAP2_BOH (1UL << 0) /* BIOS/OS handoff supported */
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| 130 | #define HOST_CAP2_NVMHCI (1UL << 1) /* NVMHCI supported */
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| 131 | #define HOST_CAP2_APST (1UL << 2) /* Automatic partial to slumber */
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| 132 |
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| 133 | /* HOST_BOHC bits */
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| 134 | #define HOST_BOHC_BOS (1UL << 0) /* BIOS owned (semaphore bit) */
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| 135 | #define HOST_BOHC_OOS (1UL << 1) /* OS owned (semaphore bit) */
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| 136 | #define HOST_BOHC_SOOE (1UL << 2) /* SMI on ownership change enable */
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| 137 | #define HOST_BOHC_OOC (1UL << 3) /* OS ownership change */
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| 138 | #define HOST_BOHC_BB (1UL << 4) /* BIOS is busy changing ownership */
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| 139 |
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| 140 | /* registers for each SATA port */
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| 141 | #define PORT_LST_ADDR 0x00 /* command list DMA addr */
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| 142 | #define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
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| 143 | #define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
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| 144 | #define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
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| 145 | #define PORT_IRQ_STAT 0x10 /* interrupt status */
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| 146 | #define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
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| 147 | #define PORT_CMD 0x18 /* port command */
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| 148 | #define PORT_TFDATA 0x20 /* taskfile data */
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| 149 | #define PORT_SIG 0x24 /* device TF signature */
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| 150 | #define PORT_CMD_ISSUE 0x38 /* command issue */
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| 151 | #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
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| 152 | #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
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| 153 | #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
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| 154 | #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
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| 155 | #define PORT_SCR_NTF 0x3c /* SATA phy register: SNotification */
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| 156 |
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| 157 | /* PORT_IRQ_{STAT,MASK} bits */
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| 158 | #define PORT_IRQ_COLD_PRES (1UL << 31) /* cold presence detect */
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| 159 | #define PORT_IRQ_TF_ERR (1UL << 30) /* task file error */
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| 160 | #define PORT_IRQ_HBUS_ERR (1UL << 29) /* host bus fatal error */
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| 161 | #define PORT_IRQ_HBUS_DATA_ERR (1UL << 28) /* host bus data error */
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| 162 | #define PORT_IRQ_IF_ERR (1UL << 27) /* interface fatal error */
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| 163 | #define PORT_IRQ_IF_NONFATAL (1UL << 26) /* interface non-fatal error */
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| 164 | #define PORT_IRQ_OVERFLOW (1UL << 24) /* xfer exhausted available S/G */
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| 165 | #define PORT_IRQ_BAD_PMP (1UL << 23) /* incorrect port multiplier */
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| 166 | #define PORT_IRQ_PHYRDY (1UL << 22) /* PhyRdy changed */
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| 167 | #define PORT_IRQ_DEV_ILCK (1UL << 7) /* device interlock */
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| 168 | #define PORT_IRQ_CONNECT (1UL << 6) /* port connect change status */
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| 169 | #define PORT_IRQ_SG_DONE (1UL << 5) /* descriptor processed */
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| 170 | #define PORT_IRQ_UNK_FIS (1UL << 4) /* unknown FIS rx'd */
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| 171 | #define PORT_IRQ_SDB_FIS (1UL << 3) /* Set Device Bits FIS rx'd */
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| 172 | #define PORT_IRQ_DMAS_FIS (1UL << 2) /* DMA Setup FIS rx'd */
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| 173 | #define PORT_IRQ_PIOS_FIS (1UL << 1) /* PIO Setup FIS rx'd */
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| 174 | #define PORT_IRQ_D2H_REG_FIS (1UL << 0) /* D2H Register FIS rx'd */
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| 175 | #define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \
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| 176 | PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \
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| 177 | PORT_IRQ_UNK_FIS | PORT_IRQ_BAD_PMP)
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| 178 | #define PORT_IRQ_ERROR (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR | \
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| 179 | PORT_IRQ_OVERFLOW | PORT_IRQ_HBUS_DATA_ERR)
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| 180 | #define DEF_PORT_IRQ (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | \
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| 181 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | \
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| 182 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS)
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| 183 |
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| 184 | #define PORT_ERR_X (1UL << 26) /* Exchanged */
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| 185 | #define PORT_ERR_FIS (1UL << 25) /* Unknown FIS type */
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| 186 | #define PORT_ERR_TP (1UL << 24) /* Transport State Transition Error */
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| 187 | #define PORT_ERR_S (1UL << 23) /* Link Sequence Error */
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| 188 | #define PORT_ERR_H (1UL << 22) /* Handshake Error */
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| 189 | #define PORT_ERR_CRC (1UL << 21) /* CRC Error */
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| 190 | #define PORT_ERR_D (1UL << 20) /* Disparity Error */
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| 191 | #define PORT_ERR_B (1UL << 19) /* 10B to 8B Decode Error */
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| 192 | #define PORT_ERR_W (1UL << 18) /* Comm Wake */
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| 193 | #define PORT_ERR_PI (1UL << 17) /* Phy Internal Error */
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| 194 | #define PORT_ERR_N (1UL << 16) /* PhyRdy Change */
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| 195 | #define PORT_ERR_IE (1UL << 11) /* Internal Error */
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| 196 | #define PORT_ERR_P (1UL << 10) /* Protocol Error */
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| 197 | #define PORT_ERR_C (1UL << 9) /* Persistent Communication or Data Integrity Error */
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| 198 | #define PORT_ERR_TD (1UL << 8) /* Transient Data Integrity Error */
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| 199 | #define PORT_ERR_M (1UL << 1) /* Recovered Communications Error */
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| 200 | #define PORT_ERR_DI (1UL << 0) /* Recoverred Data Integrity Error */
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| 201 | #define PORT_ERR_FAIL_BITS (PORT_ERR_X | PORT_ERR_FIS | PORT_ERR_TP | PORT_ERR_S | PORT_ERR_H | PORT_ERR_CRC | \
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| 202 | PORT_ERR_D | PORT_ERR_B | PORT_ERR_W | PORT_ERR_PI | PORT_ERR_IE | PORT_ERR_P | \
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| 203 | PORT_ERR_C | PORT_ERR_TD)
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| 204 |
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| 205 | /* PORT_CMD bits */
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| 206 | #define PORT_CMD_ASP (1UL << 27) /* Aggressive Slumber/Partial */
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| 207 | #define PORT_CMD_ALPE (1UL << 26) /* Aggressive Link PM enable */
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| 208 | #define PORT_CMD_ATAPI (1UL << 24) /* Device is ATAPI */
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| 209 | #define PORT_CMD_PMP (1UL << 17) /* PMP attached */
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| 210 | #define PORT_CMD_LIST_ON (1UL << 15) /* cmd list DMA engine running */
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| 211 | #define PORT_CMD_FIS_ON (1UL << 14) /* FIS DMA engine running */
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| 212 | #define PORT_CMD_FIS_RX (1UL << 4) /* Enable FIS receive DMA engine */
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| 213 | #define PORT_CMD_CLO (1UL << 3) /* Command list override */
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| 214 | #define PORT_CMD_POWER_ON (1UL << 2) /* Power up device */
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| 215 | #define PORT_CMD_SPIN_UP (1UL << 1) /* Spin up device */
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| 216 | #define PORT_CMD_START (1UL << 0) /* Enable port DMA engine */
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| 217 |
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| 218 | #define PORT_CMD_ICC_MASK (0xfUL << 28) /* i/f ICC state mask */
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| 219 | #define PORT_CMD_ICC_ACTIVE (0x1UL << 28) /* Put i/f in active state */
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| 220 | #define PORT_CMD_ICC_PARTIAL (0x2UL << 28) /* Put i/f in partial state */
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| 221 | #define PORT_CMD_ICC_SLUMBER (0x6UL << 28) /* Put i/f in slumber state */
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| 222 |
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| 223 | /* driver status bits */
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| 224 | #define AHCI_HFLAG_NO_NCQ (1UL << 0) /* no native cmd queuing */
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| 225 | #define AHCI_HFLAG_IGN_IRQ_IF_ERR (1UL << 1) /* ignore IRQ_IF_ERR */
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| 226 | #define AHCI_HFLAG_IGN_SERR_INTERNAL (1UL << 2) /* ignore SERR_INTERNAL */
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| 227 | #define AHCI_HFLAG_32BIT_ONLY (1UL << 3) /* force 32bit */
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| 228 | #define AHCI_HFLAG_MV_PATA (1UL << 4) /* PATA port */
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| 229 | #define AHCI_HFLAG_NO_MSI (1UL << 5) /* no PCI MSI */
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| 230 | #define AHCI_HFLAG_NO_PMP (1UL << 6) /* no PMP */
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| 231 | #define AHCI_HFLAG_NO_HOTPLUG (1UL << 7) /* ignore PxSERR.DIAG.N */
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| 232 | #define AHCI_HFLAG_SECT255 (1UL << 8) /* max 255 sectors */
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| 233 | #define AHCI_HFLAG_YES_NCQ (1UL << 9) /* force NCQ cap on */
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| 234 | #define AHCI_HFLAG_NO_SUSPEND (1UL << 10) /* don't suspend */
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| 235 | #define AHCI_HFLAG_SRST_TOUT_IS_OFFLINE (1UL << 11) /* treat SRST timeout as
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| 236 | link offline */
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| 237 | #define AHCI_HFLAG_NO_SNTF (1UL << 12) /* no sntf */
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| 238 |
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| 239 | #define ICH_MAP 0x90 /* ICH MAP register */
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| 240 |
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| 241 | /* em constants */
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| 242 | #define EM_MAX_SLOTS 8
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| 243 | #define EM_MAX_RETRY 5
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| 244 |
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| 245 | /* em_ctl bits */
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| 246 | #define EM_CTL_RST (1UL << 9) /* Reset */
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| 247 | #define EM_CTL_TM (1UL << 8) /* Transmit Message */
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| 248 | #define EM_CTL_ALHD (1UL << 26) /* Activity LED */
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| 249 |
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| 250 | /* Primitive types
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| 251 | *
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| 252 | * Note: Since OS/2 is essentially an x86 OS and this driver, as well as the
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| 253 | * interface it's developed for, is based on x86 design patterns, we're
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| 254 | * not even going to start making a difference between little and big
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| 255 | * endian architectures. PCI is little endian, AHCI is little endian,
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| 256 | * x86 is little endian, and that's it.
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| 257 | */
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| 258 | typedef unsigned char u8;
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| 259 | typedef unsigned short u16;
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| 260 | typedef unsigned long u32;
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| 261 |
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| 262 | /* AHCI S/G structure */
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| 263 | typedef struct {
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| 264 | u32 addr; /* address of S/G element */
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| 265 | u32 addr_hi; /* address of S/G element (upper 32 bits) */
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| 266 | u32 reserved;
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| 267 | u32 size; /* size of S/G element - 1; the high 10 bits are flags:
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| 268 | * 31 : interrupt on completion of this S/G
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| 269 | * 30-22 : reserved */
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| 270 | } AHCI_SG;
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| 271 |
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| 272 | /* AHCI command header */
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| 273 | typedef struct {
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| 274 | u32 options; /* command options */
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| 275 | u32 status; /* command status */
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| 276 | u32 tbl_addr; /* command table address */
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| 277 | u32 tbl_addr_high; /* command table address (upper 32 bits) */
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| 278 | u32 reserved[4];
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| 279 | } AHCI_CMD_HDR;
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| 280 |
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| 281 | /* AHCI command table */
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| 282 | typedef struct {
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| 283 | u8 cmd_fis[64]; /* ATA command FIS */
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| 284 | u8 atapi_cmd[16]; /* ATAPI command */
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| 285 | u8 reserved[48];
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| 286 | AHCI_SG sg_list[AHCI_MAX_SG]; /* AHCI S/G list */
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| 287 | } AHCI_CMD_TBL;
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| 288 |
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| 289 | /* AHCI port DMA scratch area */
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| 290 | typedef struct {
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| 291 | AHCI_CMD_HDR cmd_hdr[AHCI_MAX_CMDS]; /* command headers */
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| 292 | u8 rx_fis[AHCI_RX_FIS_SZ]; /* FIS RX area */
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| 293 | AHCI_CMD_TBL cmd_tbl[AHCI_MAX_CMDS]; /* command table */
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| 294 | } AHCI_PORT_DMA;
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| 295 |
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| 296 | /* AHCI port BIOS configuration save area */
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| 297 | typedef struct {
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| 298 | u32 cmd_list; /* cmd list base address */
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| 299 | u32 cmd_list_h; /* cmd list base address high */
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| 300 | u32 fis_rx; /* FIS receive buffer */
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| 301 | u32 fis_rx_h; /* FIS receive bufffer high */
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| 302 | u32 irq_mask; /* IRQ mask */
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| 303 | u32 port_cmd; /* port engine status */
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| 304 | } AHCI_PORT_CFG;
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| 305 |
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