source: trunk/src/os2ahci/ahci.h@ 13

Last change on this file since 13 was 13, checked in by root, 15 years ago

latest NCQ changes from Christian
File size: 12.9 KB
Line 
1/******************************************************************************
2 * ahci.h - AHCI-specific constants for os2ahci.h
3 *
4 * Copyright (c) 2010 Christian Mueller. Parts copied from/inspired by the
5 * Linux AHCI driver; those parts are (c) Linux AHCI/ATA maintainers
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/* ----------------------------- include files ----------------------------- */
23
24/* -------------------------- macros and constants ------------------------- */
25
26/******************************************************************************
27 * AHCI flags and constants; those were initially copied from the Linux AHCI
28 * driver but converted to macros because enums are 16 bits for OS/2 drivers
29 * (unless we use KEE and a 32-bit compiler, which we don't)
30 *
31 * Changes from the Linux source:
32 *
33 * - reduced AHCI_MAX_SG from 168 to 48 because the port-specific DMA scratch
34 * buffer needs to be less than 64K to allow mapping the whole DMA area to a
35 * 16-bit memory segment
36 *
37 * - added AHCI_MAX_SG_ELEMENT_LEN constant
38 *
39 * - replaced much of the top-level size/offset math with real structs and
40 * corresponding sizeof() directives.
41 */
42#define AHCI_PCI_BAR 5
43#define AHCI_MAX_PORTS 32
44#define AHCI_MAX_SG 48 /* hardware max is 64K */
45#define AHCI_MAX_SG_ELEMENT_LEN (1UL << 22)
46#define AHCI_MAX_CMDS 32
47#define AHCI_RX_FIS_SZ 256
48
49/* port-specific DMA scratch buffer aligned to 1024 bytes */
50#define AHCI_PORT_PRIV_DMA_SZ (((sizeof(AHCI_PORT_DMA) + 1023U) / 1024U) * 1024U)
51
52#define AHCI_IRQ_ON_SG (1UL << 31)
53#define AHCI_CMD_ATAPI (1UL << 5)
54#define AHCI_CMD_WRITE (1UL << 6)
55#define AHCI_CMD_PREFETCH (1UL << 7)
56#define AHCI_CMD_RESET (1UL << 8)
57#define AHCI_CMD_CLR_BUSY (1UL << 10)
58
59#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
60#define RX_FIS_SDB 0x58 /* offset of SDB FIS data */
61#define RX_FIS_UNK 0x60 /* offset of Unknown FIS data */
62
63#define board_ahci 0
64#define board_ahci_vt8251 1
65#define board_ahci_ign_iferr 2
66#define board_ahci_sb600 3
67#define board_ahci_mv 4
68#define board_ahci_sb700 5 /* for SB700 and SB800 */
69#define board_ahci_mcp65 6
70#define board_ahci_nopmp 7
71#define board_ahci_yesncq 8
72#define board_ahci_nosntf 9
73
74/* global controller registers */
75#define HOST_CAP 0x00 /* host capabilities */
76#define HOST_CTL 0x04 /* global host control */
77#define HOST_IRQ_STAT 0x08 /* interrupt status */
78#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
79#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
80#define HOST_CCC 0x14 /* Command Completion Coalescing Control */
81#define HOST_CCC_PORTS 0x18 /* CCC ports */
82#define HOST_EM_LOC 0x1c /* Enclosure Management location */
83#define HOST_EM_CTL 0x20 /* Enclosure Management Control */
84#define HOST_CAP2 0x24 /* host capabilities, extended */
85
86/* HOST_CTL bits */
87#define HOST_RESET (1UL << 0) /* reset controller; self-clear */
88#define HOST_IRQ_EN (1UL << 1) /* global IRQ enable */
89#define HOST_AHCI_EN (1UL << 31) /* AHCI enabled */
90
91/* HOST_CAP bits */
92#define HOST_CAP_SXS (1UL << 5) /* Supports External SATA */
93#define HOST_CAP_EMS (1UL << 6) /* Enclosure Management support */
94#define HOST_CAP_CCC (1UL << 7) /* Command Completion Coalescing */
95#define HOST_CAP_PART (1UL << 13) /* Partial state capable */
96#define HOST_CAP_SSC (1UL << 14) /* Slumber state capable */
97#define HOST_CAP_PIO_MULTI (1UL << 15) /* PIO multiple DRQ support */
98#define HOST_CAP_FBS (1UL << 16) /* FIS-based switching support */
99#define HOST_CAP_PMP (1UL << 17) /* Port Multiplier support */
100#define HOST_CAP_ONLY (1UL << 18) /* Supports AHCI mode only */
101#define HOST_CAP_CLO (1UL << 24) /* Command List Override support */
102#define HOST_CAP_LED (1UL << 25) /* Supports activity LED */
103#define HOST_CAP_ALPM (1UL << 26) /* Aggressive Link PM support */
104#define HOST_CAP_SSS (1UL << 27) /* Staggered Spin-up */
105#define HOST_CAP_MPS (1UL << 28) /* Mechanical presence switch */
106#define HOST_CAP_SNTF (1UL << 29) /* SNotification register */
107#define HOST_CAP_NCQ (1UL << 30) /* Native Command Queueing */
108#define HOST_CAP_64 (1UL << 31) /* PCI DAC (64-bit DMA) support */
109
110/* HOST_CAP2 bits */
111#define HOST_CAP2_BOH (1UL << 0) /* BIOS/OS handoff supported */
112#define HOST_CAP2_NVMHCI (1UL << 1) /* NVMHCI supported */
113#define HOST_CAP2_APST (1UL << 2) /* Automatic partial to slumber */
114
115/* registers for each SATA port */
116#define PORT_LST_ADDR 0x00 /* command list DMA addr */
117#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
118#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
119#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
120#define PORT_IRQ_STAT 0x10 /* interrupt status */
121#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
122#define PORT_CMD 0x18 /* port command */
123#define PORT_TFDATA 0x20 /* taskfile data */
124#define PORT_SIG 0x24 /* device TF signature */
125#define PORT_CMD_ISSUE 0x38 /* command issue */
126#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
127#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
128#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
129#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
130#define PORT_SCR_NTF 0x3c /* SATA phy register: SNotification */
131
132/* PORT_IRQ_{STAT,MASK} bits */
133#define PORT_IRQ_COLD_PRES (1UL << 31) /* cold presence detect */
134#define PORT_IRQ_TF_ERR (1UL << 30) /* task file error */
135#define PORT_IRQ_HBUS_ERR (1UL << 29) /* host bus fatal error */
136#define PORT_IRQ_HBUS_DATA_ERR (1UL << 28) /* host bus data error */
137#define PORT_IRQ_IF_ERR (1UL << 27) /* interface fatal error */
138#define PORT_IRQ_IF_NONFATAL (1UL << 26) /* interface non-fatal error */
139#define PORT_IRQ_OVERFLOW (1UL << 24) /* xfer exhausted available S/G */
140#define PORT_IRQ_BAD_PMP (1UL << 23) /* incorrect port multiplier */
141#define PORT_IRQ_PHYRDY (1UL << 22) /* PhyRdy changed */
142#define PORT_IRQ_DEV_ILCK (1UL << 7) /* device interlock */
143#define PORT_IRQ_CONNECT (1UL << 6) /* port connect change status */
144#define PORT_IRQ_SG_DONE (1UL << 5) /* descriptor processed */
145#define PORT_IRQ_UNK_FIS (1UL << 4) /* unknown FIS rx'd */
146#define PORT_IRQ_SDB_FIS (1UL << 3) /* Set Device Bits FIS rx'd */
147#define PORT_IRQ_DMAS_FIS (1UL << 2) /* DMA Setup FIS rx'd */
148#define PORT_IRQ_PIOS_FIS (1UL << 1) /* PIO Setup FIS rx'd */
149#define PORT_IRQ_D2H_REG_FIS (1UL << 0) /* D2H Register FIS rx'd */
150#define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \
151 PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \
152 PORT_IRQ_UNK_FIS | PORT_IRQ_BAD_PMP)
153#define PORT_IRQ_ERROR (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR | \
154 PORT_IRQ_HBUS_DATA_ERR)
155#define DEF_PORT_IRQ (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | \
156 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | \
157 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS)
158
159/* PORT_CMD bits */
160#define PORT_CMD_ASP (1UL << 27) /* Aggressive Slumber/Partial */
161#define PORT_CMD_ALPE (1UL << 26) /* Aggressive Link PM enable */
162#define PORT_CMD_ATAPI (1UL << 24) /* Device is ATAPI */
163#define PORT_CMD_PMP (1UL << 17) /* PMP attached */
164#define PORT_CMD_LIST_ON (1UL << 15) /* cmd list DMA engine running */
165#define PORT_CMD_FIS_ON (1UL << 14) /* FIS DMA engine running */
166#define PORT_CMD_FIS_RX (1UL << 4) /* Enable FIS receive DMA engine */
167#define PORT_CMD_CLO (1UL << 3) /* Command list override */
168#define PORT_CMD_POWER_ON (1UL << 2) /* Power up device */
169#define PORT_CMD_SPIN_UP (1UL << 1) /* Spin up device */
170#define PORT_CMD_START (1UL << 0) /* Enable port DMA engine */
171
172#define PORT_CMD_ICC_MASK (0xfUL << 28) /* i/f ICC state mask */
173#define PORT_CMD_ICC_ACTIVE (0x1UL << 28) /* Put i/f in active state */
174#define PORT_CMD_ICC_PARTIAL (0x2UL << 28) /* Put i/f in partial state */
175#define PORT_CMD_ICC_SLUMBER (0x6UL << 28) /* Put i/f in slumber state */
176
177/* driver status bits */
178#define AHCI_HFLAG_NO_NCQ (1UL << 0) /* no native cmd queuing */
179#define AHCI_HFLAG_IGN_IRQ_IF_ERR (1UL << 1) /* ignore IRQ_IF_ERR */
180#define AHCI_HFLAG_IGN_SERR_INTERNAL (1UL << 2) /* ignore SERR_INTERNAL */
181#define AHCI_HFLAG_32BIT_ONLY (1UL << 3) /* force 32bit */
182#define AHCI_HFLAG_MV_PATA (1UL << 4) /* PATA port */
183#define AHCI_HFLAG_NO_MSI (1UL << 5) /* no PCI MSI */
184#define AHCI_HFLAG_NO_PMP (1UL << 6) /* no PMP */
185#define AHCI_HFLAG_NO_HOTPLUG (1UL << 7) /* ignore PxSERR.DIAG.N */
186#define AHCI_HFLAG_SECT255 (1UL << 8) /* max 255 sectors */
187#define AHCI_HFLAG_YES_NCQ (1UL << 9) /* force NCQ cap on */
188#define AHCI_HFLAG_NO_SUSPEND (1UL << 10) /* don't suspend */
189#define AHCI_HFLAG_SRST_TOUT_IS_OFFLINE (1UL << 11) /* treat SRST timeout as
190 link offline */
191#define AHCI_HFLAG_NO_SNTF (1UL << 12) /* no sntf */
192
193#define ICH_MAP 0x90 /* ICH MAP register */
194
195/* em constants */
196#define EM_MAX_SLOTS 8
197#define EM_MAX_RETRY 5
198
199/* em_ctl bits */
200#define EM_CTL_RST (1UL << 9) /* Reset */
201#define EM_CTL_TM (1UL << 8) /* Transmit Message */
202#define EM_CTL_ALHD (1UL << 26) /* Activity LED */
203
204/* ------------------------ typedefs and structures ------------------------ */
205
206/* Primitive types
207 *
208 * Note: Since OS/2 is essentially an x86 OS and this driver, as well as the
209 * interface it's developed for, is based on x86 design patterns, we're
210 * not even going to start making a difference between little and big
211 * endian architectures. PCI is little endian, AHCI is little endian,
212 * x86 is little endian, and that's it.
213 */
214typedef unsigned char u8;
215typedef unsigned short u16;
216typedef unsigned long u32;
217
218/* AHCI S/G structure */
219typedef struct {
220 u32 addr; /* address of S/G element */
221 u32 addr_hi; /* address of S/G element (upper 32 bits) */
222 u32 reserved;
223 u32 size; /* size of S/G element - 1; the high 10 bits are flags:
224 * 31 : interrupt on completion of this S/G
225 * 30-22 : reserved */
226} AHCI_SG;
227
228/* AHCI command header */
229typedef struct {
230 u32 options; /* command options */
231 u32 status; /* command status */
232 u32 tbl_addr; /* command table address */
233 u32 tbl_addr_high; /* command table address (upper 32 bits) */
234 u32 reserved[4];
235} AHCI_CMD_HDR;
236
237/* AHCI command table */
238typedef struct {
239 u8 cmd_fis[64]; /* ATA command FIS */
240 u8 atapi_cmd[16]; /* ATAPI command */
241 u8 reserved[48];
242 AHCI_SG sg_list[AHCI_MAX_SG]; /* AHCI S/G list */
243} AHCI_CMD_TBL;
244
245/* AHCI port DMA scratch area */
246typedef struct {
247 AHCI_CMD_HDR cmd_hdr[AHCI_MAX_CMDS]; /* command headers */
248 u8 rx_fis[AHCI_RX_FIS_SZ]; /* FIS RX area */
249 AHCI_CMD_TBL cmd_tbl[AHCI_MAX_CMDS]; /* command table */
250} AHCI_PORT_DMA;
251
252/* AHCI port BIOS configuration save area */
253typedef struct {
254 u32 cmd_list; /* cmd list base address */
255 u32 cmd_list_h; /* cmd list base address high */
256 u32 fis_rx; /* FIS receive buffer */
257 u32 fis_rx_h; /* FIS receive bufffer high */
258 u32 irq_mask; /* IRQ mask */
259} AHCI_PORT_CFG;
260
Note: See TracBrowser for help on using the repository browser.