source: trunk/src/os2ahci/ahci.c@ 13

Last change on this file since 13 was 13, checked in by root, 15 years ago

latest NCQ changes from Christian
File size: 50.5 KB
Line 
1/******************************************************************************
2 * ahci.c - ahci hardware access functions
3 *
4 * Copyright (c) 2010 Christian Mueller. Parts copied from/inspired by the
5 * Linux AHCI driver; those parts are (c) Linux AHCI/ATA maintainers
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include "os2ahci.h"
23#include "ata.h"
24#include "atapi.h"
25
26/* -------------------------- macros and constants ------------------------- */
27
28/* produce ata/atapi function pointer with the given func name */
29#define cmd_func(iorb, func) ad_infos[iorb_unit_adapter(iorb)]. \
30 ports[iorb_unit_port(iorb)]. \
31 devs[iorb_unit_device(iorb)].atapi \
32 ? atapi_##func : ata_##func
33
34
35/* ------------------------ typedefs and structures ------------------------ */
36
37/* -------------------------- function prototypes -------------------------- */
38
39static void ahci_setup_device (AD_INFO *ai, int p, int d, u16 *id_buf);
40static void _far timeout_callback (ULONG timer_handle, ULONG p1, ULONG p2);
41
42/* ------------------------ global/static variables ------------------------ */
43
44/* Initial driver status flags indexed by the board_* constants in os2ahci.h
45 *
46 * NOTE: The Linux AHCI driver uses a combination of board-specific quirk
47 * flags and overriding certain libata service functions to handle
48 * adapter flaws. However, there were only three overrides at the time
49 * os2ahci was written, one for hard adapter resets and two for port
50 * resets, and we can easily implement those within the corresponding
51 * reset handlers. If this becomes more complex, this array of flags
52 * should be converted into a structure array which contains function
53 * pointers to all handler functions which may need to be overridden.
54 */
55u16 initial_flags[] = {
56 0, /* board_ahci */
57 AHCI_HFLAG_NO_NCQ | /* board_ahci_vt8251 */
58 AHCI_HFLAG_NO_PMP,
59 AHCI_HFLAG_IGN_IRQ_IF_ERR, /* board_ahci_ign_iferr */
60 AHCI_HFLAG_IGN_SERR_INTERNAL | /* board_ahci_sb600 */
61 AHCI_HFLAG_NO_MSI |
62 AHCI_HFLAG_SECT255 |
63 AHCI_HFLAG_32BIT_ONLY,
64 AHCI_HFLAG_NO_NCQ | /* board_ahci_mv */
65 AHCI_HFLAG_NO_MSI |
66 AHCI_HFLAG_MV_PATA |
67 AHCI_HFLAG_NO_PMP,
68 AHCI_HFLAG_IGN_SERR_INTERNAL, /* board_ahci_sb700 */
69 AHCI_HFLAG_YES_NCQ, /* board_ahci_mcp65 */
70 AHCI_HFLAG_NO_PMP, /* board_ahci_nopmp */
71 AHCI_HFLAG_YES_NCQ, /* board_ahci_yesncq */
72 AHCI_HFLAG_NO_SNTF, /* board_ahci_nosntf */
73};
74
75/* IRQ levels for stub interrupt handlers. OS/2 calls interrupt handlers
76 * without passing the IRQ level, yet it expects the interrupt handler to
77 * know the IRQ level for EOI processing. Thus we need multiple interrupt
78 * handlers, one for each IRQ, and some mapping from the interrupt handler
79 * index to the corresponding IRQ.
80 */
81static u16 irq_map[MAX_AD]; /* IRQ level for each stub IRQ func */
82static int irq_map_cnt; /* number of IRQ stub funcs used */
83
84/* ----------------------------- start of code ----------------------------- */
85
86/******************************************************************************
87 * Interrupt handlers. Those are stubs which call the real interrupt handler
88 * with the IRQ level as parameter. This mapping is required because OS/2
89 * calls interrupt handlers without any parameters, yet expects them to know
90 * which IRQ level to complete when calling DevHelp_EOI().
91 *
92 * This array of functions needs to be extended when increasing MAX_AD.
93 */
94#if MAX_AD > 8
95#error must extend irq_handler_xx and irq_handlers[] when increasing MAX_AD
96#endif
97
98/* Macro to call AHCI interrupt handler and set/clear carry flag accordingly.
99 * We need to set the carry flag if the interrupt was not handled. This is
100 * done by shifting the return value of ahci_intr() to the right, implying
101 * bit 0 will be set when the interrupt was not handled.
102 */
103#define call_ahci_intr(i) return(ahci_intr(irq_map[i]) >> 1)
104
105static USHORT _far irq_handler_00(void) { call_ahci_intr(0); }
106static USHORT _far irq_handler_01(void) { call_ahci_intr(1); }
107static USHORT _far irq_handler_02(void) { call_ahci_intr(2); }
108static USHORT _far irq_handler_03(void) { call_ahci_intr(3); }
109static USHORT _far irq_handler_04(void) { call_ahci_intr(4); }
110static USHORT _far irq_handler_05(void) { call_ahci_intr(5); }
111static USHORT _far irq_handler_06(void) { call_ahci_intr(6); }
112static USHORT _far irq_handler_07(void) { call_ahci_intr(7); }
113
114PFN irq_handlers[] = {
115 (PFN) irq_handler_00, (PFN) irq_handler_01, (PFN) irq_handler_02,
116 (PFN) irq_handler_03, (PFN) irq_handler_04, (PFN) irq_handler_05,
117 (PFN) irq_handler_06, (PFN) irq_handler_07
118};
119
120/******************************************************************************
121 * Save BIOS configuration of AHCI adapter. As a side effect, this also saves
122 * generic configuration information which we may have to restore after an
123 * adapter reset.
124 *
125 * NOTE: This function also saves working copies of the CAP and CAP2 registers
126 * as well as the initial port map in the AD_INFO structure after
127 * removing features which are known to cause trouble on this specific
128 * piece of hardware.
129 */
130int ahci_save_bios_config(AD_INFO *ai)
131{
132 int ports;
133 int i;
134
135 /* save BIOS configuration */
136 for (i = 0; i < HOST_CAP2; i += sizeof(u32)) {
137 ai->bios_config[i / sizeof(u32)] = readl(ai->mmio + i);
138 }
139
140 /* HOST_CAP2 only exists for AHCI V1.2 and later */
141 if (ai->bios_config[HOST_VERSION / sizeof(u32)] >= 0x00010200L) {
142 ai->bios_config[HOST_CAP2 / sizeof(u32)] = readl(ai->mmio + HOST_CAP2);
143 } else {
144 ai->bios_config[HOST_CAP2 / sizeof(u32)] = 0;
145 }
146
147 /* print AHCI register debug information */
148 if (debug) {
149 printf("AHCI global controller registers:\n");
150 for (i = 0; i <= HOST_CAP2 / sizeof(u32); i++) {
151 u32 val = ai->bios_config[i];
152 printf(" %02x: %08lx", i, val);
153
154 if (i == HOST_CAP) {
155 printf(" -");
156 if (val & HOST_CAP_64) printf(" 64bit");
157 if (val & HOST_CAP_NCQ) printf(" ncq");
158 if (val & HOST_CAP_SNTF) printf(" sntf");
159 if (val & HOST_CAP_MPS) printf(" mps");
160 if (val & HOST_CAP_SSS) printf(" sss");
161 if (val & HOST_CAP_ALPM) printf(" alpm");
162 if (val & HOST_CAP_LED) printf(" led");
163 if (val & HOST_CAP_CLO) printf(" clo");
164 if (val & HOST_CAP_ONLY) printf(" ahci_only");
165 if (val & HOST_CAP_PMP) printf(" pmp");
166 if (val & HOST_CAP_FBS) printf(" fbs");
167 if (val & HOST_CAP_PIO_MULTI) printf(" pio_multi");
168 if (val & HOST_CAP_SSC) printf(" ssc");
169 if (val & HOST_CAP_PART) printf(" part");
170 if (val & HOST_CAP_CCC) printf(" ccc");
171 if (val & HOST_CAP_EMS) printf(" ems");
172 if (val & HOST_CAP_SXS) printf(" sxs");
173 printf(" cmd_slots:%d", (u16) ((val >> 8) & 0x1f) + 1);
174 printf(" ports:%d", (u16) (val & 0x1f) + 1);
175
176 } else if (i == HOST_CTL) {
177 printf(" -");
178 if (val & HOST_AHCI_EN) printf(" ahci_enabled");
179 if (val & HOST_IRQ_EN) printf(" irq_enabled");
180 if (val & HOST_RESET) printf(" resetting");
181
182 } else if (i == HOST_CAP2) {
183 printf(" -");
184 if (val & HOST_CAP2_BOH) printf(" boh");
185 if (val & HOST_CAP2_NVMHCI) printf(" nvmhci");
186 if (val & HOST_CAP2_APST) printf(" apst");
187
188 }
189 printf("\n");
190 }
191 }
192
193 /* Save working copies of CAP, CAP2 and port_map and remove broken feature
194 * bits. This is largely copied from the Linux AHCI driver -- the wisdom
195 * around quirks and faulty hardware is hard to come by...
196 */
197 ai->cap = ai->bios_config[HOST_CAP / sizeof(u32)];
198 ai->cap2 = ai->bios_config[HOST_CAP2 / sizeof(u32)];
199 ai->port_map = ai->bios_config[HOST_PORTS_IMPL / sizeof(u32)];
200
201 if (ai->pci->board >= sizeof(initial_flags) / sizeof(*initial_flags)) {
202 dprintf("error: invalid board index in PCI info\n");
203 return(-1);
204 }
205 ai->flags = initial_flags[ai->pci->board];
206
207 if ((ai->cap & HOST_CAP_64) && (ai->flags & AHCI_HFLAG_32BIT_ONLY)) {
208 /* disable 64-bit support for faulty controllers; OS/2 can't do 64 bits at
209 * this point, of course, but who knows where all this will be in a few
210 * years...
211 */
212 ai->cap &= ~HOST_CAP_64;
213 }
214
215 if ((ai->cap & HOST_CAP_NCQ) && (ai->flags & AHCI_HFLAG_NO_NCQ)) {
216 dprintf("controller can't do NCQ, turning off CAP_NCQ\n");
217 ai->cap &= ~HOST_CAP_NCQ;
218 }
219
220 if (!(ai->cap & HOST_CAP_NCQ) && (ai->flags & AHCI_HFLAG_YES_NCQ)) {
221 dprintf("controller can do NCQ, turning on CAP_NCQ\n");
222 ai->cap |= HOST_CAP_NCQ;
223 }
224
225 if ((ai->cap & HOST_CAP_PMP) && (ai->flags & AHCI_HFLAG_NO_PMP)) {
226 dprintf("controller can't do PMP, turning off CAP_PMP\n");
227 ai->cap |= HOST_CAP_PMP;
228 }
229
230 if ((ai->cap & HOST_CAP_SNTF) && (ai->flags & AHCI_HFLAG_NO_SNTF)) {
231 dprintf("controller can't do SNTF, turning off CAP_SNTF\n");
232 ai->cap &= ~HOST_CAP_SNTF;
233 }
234
235 if (ai->pci->vendor == PCI_VENDOR_ID_JMICRON &&
236 ai->pci->device == 0x2361 && ai->port_map != 1) {
237 dprintf("JMB361 has only one port, port_map 0x%x -> 0x%x\n", ai->port_map, 1);
238 ai->port_map = 1;
239 }
240
241 /* Correlate port map to number of ports reported in HOST_CAP
242 *
243 * NOTE: Port map and number of ports handling differs a bit from the
244 * Linux AHCI driver because we're storing both in AI_INFO. As in the
245 * Linux driver, the port map is the main driver for port scanning but
246 * we're also saving a maximum port number in AI_INFO to reduce the
247 * number of IORB queues to look at in trigger_engine(). This is done
248 * in ahci_scan_ports().
249 */
250 ports = (ai->cap & 0x1f) + 1;
251 for (i = 0; i < AHCI_MAX_PORTS; i++) {
252 if (ai->port_map & (1UL << i)) {
253 ports--;
254 }
255 }
256 if (ports < 0) {
257 /* more ports in port_map than in HOST_CAP & 0x1f */
258 ports = (ai->cap & 0x1f) + 1;
259 dprintf("implemented port map (0x%lx) contains more "
260 "ports than nr_ports (%d), using nr_ports\n",
261 ai->port_map, ports);
262 ai->port_map = (1UL << ports) - 1UL;
263 }
264
265 /* set maximum command slot number */
266 ai->cmd_max = (u16) ((ai->cap >> 8) & 0x1f);
267
268 return(0);
269}
270
271/******************************************************************************
272 * Restore BIOS configuration of AHCI adapter. This is needed after scanning
273 * for devices because we still need the BIOS until the initial boot sequence
274 * has completed.
275 */
276int ahci_restore_bios_config(AD_INFO *ai)
277{
278 ddprintf("restoring AHCI BIOS configuration\n");
279
280 /* restore saved BIOS configuration */
281 writel(ai->mmio + HOST_CTL, ai->bios_config[HOST_CTL / sizeof(u32)]);
282 writel(ai->mmio + HOST_CCC, ai->bios_config[HOST_CCC / sizeof(u32)]);
283 writel(ai->mmio + HOST_CCC_PORTS, ai->bios_config[HOST_CCC_PORTS / sizeof(u32)]);
284 writel(ai->mmio + HOST_EM_CTL, ai->bios_config[HOST_EM_CTL / sizeof(u32)]);
285
286 /* flush PCI MMIO delayed write buffers */
287 readl(ai->mmio + HOST_EM_CTL);
288
289 return(0);
290}
291
292/******************************************************************************
293 * Restore initial configuration (e.g. after an adapter reset). This relies
294 * on information saved by 'ahci_save_bios_config()'.
295 */
296int ahci_restore_initial_config(AD_INFO *ai)
297{
298 ddprintf("restoring initial configuration\n");
299
300 /* restore saved BIOS configuration */
301 writel(ai->mmio + HOST_CTL, ai->bios_config[HOST_CTL / sizeof(u32)]);
302 writel(ai->mmio + HOST_CCC, ai->bios_config[HOST_CCC / sizeof(u32)]);
303 writel(ai->mmio + HOST_CCC_PORTS, ai->bios_config[HOST_CCC_PORTS / sizeof(u32)]);
304 writel(ai->mmio + HOST_EM_CTL, ai->bios_config[HOST_EM_CTL / sizeof(u32)]);
305
306 /* flush PCI MMIO delayed write buffers */
307 readl(ai->mmio + HOST_EM_CTL);
308
309 /* (re-)enable AHCI mode */
310 ahci_enable_ahci(ai);
311
312 return(0);
313}
314
315/******************************************************************************
316 * Save port configuration. This is primarily used to save the BIOS port
317 * configuration (command list and FIS buffers and the IRQ mask).
318 *
319 * The port configuration returned by this function is dynamically allocated
320 * and automatically freed when calling ahci_restore_port_config().
321 */
322AHCI_PORT_CFG *ahci_save_port_config(AD_INFO *ai, int p)
323{
324 AHCI_PORT_CFG *pc;
325 u8 _far *port_mmio = port_base(ai, p);
326
327 if ((pc = malloc(sizeof(*pc))) == NULL) {
328 return(NULL);
329 }
330
331 pc->cmd_list = readl(port_mmio + PORT_LST_ADDR);
332 pc->cmd_list_h = readl(port_mmio + PORT_LST_ADDR_HI);
333 pc->fis_rx = readl(port_mmio + PORT_FIS_ADDR);
334 pc->fis_rx_h = readl(port_mmio + PORT_FIS_ADDR_HI);
335 pc->irq_mask = readl(port_mmio + PORT_IRQ_MASK);
336
337 return(pc);
338}
339
340/******************************************************************************
341 * Restore port configuration. This is primarily used to restore the BIOS port
342 * configuration (command list and FIS buffers and the IRQ mask).
343 *
344 * The port configuration automatically freed.
345 */
346void ahci_restore_port_config(AD_INFO *ai, int p, AHCI_PORT_CFG *pc)
347{
348 u8 _far *port_mmio = port_base(ai, p);
349
350 writel(port_mmio + PORT_LST_ADDR, pc->cmd_list);
351 writel(port_mmio + PORT_LST_ADDR_HI, pc->cmd_list_h);
352 writel(port_mmio + PORT_FIS_ADDR, pc->fis_rx);
353 writel(port_mmio + PORT_FIS_ADDR_HI, pc->fis_rx_h);
354 writel(port_mmio + PORT_IRQ_MASK, pc->irq_mask);
355
356 readl(port_base(ai, p) + PORT_IRQ_MASK); /* flush */
357
358 free(pc);
359}
360
361/******************************************************************************
362 * Enable AHCI mode on this controller.
363 */
364int ahci_enable_ahci(AD_INFO *ai)
365{
366 u32 ctl = readl(ai->mmio + HOST_CTL);
367 int i;
368
369 if (ctl & HOST_AHCI_EN) {
370 /* AHCI mode already enbled */
371 return(0);
372 }
373
374 /* some controllers need AHCI_EN to be written multiple times */
375 for (i = 0; i < 5; i++) {
376 ctl |= HOST_AHCI_EN;
377 writel(ai->mmio + HOST_CTL, ctl);
378 ctl = readl(ai->mmio + HOST_CTL); /* flush && sanity check */
379 if (ctl & HOST_AHCI_EN) {
380 return(0);
381 }
382 mdelay(10);
383 }
384
385 /* couldn't enable AHCI mode */
386 dprintf("failed to enable AHCI mode on adapter #%d\n", ad_no(ai));
387 return(1);
388}
389
390/******************************************************************************
391 * Scan all ports for connected devices and fill in the corresponding device
392 * information.
393 *
394 * NOTES:
395 *
396 * - The adapter is temporarily configured for os2ahci but the original BIOS
397 * configuration will be restored when done. This happens only until we
398 * have received the IOCC_COMPLETE_INIT command.
399 *
400 * - Subsequent calls are currently not planned but may be required for
401 * suspend/resume handling, hot swap functionality, etc.
402 *
403 * - This function is expected to be called with the spinlock released but
404 * the corresponding adapter's busy flag set. It will aquire the spinlock
405 * temporarily to allocate/free memory for the ATA identify buffer.
406 */
407int ahci_scan_ports(AD_INFO *ai)
408{
409 AHCI_PORT_CFG *pc = NULL;
410 u16 *id_buf;
411 int rc;
412 int p;
413
414 spin_lock(drv_lock);
415 id_buf = malloc(ATA_ID_WORDS * sizeof(u16));
416 spin_unlock(drv_lock);
417 if (id_buf == NULL) {
418 return(-1);
419 }
420
421 if (ai->bios_config[0] == 0) {
422 /* first call */
423 ahci_save_bios_config(ai);
424 }
425
426 if (ahci_enable_ahci(ai)) {
427 goto exit_port_scan;
428 }
429
430 /* perform port scan */
431 dprintf("scanning ports on adapter #%d\n", ad_no(ai));
432 for (p = 0; p < AHCI_MAX_PORTS; p++) {
433 if (ai->port_map & (1UL << p)) {
434
435 if (!init_complete) {
436 if ((pc = ahci_save_port_config(ai, p)) == NULL) {
437 goto exit_port_scan;
438 }
439 }
440
441 /* start/reset port; if no device is attached, this is expected to fail */
442 if (init_reset) {
443 ddprintf("resetting port #%d\n", p);
444 rc = ahci_reset_port(ai, p, 0);
445 } else {
446 ddprintf("(re)starting port #%d\n", p);
447 ahci_stop_port(ai, p);
448 rc = ahci_start_port(ai, p, 0);
449 }
450 if (rc) {
451 /* no device attached to this port */
452 ai->port_map &= ~(1UL << p);
453 goto restore_port_config;
454 }
455
456 /* this port has a device attached and is ready to accept commands */
457 ddprintf("port #%d seems to be attached to a device; probing...\n", p);
458 rc = ahci_exec_polled_cmd(ai, p, 0, 500, ATA_CMD_ID_ATA,
459 AP_VADDR, (void _far *) id_buf, 512,
460 AP_END);
461
462 if (rc != 0 || id_buf[ATA_ID_CONFIG] & (1U << 15)) {
463 /* this might be an ATAPI device; run IDENTIFY_PACKET_DEVICE */
464 rc = ahci_exec_polled_cmd(ai, p, 0, 500, ATA_CMD_ID_ATAPI,
465 AP_VADDR, (void _far *) id_buf, 512,
466 AP_END);
467 }
468
469 if (rc == 0) {
470 /* we have a valid IDENTIFY or IDENTIFY_PACKET response */
471 ddphex(id_buf, 512, "ATA_IDENTIFY(_PACKET) results:\n");
472 ahci_setup_device(ai, p, 0, id_buf);
473 } else {
474 /* no device attached to this port */
475 ai->port_map &= ~(1UL << p);
476 }
477
478 restore_port_config:
479 if (pc != NULL) {
480 ahci_restore_port_config(ai, p, pc);
481 }
482 }
483 }
484
485exit_port_scan:
486 if (!init_complete) {
487 ahci_restore_bios_config(ai);
488 }
489 spin_lock(drv_lock);
490 free(id_buf);
491 spin_unlock(drv_lock);
492 return(0);
493}
494
495/******************************************************************************
496 * Complete initialization of adapter. This includes restarting all active
497 * ports and initializing interrupt processing. This is called when receiving
498 * the IOCM_COMPLETE_INIT request.
499 */
500int ahci_complete_init(AD_INFO *ai)
501{
502 int rc;
503 int p;
504 int i;
505
506 dprintf("completing initialization of adapter #%d\n", ad_no(ai));
507
508 /* register IRQ handlers; each IRQ level is registered only once */
509 for (i = 0; i < irq_map_cnt; i++) {
510 if (irq_map[i] == ai->irq) {
511 /* we already have this IRQ registered */
512 break;
513 }
514 }
515
516 if (i >= irq_map_cnt) {
517 dprintf("registering interrupt #%d\n", ai->irq);
518
519 if (DevHelp_SetIRQ(mk_NPFN(irq_handlers[irq_map_cnt]), ai->irq, 1) != 0) {
520 dprintf("failed to register shared interrupt\n");
521
522 if (DevHelp_SetIRQ(mk_NPFN(irq_handlers[irq_map_cnt]), ai->irq, 0) != 0) {
523 dprintf("failed to register exclusive interrupt\n");
524 return(-1);
525 }
526 }
527 irq_map[irq_map_cnt++] = ai->irq;
528 }
529
530 /* enable AHCI mode */
531 if ((rc = ahci_enable_ahci(ai)) != 0) {
532 return(rc);
533 }
534
535 /* Start all ports. The main purpose is to set the command list and FIS
536 * receive area addresses properly and to enable port-level interrupts; we
537 * don't really care about the return status because we'll find out soon
538 * enough if a previously detected device has problems.
539 */
540 for (p = 0; p < AHCI_MAX_PORTS; p++) {
541 if (ai->port_map & (1UL << p)) {
542 dprintf("restarting port #%d\n", p);
543 ahci_stop_port(ai, p);
544 ahci_start_port(ai, p, 1);
545 }
546 }
547
548 /* enable adapter-level interrupts */
549 writel(ai->mmio + HOST_CTL, HOST_IRQ_EN);
550 readl(ai->mmio + HOST_CTL); /* flush */
551
552 /* enable interrupts on PCI-level (PCI 2.3 added a feature to disable ints) */
553 pci_enable_int(ai->bus, ai->dev_func);
554
555 return(0);
556}
557
558/******************************************************************************
559 * Reset specified port. This function is typically called during adapter
560 * initialization and first gets the port into a defined status, then resets
561 * the port by sending a COMRESET signal.
562 *
563 * This function is also the location of the link speed initialization (link
564 * needs to be restablished after changing link speed, anyway).
565 *
566 * NOTE: This function uses a busy loop to wait for DMA engines to stop and
567 * the COMRESET to complete. It should only be called at task time
568 * during initialization or in a context hook.
569 */
570int ahci_reset_port(AD_INFO *ai, int p, int ei)
571{
572 u8 _far *port_mmio = port_base(ai, p);
573 u32 tmp;
574 int timeout = 500;
575
576 dprintf("resetting port %d.%d\n", ad_no(ai), p);
577
578 /* stop port engines (we don't care whether there is an error doing so) */
579 ahci_stop_port(ai, p);
580
581 /* clear SError */
582 tmp = readl(port_mmio + PORT_SCR_ERR);
583 ddprintf(" PORT_SCR_ERR = 0x%lx\n", tmp);
584 writel(port_mmio + PORT_SCR_ERR, tmp);
585
586 /* clear pending port IRQs */
587 tmp = readl(port_mmio + PORT_IRQ_STAT);
588 if (tmp) {
589 writel(port_mmio + PORT_IRQ_STAT, tmp);
590 }
591 ddprintf(" PORT_IRQ_STAT = 0x%lx\n", tmp);
592 ddprintf(" PORT_IRQ_MASK = 0x%lx\n", readl(port_mmio + PORT_IRQ_MASK));
593 ddprintf(" HOST_IRQ_STAT = 0x%lx\n", readl(ai->mmio + HOST_IRQ_STAT));
594 writel(ai->mmio + HOST_IRQ_STAT, 1UL << p);
595
596 /* set link speed */
597 tmp = readl(port_mmio + PORT_SCR_CTL) & ~0x000000f0UL;
598 writel(port_mmio + PORT_SCR_CTL, tmp | (link_speed[ad_no(ai)][p] << 4));
599
600 /* issue COMRESET on the port */
601 tmp = readl(port_mmio + PORT_SCR_CTL) & ~0x0000000fUL;
602 writel(port_mmio + PORT_SCR_CTL, tmp | 1);
603 readl(port_mmio + PORT_SCR_CTL); /* flush */
604
605 /* spec says "leave reset bit on for at least 1ms"; make it 2ms */
606 mdelay(2);
607
608 writel(port_mmio + PORT_SCR_CTL, tmp);
609 readl(port_mmio + PORT_SCR_CTL); /* flush */
610
611 /* wait for communication to be re-established after port reset */
612 while (((tmp = readl(port_mmio + PORT_SCR_STAT) & 3)) != 3) {
613 mdelay(10);
614 timeout -= 10;
615 if (timeout <= 0) {
616 dprintf("no device present after resetting port #%d "
617 "(PORT_SCR_STAT = 0x%lx)\n", p, tmp);
618 return(-1);
619 }
620 }
621
622 /* clear SError again (recommended by AHCI spec) */
623 tmp = readl(port_mmio + PORT_SCR_ERR);
624 writel(port_mmio + PORT_SCR_ERR, tmp);
625
626 /* start port so we can receive the COMRESET FIS */
627 ahci_start_port(ai, p, ei);
628
629 /* wait for device to be ready ((PxTFD & (BSY | DRQ | ERR)) == 0) */
630 while (((tmp = readl(port_mmio + PORT_TFDATA)) & 0x89) != 0) {
631 mdelay(10);
632 timeout -= 10;
633 if (timeout <= 0) {
634 dprintf("device not ready on port #%d "
635 "(PORT_TFDATA = 0x%lx)\n", p, tmp);
636 ahci_stop_port(ai, p);
637 return(-1);
638 }
639 }
640 ddprintf(" PORT_TFDATA = 0x%lx\n", readl(port_mmio + PORT_TFDATA));
641
642 return(0);
643}
644
645/******************************************************************************
646 * Start specified port.
647 */
648int ahci_start_port(AD_INFO *ai, int p, int ei)
649{
650 u8 _far *port_mmio = port_base(ai, p);
651 u32 status;
652
653 /* check whether device presence is detected and link established */
654 status = readl(port_mmio + PORT_SCR_STAT);
655 ddprintf(" PORT_SCR_STAT = 0x%lx\n", status);
656 if ((status & 0xf) != 3) {
657 return(-1);
658 }
659
660 /* enable FIS reception */
661 ahci_start_fis_rx(ai, p);
662
663 /* enable DMA */
664 ahci_start_engine(ai, p);
665
666 if (ei) {
667 /* enable port interrupts */
668 writel(port_mmio + PORT_IRQ_MASK, PORT_IRQ_TF_ERR |
669 PORT_IRQ_HBUS_ERR |
670 PORT_IRQ_HBUS_DATA_ERR |
671 PORT_IRQ_IF_ERR |
672 PORT_IRQ_OVERFLOW |
673 PORT_IRQ_BAD_PMP |
674 PORT_IRQ_UNK_FIS |
675 PORT_IRQ_SDB_FIS |
676 PORT_IRQ_D2H_REG_FIS);
677 } else {
678 writel(port_mmio + PORT_IRQ_MASK, 0);
679 }
680 readl(port_mmio + PORT_IRQ_MASK); /* flush */
681
682 return(0);
683}
684
685/******************************************************************************
686 * Start port FIS reception. Copied from Linux AHCI driver and adopted to
687 * OS2AHCI.
688 */
689void ahci_start_fis_rx(AD_INFO *ai, int p)
690{
691 u8 _far *port_mmio = port_base(ai, p);
692 u32 port_dma = port_dma_base_phys(ai, p);
693 u32 tmp;
694
695 /* set comand header and FIS address registers */
696 writel(port_mmio + PORT_LST_ADDR, port_dma + offsetof(AHCI_PORT_DMA, cmd_hdr));
697 writel(port_mmio + PORT_LST_ADDR_HI, 0);
698 writel(port_mmio + PORT_FIS_ADDR, port_dma + offsetof(AHCI_PORT_DMA, rx_fis));
699 writel(port_mmio + PORT_FIS_ADDR_HI, 0);
700
701 /* enable FIS reception */
702 tmp = readl(port_mmio + PORT_CMD);
703 tmp |= PORT_CMD_FIS_RX;
704 writel(port_mmio + PORT_CMD, tmp);
705
706 /* flush */
707 readl(port_mmio + PORT_CMD);
708}
709
710/******************************************************************************
711 * Start port HW engine. Copied from Linux AHCI driver and adopted to OS2AHCI.
712 */
713void ahci_start_engine(AD_INFO *ai, int p)
714{
715 u8 _far *port_mmio = port_base(ai, p);
716 u32 tmp;
717
718 /* start DMA */
719 tmp = readl(port_mmio + PORT_CMD);
720 tmp |= PORT_CMD_START;
721 writel(port_mmio + PORT_CMD, tmp);
722 readl(port_mmio + PORT_CMD); /* flush */
723}
724
725/******************************************************************************
726 * Stop specified port
727 */
728int ahci_stop_port(AD_INFO *ai, int p)
729{
730 u8 _far *port_mmio = port_base(ai, p);
731 int rc;
732
733 /* disable FIS reception */
734 if ((rc = ahci_stop_fis_rx(ai, p)) != 0) {
735 dprintf("error: failed to stop FIS receive (%d)\n", rc);
736 return(rc);
737 }
738
739 /* disable DMA */
740 if ((rc = ahci_stop_engine(ai, p)) != 0) {
741 dprintf("error: failed to stop port HW engine (%d)\n", rc);
742 return(rc);
743 }
744
745 /* reset PxSACT register (tagged command queues, not reset by COMRESET) */
746 writel(port_mmio + PORT_SCR_ACT, 0);
747 readl(port_mmio + PORT_SCR_ACT); /* flush */
748
749 return(0);
750}
751
752/******************************************************************************
753 * Stop port FIS reception. Copied from Linux AHCI driver and adopted to
754 * OS2AHCI.
755 *
756 * NOTE: This function uses a busy loop to wait for the DMA engine to stop. It
757 * should only be called at task time during initialization or in a
758 * context hook (e.g. when resetting a port).
759 */
760int ahci_stop_fis_rx(AD_INFO *ai, int p)
761{
762 u8 _far *port_mmio = port_base(ai, p);
763 int timeout = 1000;
764 u32 tmp;
765
766 /* disable FIS reception */
767 tmp = readl(port_mmio + PORT_CMD);
768 tmp &= ~PORT_CMD_FIS_RX;
769 writel(port_mmio + PORT_CMD, tmp);
770
771 /* wait for completion, spec says 500ms, give it 1000 */
772 while (timeout > 0 && (readl(port_mmio + PORT_CMD) & PORT_CMD_FIS_ON)) {
773 mdelay(10);
774 timeout -= 10;
775 }
776
777 return((timeout <= 0) ? -1 : 0);
778}
779
780/******************************************************************************
781 * Stop port HW engine. Copied from Linux AHCI driver and adopted to OS2AHCI.
782 *
783 * NOTE: This function uses a busy loop to wait for the DMA engine to stop. It
784 * should only be called at task time during initialization or in a
785 * context hook (e.g. when resetting a port).
786 */
787int ahci_stop_engine(AD_INFO *ai, int p)
788{
789 u8 _far *port_mmio = port_base(ai, p);
790 int timeout = 500;
791 u32 tmp;
792
793 tmp = readl(port_mmio + PORT_CMD);
794
795 /* check if the port is already stopped */
796 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) {
797 return 0;
798 }
799
800 /* set port to idle */
801 tmp &= ~PORT_CMD_START;
802 writel(port_mmio + PORT_CMD, tmp);
803
804 /* wait for engine to stop. This could be as long as 500 msec */
805 while (timeout > 0 && (readl(port_mmio + PORT_CMD) & PORT_CMD_LIST_ON)) {
806 mdelay(10);
807 timeout -= 10;
808 }
809
810 return((timeout <= 0) ? -1 : 0);
811}
812
813/******************************************************************************
814 * Execute AHCI command for given IORB. This includes all steps typically
815 * required by any of the ahci_*() IORB processing functions.
816 *
817 * NOTE: In order to prevent race conditions with port restart and reset
818 * handlers, we either need to keep the spinlock during the whole
819 * operation or set the adapter's busy flag. Since the expectation
820 * is that command preparation will be quick (it certainly doesn't
821 * involve delays), we're going with the spinlock for the time being.
822 */
823void ahci_exec_iorb(IORBH _far *iorb, int ncq_capable,
824 int (*func)(IORBH _far *, int))
825{
826 volatile u32 *cmds;
827 ADD_WORKSPACE _far *aws = add_workspace(iorb);
828 AD_INFO *ai = ad_infos + iorb_unit_adapter(iorb);
829 P_INFO *port = ai->ports + iorb_unit_port(iorb);
830 ULONG timeout = (iorb->Timeout > 0) ? iorb->Timeout : DEFAULT_TIMEOUT;
831 u8 _far *port_mmio = port_base(ai, iorb_unit_port(iorb));
832 u16 cmd_max = ai->cmd_max;
833 int i;
834
835 /* determine whether this will be an NCQ request */
836 aws->is_ncq = 0;
837 if (ncq_capable && port->devs[iorb_unit_device(iorb)].ncq_max > 1 &&
838 (ai->cap & HOST_CAP_NCQ) && !aws->no_ncq && init_complete) {
839
840 /* We can make this an NCQ request; limit command slots to the maximum
841 * NCQ tag number reported by the device - 1. Why "minus one"? I seem to
842 * recall an issue related to using all 32 tag numbers but can't quite
843 * pinpoint it right now. One less won't make much of a difference...
844 */
845 aws->is_ncq = 1;
846 if ((cmd_max = port->devs[iorb_unit_device(iorb)].ncq_max - 1) > ai->cmd_max) {
847 cmd_max = ai->cmd_max;
848 }
849 ddprintf("NCQ command; cmd_max = %d->%d\n", (u16) ai->cmd_max, cmd_max);
850 }
851
852 /* make sure adapter is available */
853 spin_lock(drv_lock);
854 if (!ai->busy) {
855
856 if (!init_complete) {
857 ai->busy = 1;
858 spin_unlock(drv_lock);
859 ahci_exec_polled_iorb(iorb, func, timeout);
860 ai->busy = 0;
861 return;
862 }
863
864 /* make sure we don't mix NCQ and regular commands */
865 if (aws->is_ncq && port->reg_cmds == 0 || !aws->is_ncq && port->ncq_cmds == 0) {
866
867 /* Find next available command slot. We use a simple round-robin
868 * algorithm for this to prevent commands with higher slot indexes
869 * from stalling when new commands are coming in frequently.
870 */
871 cmds = (aws->is_ncq) ? &port->ncq_cmds : &port->reg_cmds;
872 for (i = 0; i <= cmd_max; i++) {
873 if (++(port->cmd_slot) > cmd_max) {
874 port->cmd_slot = 0;
875 }
876 if ((*cmds & (1UL << port->cmd_slot)) == 0) {
877 break;
878 }
879 }
880
881 if ((*cmds & (1UL << port->cmd_slot)) == 0) {
882 /* prepare command */
883 if (func(iorb, port->cmd_slot)) {
884 /* Command preparation failed, or no HW command required; IORB
885 * will already have the error code if there was an error.
886 */
887 spin_unlock(drv_lock);
888 iorb_done(iorb);
889 return;
890 }
891
892 /* start timer for this IORB */
893 ADD_StartTimerMS(&aws->timer, timeout, (PFN) timeout_callback, iorb, 0);
894
895 /* update IORB */
896 aws->queued_hw = 1;
897 aws->cmd_slot = port->cmd_slot;
898
899 /* issue command to hardware */
900 ddprintf("issuing command on slot %d\n", port->cmd_slot);
901 *cmds |= (1UL << port->cmd_slot);
902 if (aws->is_ncq) {
903 writel(port_mmio + PORT_SCR_ACT, (1UL << port->cmd_slot));
904 readl(port_mmio + PORT_SCR_ACT); /* flush */
905 }
906 writel(port_mmio + PORT_CMD_ISSUE, (1UL << port->cmd_slot));
907 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
908
909 spin_unlock(drv_lock);
910 return;
911 }
912 }
913 }
914
915 /* requeue this IORB; it will be picked up again in trigger_engine() */
916 aws->processing = 0;
917 spin_unlock(drv_lock);
918}
919
920/******************************************************************************
921 * Execute polled IORB command. This function is called by ahci_exec_iorb()
922 * when the initialization has not yet completed. The reasons for polling until
923 * initialization has completed are:
924 *
925 * - We need to restore the BIOS configuration after we're done with this
926 * command because someone might still call int 13h routines; sending
927 * asynchronous commands and waiting for interrupts to indicate completion
928 * won't work in such a scenario.
929 * - Our context hooks won't work while the device managers are initializing
930 * (they can't yield at init time).
931 * - The device managers typically poll for command completion during
932 * initialization so it won't make much of a difference, anyway.
933 *
934 * NOTE: This function must be called with the adapter-level busy flag set but
935 * without the driver-level spinlock held.
936 */
937void ahci_exec_polled_iorb(IORBH _far *iorb, int (*func)(IORBH _far *, int),
938 ULONG timeout)
939{
940 AHCI_PORT_CFG *pc = NULL;
941 AD_INFO *ai = ad_infos + iorb_unit_adapter(iorb);
942 int p = iorb_unit_port(iorb);
943 u8 _far *port_mmio = port_base(ai, p);
944
945 /* enable AHCI mode */
946 if (ahci_enable_ahci(ai) != 0) {
947 iorb_seterr(iorb, IOERR_ADAPTER_NONSPECIFIC);
948 goto restore_bios_config;
949 }
950
951 /* check whether command slot 0 is available */
952 if ((readl(port_mmio + PORT_CMD_ISSUE) & 1) != 0) {
953 iorb_seterr(iorb, IOERR_DEVICE_BUSY);
954 goto restore_bios_config;
955 }
956
957 /* save port configuration */
958 if ((pc = ahci_save_port_config(ai, p)) == NULL) {
959 iorb_seterr(iorb, IOERR_CMD_SW_RESOURCE);
960 goto restore_bios_config;
961 }
962
963 /* restart port (includes the necessary port configuration) */
964 if (ahci_stop_port(ai, p) || ahci_start_port(ai, p, 0)) {
965 iorb_seterr(iorb, IOERR_ADAPTER_NONSPECIFIC);
966 goto restore_bios_config;
967 }
968
969 /* prepare command */
970 if (func(iorb, 0) == 0) {
971 /* successfully prepared cmd; issue cmd and wait for completion */
972 ddprintf("executing polled cmd...");
973 writel(port_mmio + PORT_CMD_ISSUE, 1);
974 timeout /= 10;
975 while (timeout > 0 && (readl(port_mmio + PORT_CMD_ISSUE) & 1)) {
976 mdelay(10);
977 timeout--;
978 }
979 ddprintf(" done (time left = %ld)\n", timeout * 10);
980
981 if (timeout == 0) {
982 dprintf("timeout for IORB %Fp\n", iorb);
983 iorb_seterr(iorb, IOERR_ADAPTER_TIMEOUT);
984
985 } else if (readl(port_mmio + PORT_SCR_ERR) != 0 ||
986 readl(port_mmio + PORT_TFDATA) & 0x89) {
987 dprintf("polled cmd error for IORB %Fp\n", iorb);
988 iorb_seterr(iorb, IOERR_DEVICE_NONSPECIFIC);
989 ahci_reset_port(ai, iorb_unit_port(iorb), 0);
990
991 } else {
992 /* successfully executed command */
993 if (add_workspace(iorb)->ppfunc != NULL) {
994 add_workspace(iorb)->ppfunc(iorb);
995 } else {
996 add_workspace(iorb)->complete = 1;
997 }
998 }
999 }
1000
1001restore_bios_config:
1002 /* restore BIOS configuration */
1003 if (pc != NULL) {
1004 ahci_restore_port_config(ai, p, pc);
1005 }
1006 ahci_restore_bios_config(ai);
1007
1008 if (add_workspace(iorb)->complete | (iorb->Status | IORB_ERROR)) {
1009 aws_free(add_workspace(iorb));
1010 iorb_done(iorb);
1011 }
1012 return;
1013}
1014
1015/******************************************************************************
1016 * Execute polled ATA/ATAPI command. This function will block until the command
1017 * has completed or the timeout has expired, thus it should only be used during
1018 * initialization. Furthermore, it will always use command slot zero.
1019 *
1020 * The difference to ahci_exec_polled_iorb() is that this function executes
1021 * arbitrary ATA/ATAPI commands outside the context of an IORB. It's typically
1022 * used when scanning for devices during initialization.
1023 */
1024int ahci_exec_polled_cmd(AD_INFO *ai, int p, int d, int timeout, int cmd, ...)
1025{
1026 va_list va;
1027 u8 _far *port_mmio = port_base(ai, p);
1028 u32 tmp;
1029 int rc;
1030
1031 /* verify that command slot 0 is idle */
1032 if (readl(port_mmio + PORT_CMD_ISSUE) & 1) {
1033 ddprintf("port %d slot 0 is not idle; not executing polled cmd\n", p);
1034 return(-1);
1035 }
1036
1037 /* fill in command slot 0 */
1038 va_start(va, cmd);
1039 if ((rc = v_ata_cmd(ai, p, d, 0, cmd, va)) != 0) {
1040 return(rc);
1041 }
1042
1043 /* start command execution for slot 0 */
1044 ddprintf("executing polled cmd...");
1045 writel(port_mmio + PORT_CMD_ISSUE, 1);
1046
1047 /* wait until command has completed */
1048 while (timeout > 0 && (readl(port_mmio + PORT_CMD_ISSUE) & 1)) {
1049 mdelay(10);
1050 timeout -= 10;
1051 }
1052 ddprintf(" done (time left = %d)\n", timeout);
1053
1054 /* check error condition */
1055 if ((tmp = readl(port_mmio + PORT_SCR_ERR)) != 0) {
1056 dprintf("SERR = 0x%08lx\n", tmp);
1057 return(-1);
1058 }
1059 if (((tmp = readl(port_mmio + PORT_TFDATA)) & 0x89) != 0) {
1060 dprintf("TFDATA = 0x%08lx\n", tmp);
1061 return(-1);
1062 }
1063
1064 return((timeout <= 0) ? -1 : 0);
1065}
1066
1067/******************************************************************************
1068 * AHCI top-level hardware interrupt handler. This handler finds the adapters
1069 * and ports which have issued the interrupt and calls the corresponding
1070 * port interrupt handler.
1071 *
1072 * On entry, OS/2 will have processor interrupts enabled because we're using
1073 * shared IRQs but we won't be preempted by another interrupt on the same IRQ
1074 * IRQ level until we indicated EOI. We'll keep it this way, only requesting
1075 * the driver-level spinlock when actually changing the driver state (IORB
1076 * queues, ...)
1077 */
1078int ahci_intr(u16 irq)
1079{
1080 u32 irq_stat;
1081 int handled = 0;
1082 int a;
1083 int p;
1084
1085 /* find adapter(s) with pending interrupts */
1086 for (a = 0; a < ad_info_cnt; a++) {
1087 AD_INFO *ai = ad_infos + a;
1088
1089 if (ai->irq == irq && (irq_stat = readl(ai->mmio + HOST_IRQ_STAT)) != 0) {
1090 /* this adapter has interrupts pending */
1091 u32 irq_masked = irq_stat & ai->port_map;
1092
1093 for (p = 0; p <= ai->port_max; p++) {
1094 if (irq_masked & (1UL << p)) {
1095 ahci_port_intr(ai, p);
1096 }
1097 }
1098
1099 /* clear interrupt condition on the adapter */
1100 writel(ai->mmio + HOST_IRQ_STAT, irq_stat);
1101 readl(ai->mmio + HOST_IRQ_STAT); /* flush */
1102 handled = 1;
1103 }
1104 }
1105
1106 if (handled) {
1107 /* trigger state machine to process next IORBs, if any */
1108 spin_lock(drv_lock);
1109 trigger_engine();
1110 spin_unlock(drv_lock);
1111
1112 /* complete the interrupt */
1113 DevHelp_EOI(irq);
1114 return(0);
1115 } else {
1116 return(1);
1117 }
1118}
1119
1120/******************************************************************************
1121 * AHCI port-level interrupt handler. As described above, processor interrupts
1122 * are enabled on entry thus we have to protect shared resources with a
1123 * spinlock.
1124 */
1125void ahci_port_intr(AD_INFO *ai, int p)
1126{
1127 IORB_QUEUE done_queue;
1128 IORBH _far *iorb;
1129 IORBH _far *next = NULL;
1130 u8 _far *port_mmio = port_base(ai, p);
1131 u32 irq_stat;
1132 u32 active_cmds;
1133 u32 done_mask;
1134
1135 ddprintf("port interrupt for adapter #%d, port #%d\n", ad_no(ai), p);
1136 memset(&done_queue, 0x00, sizeof(done_queue));
1137
1138 /* get interrupt status and clear it right away */
1139 irq_stat = readl(port_mmio + PORT_IRQ_STAT);
1140 writel(port_mmio + PORT_IRQ_STAT, irq_stat);
1141 readl(port_mmio + PORT_IRQ_STAT); /* flush */
1142
1143 if (irq_stat & PORT_IRQ_ERROR) {
1144 /* this is an error interrupt */
1145 ahci_error_intr(ai, p, irq_stat);
1146 return;
1147 }
1148
1149 spin_lock(drv_lock);
1150
1151 /* Find out which command slots have completed. Since error recovery for
1152 * NCQ commands interfers with non-NCQ commands, the upper layers will
1153 * make sure there's never a mixture of NCQ and non-NCQ commands active
1154 * on any port at any given time. This makes it easier to find out which
1155 * commands have completed, too.
1156 */
1157 if (ai->ports[p].ncq_cmds != 0) {
1158 active_cmds = readl(port_mmio + PORT_SCR_ACT);
1159 done_mask = ai->ports[p].ncq_cmds ^ active_cmds;
1160 ddprintf("[ncq_cmds]: active_cmds = 0x%08lx, done_mask = 0x%08lx\n",
1161 active_cmds, done_mask);
1162 } else {
1163 active_cmds = readl(port_mmio + PORT_CMD_ISSUE);
1164 done_mask = ai->ports[p].reg_cmds ^ active_cmds;
1165 ddprintf("[reg_cmds]: active_cmds = 0x%08lx, done_mask = 0x%08lx\n",
1166 active_cmds, done_mask);
1167 }
1168
1169 /* Find the IORBs related to the completed commands and complete them.
1170 *
1171 * NOTES: The spinlock must not be released while in this loop to prevent
1172 * race conditions with timeout handlers or other threads in SMP
1173 * systems.
1174 *
1175 * Since we hold the spinlock when IORBs complete, we can't call the
1176 * IORB notification routine right away because this routine might
1177 * schedule another IORB which could cause a deadlock. Thus, we'll
1178 * add all IORBs to be completed to a temporary queue which will be
1179 * processed after releasing the spinlock.
1180 */
1181 for (iorb = ai->ports[p].iorb_queue.root; iorb != NULL; iorb = next) {
1182 ADD_WORKSPACE _far *aws = (ADD_WORKSPACE _far *) &iorb->ADDWorkSpace;
1183 next = iorb->pNxtIORB;
1184 if (aws->queued_hw && (done_mask & (1UL << aws->cmd_slot))) {
1185 /* this command has completed */
1186 if (aws->ppfunc != NULL) {
1187 aws->ppfunc(iorb);
1188 } else {
1189 aws->complete = 1;
1190 }
1191
1192 if (aws->complete) {
1193 /* this IORB is complete */
1194 aws_free(aws);
1195
1196 /* move IORB to our temporary done queue */
1197 iorb_queue_del(&ai->ports[p].iorb_queue, iorb);
1198 iorb_queue_add(&done_queue, iorb);
1199 }
1200
1201 /* clear corresponding bit in issued command bitmaps */
1202 ai->ports[p].ncq_cmds &= ~(1UL << aws->cmd_slot);
1203 ai->ports[p].reg_cmds &= ~(1UL << aws->cmd_slot);
1204 }
1205 }
1206
1207 spin_unlock(drv_lock);
1208
1209 /* call notification routines for all IORBs in the done queue */
1210 for (iorb = done_queue.root; iorb != NULL; iorb = next) {
1211 next = iorb->pNxtIORB;
1212 iorb->Status = IORB_DONE;
1213 if (iorb->RequestControl & IORB_ASYNC_POST) {
1214 iorb->NotifyAddress(iorb);
1215 }
1216 }
1217}
1218
1219/******************************************************************************
1220 * AHCI error interrupt handler. Errors include interface errors and device
1221 * errors (usually triggered by the error bit in the AHCI task file register).
1222 *
1223 * Since this involves long-running operations such as restarting or even
1224 * resetting a port, this function is invoked at task time via a context
1225 * hook.
1226 *
1227 * NOTE: AHCI controllers stop all processing when encountering an error
1228 * condition in order to give the driver time to find out what exactly
1229 * went wrong. This means no new commands will be processed until we
1230 * clear the error register and restore the "commands issued" register.
1231 */
1232void ahci_error_intr(AD_INFO *ai, int p, u32 irq_stat)
1233{
1234 u8 _far *port_mmio = port_base(ai, p);
1235 int reset_port = 0;
1236 u32 tmp;
1237
1238 /* Handle adapter and interface errors. Those typically require a port
1239 * reset, or worse.
1240 */
1241 if (irq_stat & PORT_IRQ_UNK_FIS) {
1242 u32 _far *unk = (u32 _far *) (port_dma_base(ai, p)->rx_fis + RX_FIS_UNK);
1243 dprintf("warning: unknown FIS %08lx %08lx %08lx %08lx\n",
1244 unk[0], unk[1], unk[2], unk[3]);
1245 reset_port = 1;
1246 }
1247 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1248 dprintf("warning: host bus [data] error for port #%d\n", p);
1249 reset_port = 1;
1250 }
1251 if (irq_stat & PORT_IRQ_IF_ERR && !(ai->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)) {
1252 dprintf("warning: interface fatal error for port #%d\n", p);
1253 reset_port = 1;
1254 }
1255 if (reset_port) {
1256 /* need to reset the port; leave this to the reset context hook */
1257 ports_to_reset[ad_no(ai)] |= 1UL << p;
1258 DevHelp_ArmCtxHook(0, reset_ctxhook_h);
1259
1260 /* no point analyzing device errors after a reset... */
1261 return;
1262 }
1263
1264 /* Handle device-specific errors. Those errors typically involve restarting
1265 * the corresponding port to resume operations which can take some time,
1266 * thus we need to offload this functionality to the restart context hook.
1267 */
1268 if (irq_stat & PORT_IRQ_TF_ERR) {
1269 ports_to_restart[ad_no(ai)] |= 1UL << p;
1270 DevHelp_ArmCtxHook(0, restart_ctxhook_h);
1271 }
1272}
1273
1274/******************************************************************************
1275 * Get device or media geometry. Device and media geometry are expected to be
1276 * the same for non-removable devices.
1277 */
1278void ahci_get_geometry(IORBH _far *iorb)
1279{
1280 dprintf("ahci_get_geometry(%d.%d.%d)\n", (int) iorb_unit_adapter(iorb),
1281 (int) iorb_unit_port(iorb), (int) iorb_unit_device(iorb));
1282
1283 ahci_exec_iorb(iorb, 0, cmd_func(iorb, get_geometry));
1284}
1285
1286/******************************************************************************
1287 * Test whether unit is ready.
1288 */
1289void ahci_unit_ready(IORBH _far *iorb)
1290{
1291 dprintf("ahci_unit_ready(%d.%d.%d)\n", (int) iorb_unit_adapter(iorb),
1292 (int) iorb_unit_port(iorb), (int) iorb_unit_device(iorb));
1293
1294 ahci_exec_iorb(iorb, 0, cmd_func(iorb, unit_ready));
1295}
1296
1297/******************************************************************************
1298 * Read sectors from AHCI device.
1299 */
1300void ahci_read(IORBH _far *iorb)
1301{
1302 dprintf("ahci_read(%d.%d.%d, %ld, %ld)\n", (int) iorb_unit_adapter(iorb),
1303 (int) iorb_unit_port(iorb), (int) iorb_unit_device(iorb),
1304 (long) ((IORB_EXECUTEIO _far *) iorb)->RBA,
1305 (long) ((IORB_EXECUTEIO _far *) iorb)->BlockCount);
1306
1307 ahci_exec_iorb(iorb, 1, cmd_func(iorb, read));
1308}
1309
1310/******************************************************************************
1311 * Verify readability of sectors on AHCI device.
1312 */
1313void ahci_verify(IORBH _far *iorb)
1314{
1315 dprintf("ahci_verify(%d.%d.%d, %ld, %ld)\n", (int) iorb_unit_adapter(iorb),
1316 (int) iorb_unit_port(iorb), (int) iorb_unit_device(iorb),
1317 (long) ((IORB_EXECUTEIO _far *) iorb)->RBA,
1318 (long) ((IORB_EXECUTEIO _far *) iorb)->BlockCount);
1319
1320 ahci_exec_iorb(iorb, 0, cmd_func(iorb, verify));
1321}
1322
1323/******************************************************************************
1324 * Write sectors to AHCI device.
1325 */
1326void ahci_write(IORBH _far *iorb)
1327{
1328 dprintf("ahci_write(%d.%d.%d, %ld, %ld)\n", (int) iorb_unit_adapter(iorb),
1329 (int) iorb_unit_port(iorb), (int) iorb_unit_device(iorb),
1330 (long) ((IORB_EXECUTEIO _far *) iorb)->RBA,
1331 (long) ((IORB_EXECUTEIO _far *) iorb)->BlockCount);
1332
1333 ahci_exec_iorb(iorb, 1, cmd_func(iorb, write));
1334}
1335
1336/******************************************************************************
1337 * Execute SCSI (ATAPI) command.
1338 */
1339void ahci_execute_cdb(IORBH _far *iorb)
1340{
1341 int a = iorb_unit_adapter(iorb);
1342 int p = iorb_unit_port(iorb);
1343 int d = iorb_unit_device(iorb);
1344
1345 dphex(((IORB_ADAPTER_PASSTHRU _far *) iorb)->pControllerCmd,
1346 ((IORB_ADAPTER_PASSTHRU _far *) iorb)->ControllerCmdLen,
1347 "ahci_execute_cdb(%d.%d.%d)", a, p, d);
1348
1349 if (ad_infos[a].ports[p].devs[d].atapi) {
1350 ahci_exec_iorb(iorb, 0, atapi_execute_cdb);
1351 } else {
1352 iorb_seterr(iorb, IOERR_CMD_NOT_SUPPORTED);
1353 iorb_done(iorb);
1354 }
1355}
1356
1357/******************************************************************************
1358 * Execute ATA command.
1359 */
1360void ahci_execute_ata(IORBH _far *iorb)
1361{
1362 int a = iorb_unit_adapter(iorb);
1363 int p = iorb_unit_port(iorb);
1364 int d = iorb_unit_device(iorb);
1365
1366 dphex(((IORB_ADAPTER_PASSTHRU _far *) iorb)->pControllerCmd,
1367 ((IORB_ADAPTER_PASSTHRU _far *) iorb)->ControllerCmdLen,
1368 "ahci_execute_cdb(%d.%d.%d)", a, p, d);
1369
1370 if (ad_infos[a].ports[p].devs[d].atapi) {
1371 iorb_seterr(iorb, IOERR_CMD_NOT_SUPPORTED);
1372 iorb_done(iorb);
1373 } else {
1374 ahci_exec_iorb(iorb, 0, ata_execute_ata);
1375 }
1376}
1377
1378/******************************************************************************
1379 * Set up device attached to the specified port based on ATA_IDENTFY_DEVICE or
1380 * ATA_IDENTFY_PACKET_DEVICE data.
1381 *
1382 * NOTE: Port multipliers are not supported, yet, thus the device number is
1383 * expected to be 0 for the time being.
1384 */
1385static void ahci_setup_device(AD_INFO *ai, int p, int d, u16 *id_buf)
1386{
1387 DEVICESTRUCT ds;
1388 ADJUNCT adj;
1389 HDEVICE dh;
1390
1391 if (ai->port_max < p) {
1392 ai->port_max = p;
1393 }
1394 if (ai->ports[p].dev_max < d) {
1395 ai->ports[p].dev_max = d;
1396 }
1397 memset(ai->ports[p].devs + d, 0x00, sizeof(*ai->ports[p].devs));
1398
1399 /* set generic device information (assuming an ATA disk device for now) */
1400 ai->ports[p].devs[d].present = 1;
1401 ai->ports[p].devs[d].removable = (id_buf[ATA_ID_CONFIG] & 0x0080U) != 0;
1402 ai->ports[p].devs[d].dev_type = UIB_TYPE_DISK;
1403
1404 if (id_buf[ATA_ID_CONFIG] & 0x8000U) {
1405 /* this is an ATAPI device; augment device information */
1406 ai->ports[p].devs[d].atapi = 1;
1407 ai->ports[p].devs[d].atapi_16 = (id_buf[ATA_ID_CONFIG] & 0x0001U) != 0;
1408 ai->ports[p].devs[d].dev_type = (id_buf[ATA_ID_CONFIG] & 0x1f00U) >> 8;
1409
1410 } else {
1411 /* complete ATA-specific device information */
1412 if (!disable_ncq[ad_no(ai)][p]) {
1413 ai->ports[p].devs[d].ncq_max = id_buf[ATA_ID_QUEUE_DEPTH] & 0x001fU;
1414 }
1415 if (id_buf[ATA_ID_CFS_ENABLE_2] & 0x0400U) {
1416 ai->ports[p].devs[d].lba48 = 1;
1417 }
1418 }
1419
1420 dprintf("found device %d.%d.%d: removable = %d, dev_type = %d, atapi = %d\n",
1421 ad_no(ai), p, d,
1422 ai->ports[p].devs[d].removable,
1423 ai->ports[p].devs[d].dev_type,
1424 ai->ports[p].devs[d].atapi);
1425
1426 /* add device to resource manager; we don't really care about errors here */
1427 memset(&ds, 0x00, sizeof(ds));
1428 memset(&adj, 0x00, sizeof(adj));
1429
1430 adj.pNextAdj = NULL;
1431 adj.AdjLength = sizeof(adj);
1432 adj.AdjType = ADJ_ADD_UNIT;
1433 adj.Add_Unit.ADDHandle = rm_drvh;
1434
1435 ds.DevDescriptName = ata_dev_name(id_buf);
1436 ds.DevFlags = (ai->ports[p].devs[d].removable) ? DS_REMOVEABLE_MEDIA
1437 : DS_FIXED_LOGICALNAME;
1438 ds.DevType = ai->ports[p].devs[d].dev_type;
1439
1440 RMCreateDevice(rm_drvh, &dh, &ds, ai->rm_adh, NULL);
1441
1442 /* try to detect virtualbox environment to enable a hack for IRQ routing */
1443 if (ai == ad_infos && p == 7 &&
1444 ai->pci->vendor == 0x8086 && ai->pci->device == 0x2829 &&
1445 !memcmp(ds.DevDescriptName, "VBOX HARDDISK", 13)) {
1446 /* running inside virtualbox */
1447 pci_hack_virtualbox();
1448 }
1449}
1450
1451/******************************************************************************
1452 * Timeout handler for I/O commands. Since timeout handling can involve
1453 * lengthy operations like port resets, the main code is located in a
1454 * separate function which is invoked via a context hook.
1455 */
1456static void _far timeout_callback(ULONG timer_handle, ULONG p1, ULONG p2)
1457{
1458 IORBH _far *iorb = (IORBH _far *) p1;
1459 int a = iorb_unit_adapter(iorb);
1460 int p = iorb_unit_port(iorb);
1461
1462 ADD_CancelTimer(timer_handle);
1463 dprintf("timeout for IORB %Fp\n", iorb);
1464
1465 /* Move the timed-out IORB to the abort queue. Since it's possible that the
1466 * IORB has completed after the timeout has expired but before we got to
1467 * this line of code, we'll check the return code of iorb_queue_del(): If it
1468 * returns an error, the IORB must have completed a few microseconds ago and
1469 * there is no timeout.
1470 */
1471 spin_lock(drv_lock);
1472 if (iorb_queue_del(&ad_infos[a].ports[p].iorb_queue, iorb) == 0) {
1473 iorb_queue_add(&abort_queue, iorb);
1474 iorb->ErrorCode = IOERR_ADAPTER_TIMEOUT;
1475 }
1476 spin_unlock(drv_lock);
1477
1478 /* Trigger abort processing function. We don't really care whether this
1479 * succeeds because the only reason why it would fail should be multiple
1480 * calls to DevHelp_ArmCtxHook() before the context hook had a chance to
1481 * start executing, which leaves two scenarios:
1482 *
1483 * - We succeded in arming the context hook. Fine.
1484 *
1485 * - We armed the context hook a second time before it had a chance to
1486 * start executing. In this case, the already scheduled context hook
1487 * will process our IORB as well.
1488 */
1489 DevHelp_ArmCtxHook(0, reset_ctxhook_h);
1490}
1491
Note: See TracBrowser for help on using the repository browser.