source: trunk/src/os2ahci.h@ 9

Last change on this file since 9 was 8, checked in by markus, 15 years ago

latest changes by Christian
File size: 21.3 KB
RevLine 
[4]1/******************************************************************************
2 * os2ahci.h - main header file for os2ahci driver
3 *
4 * Copyright (c) 2010 Christian Mueller. Parts copied from/inspired by the
5 * Linux AHCI driver; those parts are (c) Linux AHCI/ATA maintainers
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/* ----------------------------- include files ----------------------------- */
23
24/* IMPORTANT NOTE: The DDK headers require tight structure packing and this
25 * is controlled via compiler parameters. Thus, all stuctures in os2ahci.sys
26 * are expected to be byte-aligned without the need of explicit pragma pack()
27 * directives. Where possible, the structures are layed out such that words
28 * and dwords are aligned at least on 2-byte boundaries.
29 */
30
31#define INCL_NOPMAPI
32#define INCL_DOSINFOSEG
33#define INCL_NO_SCB
34#define INCL_DOSERRORS
35#include <os2.h>
36#include <dos.h>
37#include <bseerr.h>
38#include <dskinit.h>
39#include <scb.h>
40
41#include <devhdr.h>
42#include <iorb.h>
43#include <strat2.h>
44#include <reqpkt.h>
45#include <dhcalls.h>
46#include <addcalls.h>
47#include <rmcalls.h>
48#include <devclass.h>
49#include <devcmd.h>
50#include <rmbase.h>
51
52#include "ahci.h"
53
54/* -------------------------- macros and constants ------------------------- */
55
56#define VERSION 100 /* driver version (2 implied decimals) */
57#define MAX_AD 8 /* maximum number of adapters */
58
59/* Timer pool size. In theory, we need one timer per outstanding command plus
60 * a few miscellaneous timers but it's unlikely we'll ever have outstanding
61 * commands on all devices on all ports on all apapters -- this would be
62 * 8 * 32 * 32 = 8192 outstanding commands on a maximum of 8 * 32 * 15 = 3840
63 * devices and that's a bit of an exaggeration. It should be more than enough
64 * to have 128 timers.
65 */
66#define TIMER_COUNT 128
67#define TIMER_POOL_SIZE (sizeof(ADD_TIMER_POOL) + \
68 TIMER_COUNT * sizeof(ADD_TIMER_DATA))
69
70/* default command timeout (can be overwritten in the IORB) */
71#define DEFAULT_TIMEOUT 30000
72
73/* debug output macros */
74#define dprintf if (debug > 0) printf
75#define dphex if (debug > 0) phex
76#define ddprintf if (debug > 1) printf
77#define ddphex if (debug > 1) phex
78#define dddprintf if (debug > 2) printf
79#define dddphex if (debug > 2) phex
80
81/* adapter number from AD_INFO pointer; mainly for dprintf() purposes */
82#define ad_no(ai) (((u16) ai - (u16) ad_infos) / sizeof(*ai))
83
84/* Convert far function address into NPFN (the DDK needs this all over the
85 * place and just casting to NPFN will produce a "segment lost in conversion"
86 * warning. Since casting to a u32 is a bit nasty for function pointers and
87 * might have to be revised for different compilers, we'll use a central
88 * macro for this crap.
89 */
90#define mk_NPFN(func) (NPFN) (u32) (func)
91
92/* stdarg.h macros with explicit far pointers
93 *
94 * NOTE: The compiler pushes fixed arguments with 16 bits minimum, thus
95 * the last fixed argument (i.e. the one passed to va_start) must
96 * have at least 16 bits. Otherwise, the address calculation in
97 * va_start() will fail.
98 */
99typedef char _far *va_list;
100#define va_start(va, last) va = (va_list) (&last + 1)
101#define va_arg(va, type) ((type _far *) (va += sizeof(type)))[-1]
102#define va_end(va) va = 0
103
104/* ctype macros */
105#define isupper(ch) ((ch) >= 'A' && (ch) <= 'Z')
106#define tolower(ch) (isupper(ch) ? (ch) - ('a' - 'A') : (ch))
107
108/* stddef macros */
109#define offsetof(s, e) ((u16) &((s *) 0)->e)
110
111/* SMP spinlock compatibility macros for older DDKs using CLI/STI */
112#ifndef OS2AHCI_SMP
113#define DevHelp_CreateSpinLock(sph) *(sph) = 0
114#define DevHelp_FreeSpinLock(sph) 0
115
116#define DevHelp_AquireSpinLock(sph) if ((sph) != 0) \
117 panic("recursive spinlock"); \
118 (sph) = disable()
119
120#define DevHelp_ReleaseSpinLock(sph) if (sph) { \
121 (sph) = 0; \
122 enable(); \
123 }
124#endif
125
126/* shortcut macros */
127#define spin_lock(sl) DevHelp_AquireSpinLock(sl)
128#define spin_unlock(sl) DevHelp_ReleaseSpinLock(sl)
129
130/* Get AHCI port MMIO base from AD_INFO and port number. For the time being,
131 * MMIO addresses are assumed to be valid 16:16 pointers which implies
132 * that one GDT selector is allocated per adapter.
133 */
134#define port_base(ai, p) ((u8 _far *) (ai)->mmio + 0x100 + (p) * 0x80)
135
136/* Get address of port-specific DMA scratch buffer. The total size of all DMA
137 * buffers required for 32 ports exceeds 65536 bytes, thus we need multiple
138 * GDT selectors to access all port DMA scratch buffers and some logic to map
139 * a port number to the corresponding DMA scratch buffer address.
140 */
141#define PORT_DMA_BUFS_PER_SEG ((size_t) (65536UL / AHCI_PORT_PRIV_DMA_SZ))
142#define PORT_DMA_BUF_SEGS ((AHCI_MAX_PORTS + PORT_DMA_BUFS_PER_SEG - 1) \
143 / PORT_DMA_BUFS_PER_SEG)
144#define PORT_DMA_SEG_SIZE ((u32) PORT_DMA_BUFS_PER_SEG * \
145 (u32) AHCI_PORT_PRIV_DMA_SZ)
146
147#define port_dma_base(ai, p) \
148 ((AHCI_PORT_DMA _far *) ((ai)->dma_buf[(p) / PORT_DMA_BUFS_PER_SEG] + \
149 ((p) % PORT_DMA_BUFS_PER_SEG) * AHCI_PORT_PRIV_DMA_SZ))
150
151#define port_dma_base_phys(ai, p) \
152 ((ai)->dma_buf_phys + (u32) (p) * AHCI_PORT_PRIV_DMA_SZ)
153
154/* Convert an SATA adapter/port/device address into a 16-bit IORB unit handle
155 * (and the other way round). The mapping looks like this:
156 *
157 * mapping comment
158 * -----------------------------------------------------------------------
159 * 4 bits for the adapter current max is 8 adapters
160 * 4 bits for the port AHCI spec defines up to 32 ports
161 * 4 bits for the device SATA spec defines up to 15 devices behind PMP
162 */
163#define iorb_unit(a, p, d) ((((u16) (a) & 0x0fU) << 8) | \
164 (((u16) (p) & 0x0fU) << 4) | \
165 (((u16) (d) & 0x0fU)))
166#define iorb_unit_adapter(iorb) (((u16) (iorb)->UnitHandle >> 8) & 0x07U)
167#define iorb_unit_port(iorb) (((u16) (iorb)->UnitHandle >> 4) & 0x0fU)
168#define iorb_unit_device(iorb) ((u16) (iorb)->UnitHandle & 0x0fU)
169
170/*******************************************************************************
171 * Convenience macros for IORB processing functions
172 */
173/* is this IORB on driver or port level? */
174#define iorb_driver_level(iorb) ((iorb)->CommandCode == IOCC_CONFIGURATION)
175
176/* is this IORB to be inserted at the beginnig of the IORB queue? */
177#define iorb_priority(iorb) ((iorb)->CommandCode == IOCC_DEVICE_CONTROL && \
178 (iorb)->CommandModifier == IOCM_ABORT))
179
180/* access IORB ADD workspace */
181#define add_workspace(iorb) ((ADD_WORKSPACE _far *) &(iorb)->ADDWorkSpace)
182
183/* free resources in ADD workspace (timer, buffer, ...) */
184#define aws_free(aws) if ((aws)->timer != 0) { \
185 ADD_CancelTimer((aws)->timer); \
186 (aws)->timer = 0; \
187 } \
188 if ((aws)->buf != NULL) { \
189 free((aws)->buf); \
190 (aws)->buf = NULL; \
191 }
192
193/******************************************************************************
194 * PCI generic IDs and macros
195 */
196#define PCI_ANY_ID 0xffffU
197#define PCI_VDEVICE(vendor, device) PCI_VENDOR_ID_##vendor, (device), \
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0
199
200/******************************************************************************
201 * PCI vendor IDs for AHCI adapters known to this driver (copied from Linux
202 * pci_ids.h)
203 */
204#define PCI_VENDOR_ID_AL 0x10b9
205#define PCI_VENDOR_ID_AMD 0x1022
206#define PCI_VENDOR_ID_AT 0x1259
207#define PCI_VENDOR_ID_ATI 0x1002
208#define PCI_VENDOR_ID_ATT 0x11c1
209#define PCI_VENDOR_ID_CMD 0x1095
210#define PCI_VENDOR_ID_CT 0x102c
211#define PCI_VENDOR_ID_INTEL 0x8086
212#define PCI_VENDOR_ID_JMICRON 0x197B
213#define PCI_VENDOR_ID_MARVELL 0x11ab
214#define PCI_VENDOR_ID_NVIDIA 0x10de
215#define PCI_VENDOR_ID_PROMISE 0x105a
216#define PCI_VENDOR_ID_SI 0x1039
217#define PCI_VENDOR_ID_VIA 0x1106
218
219/******************************************************************************
220 * PCI class IDs we're interested in (copied from Linux pci_ids.h)
221 */
222#define PCI_BASE_CLASS_STORAGE 0x01
223#define PCI_CLASS_STORAGE_SCSI 0x0100
224#define PCI_CLASS_STORAGE_IDE 0x0101
225#define PCI_CLASS_STORAGE_FLOPPY 0x0102
226#define PCI_CLASS_STORAGE_IPI 0x0103
227#define PCI_CLASS_STORAGE_RAID 0x0104
228#define PCI_CLASS_STORAGE_SATA 0x0106
229#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
230#define PCI_CLASS_STORAGE_SAS 0x0107
231#define PCI_CLASS_STORAGE_OTHER 0x0180
232
233/* ------------------------ typedefs and structures ------------------------ */
234
235typedef unsigned int size_t;
236
237/* PCI device information structure; this is used both for scanning and for
238 * identification purposes in 'AD_INFO'; based on the Linux pci_device_id
239 * structure but hard-wired to use board_* constants for 'driver_data'
240 */
241typedef struct {
242 u16 vendor; /* PCI device vendor/manufacturer */
243 u16 device; /* PCI device ID inside vendor scope */
244 u16 subvendor; /* subsystem vendor (unused so far) */
245 u16 subdevice; /* subsystem device (unused so far) */
246 u32 class; /* PCI device class */
247 u32 class_mask; /* bits to match when scanning for 'class' */
248 u32 board; /* AHCI controller board type (board_* constants) */
249} PCI_ID;
250
251/* IORB queue; since IORB queues are updated at interrupt time, the
252 * corresponding pointers (not the data they point to) need to be volatile.
253 */
254typedef struct {
255 IORBH _far *volatile root; /* root of request list */
256 IORBH _far *volatile tail; /* tail of request list */
257} IORB_QUEUE;
258
259/* port information structure */
260typedef struct {
261 IORB_QUEUE iorb_queue; /* IORB queue for this port */
262 unsigned dev_max : 4; /* maximum device number on this port (0-15) */
263 unsigned cmd_slot : 4; /* current command slot index (using round-
264 * robin indexes to prevent starvation) */
265
266 volatile u32 ncq_cmds; /* bitmap for NCQ commands issued */
267 volatile u32 reg_cmds; /* bitmap for regular commands issued */
268
269 struct {
270 unsigned allocated : 1; /* if != 0, device is allocated */
271 unsigned present : 1; /* if != 0, device is present */
272 unsigned lba48 : 1; /* if != 0, device supports 48-bit LBA */
273 unsigned atapi : 1; /* if != 0, this is an ATAPI device */
274 unsigned atapi_16 : 1; /* if != 0, device suports 16-byte cmds */
275 unsigned removable : 1; /* if != 0, device has removable media */
276 unsigned dev_type : 5; /* device type (UIB_TYPE_* in iorb.h) */
277 unsigned ncq_max : 5; /* maximum tag number for queued commands */
278 UNITINFO _far *unit_info; /* pointer to modified unit info */
279 } devs[15];
280} P_INFO;
281
282/* adapter information structure */
283typedef struct {
284 PCI_ID *pci; /* pointer to corresponding PCI ID */
285
286 unsigned port_max : 4; /* maximum port number (0-31) */
287 unsigned cmd_max : 4; /* maximum cmd slot number (0-31) */
288 unsigned port_scan_done : 1; /* if != 0, port scan already done */
289 unsigned busy : 1; /* if != 0, adapter is busy */
290
291 u32 port_map; /* bitmap of active ports */
292
293 /* initial adapter configuration from BIOS */
294 u32 bios_config[HOST_CAP2 / sizeof(u32) + 1];
295
296 u32 cap; /* working copy of CAP register */
297 u32 cap2; /* working copy of CAP2 register */
298 u32 flags; /* adapter flags */
299
300 HRESOURCE rm_adh; /* resource handle for adapter */
301 HRESOURCE rm_mmio; /* resource handle for MMIO */
302 HRESOURCE rm_irq; /* resource handle for IRQ */
303
304 u8 bus; /* PCI bus number */
305 u8 dev_func; /* PCI device and function number */
306 u16 irq; /* interrupt number */
307
308 u32 mmio_phys; /* physical address of MMIO region */
309 u8 _far *mmio; /* pointer to this adapter's MMIO region */
310
311 u32 dma_buf_phys; /* physical address of DMA scratch buffer */
312 u8 _far *dma_buf[PORT_DMA_BUF_SEGS]; /* DMA scatch buffer */
313
314 P_INFO ports[AHCI_MAX_PORTS]; /* SATA ports on this adapter */
315} AD_INFO;
316
317/* ADD workspace in IORB (must not exceed 16 bytes) */
318typedef struct {
319 void (*ppfunc)(IORBH _far *iorb); /* post-processing function */
320 void *buf; /* response buffer (e.g. for identify cmds) */
321 ULONG timer; /* timer for timeout procesing */
[8]322 USHORT blocks; /* number of blocks to be transferred */
[4]323 unsigned processing : 1; /* IORB is being processd */
324 unsigned idempotent : 1; /* IORB is idempotent (can be retried) */
325 unsigned queued_hw : 1; /* IORB has been queued to hardware */
[8]326 unsigned no_ncq : 1; /* must not use native command queuing */
327 unsigned is_ncq : 1; /* should use native command queueing */
328 unsigned complete : 1; /* IORB has completed processing */
[4]329 unsigned cmd_slot : 4; /* AHCI command slot for this IORB */
330} ADD_WORKSPACE;
331
332/* -------------------------- function prototypes -------------------------- */
333
334/* init.asm */
335extern u32 readl (void _far *addr);
336extern u32 writel (void _far *addr, u32 val);
337extern void _far *memcpy (void _far *v_dst, void _far *v_src, int len);
338extern void _far *memset (void _far *p, int ch, size_t len);
339extern void _far restart_hook (void);
340extern void _far reset_hook (void);
341extern void _far engine_hook (void);
342
343/* os2ahci.c */
344extern USHORT init_drv (RPINITIN _far *req);
345extern void _far _loadds add_entry (IORBH _far *iorb);
346extern void trigger_engine (void);
347extern int trigger_engine_1 (void);
348extern void send_iorb (IORBH _far *iorb);
349extern void iocc_configuration (IORBH _far *iorb);
350extern void iocc_device_control (IORBH _far *iorb);
351extern void iocc_unit_control (IORBH _far *iorb);
352extern void iocm_device_table (IORBH _far *iorb);
353extern void iocc_geometry (IORBH _far *iorb);
354extern void iocc_execute_io (IORBH _far *iorb);
355extern void iocc_unit_status (IORBH _far *iorb);
356extern void iocc_adapter_passthru (IORBH _far *iorb);
357extern void iorb_queue_add (IORB_QUEUE _far *queue, IORBH _far *iorb);
358extern int iorb_queue_del (IORB_QUEUE _far *queue, IORBH _far *iorb);
359extern void iorb_seterr (IORBH _far *iorb, USHORT error_code);
360extern void iorb_done (IORBH _far *iorb);
[8]361extern void iorb_requeue (IORBH _far *iorb);
[4]362
363/* ahci.c */
364extern int ahci_save_bios_config (AD_INFO *ai);
365extern int ahci_restore_bios_config (AD_INFO *ai);
366extern int ahci_restore_initial_config (AD_INFO *ai);
367extern AHCI_PORT_CFG *ahci_save_port_config (AD_INFO *ai, int p);
368extern void ahci_restore_port_config (AD_INFO *ai, int p,
369 AHCI_PORT_CFG *pc);
370extern int ahci_enable_ahci (AD_INFO *ai);
371extern int ahci_scan_ports (AD_INFO *ai);
372extern int ahci_complete_init (AD_INFO *ai);
373extern int ahci_reset_port (AD_INFO *ai, int p, int ei);
374extern int ahci_start_port (AD_INFO *ai, int p, int ei);
375extern void ahci_start_fis_rx (AD_INFO *ai, int p);
376extern void ahci_start_engine (AD_INFO *ai, int p);
377extern int ahci_stop_port (AD_INFO *ai, int p);
378extern int ahci_stop_fis_rx (AD_INFO *ai, int p);
379extern int ahci_stop_engine (AD_INFO *ai, int p);
380extern void ahci_exec_iorb (IORBH _far *iorb, int ncq_capable,
381 int (*func)(IORBH _far *, int));
382extern void ahci_exec_polled_iorb (IORBH _far *iorb,
383 int (*func)(IORBH _far *, int),
384 ULONG timeout);
[8]385extern int ahci_exec_polled_cmd (AD_INFO *ai, int p, int d,
386 int timeout, int cmd, ...);
[4]387
388extern int ahci_intr (u16 irq);
389extern void ahci_port_intr (AD_INFO *ai, int p);
390extern void ahci_error_intr (AD_INFO *ai, int p, u32 irq_stat);
391
392extern void ahci_get_geometry (IORBH _far *iorb);
393extern void ahci_unit_ready (IORBH _far *iorb);
394extern void ahci_read (IORBH _far *iorb);
395extern void ahci_verify (IORBH _far *iorb);
396extern void ahci_write (IORBH _far *iorb);
397extern void ahci_execute_cdb (IORBH _far *iorb);
398extern void ahci_execute_ata (IORBH _far *iorb);
399
400/* libc.c */
401extern void init_com1 (void);
402extern int vsprintf (char _far *buf, const char *fmt, va_list va);
403extern int sprintf (char _far *buf, const char *fmt, ...);
404extern void vfprintf (const char *fmt, va_list va);
405extern void printf (const char *fmt, ...);
406extern void cprintf (const char *fmt, ...);
407extern void phex (const void _far *p, int len,
408 const char *fmt, ...);
409extern size_t strlen (const char _far *s);
410extern char _far *strcpy (char _far *dst, const char _far *src);
411extern int memcmp (void _far *p1, void _far *p2, size_t len);
412extern long strtol (const char _far *buf,
413 const char _far * _far *ep, int base);
414extern void *malloc (size_t len);
415extern void free (void *ptr);
416extern void mdelay_cal (void);
417extern void mdelay (u32 millies);
418extern void msleep (u32 millies);
419extern void panic (char *msg);
420extern int disable (void);
421extern void enable (void);
422
423/* pci.c */
424extern int add_pci_id (u16 vendor, u16 device);
425extern void scan_pci_bus (void);
426extern int pci_enable_int (UCHAR bus, UCHAR dev_func);
427extern void pci_hack_virtualbox(void);
428
429/* ctxhook.c */
430extern void restart_ctxhook (ULONG parm);
431extern void reset_ctxhook (ULONG parm);
432extern void engine_ctxhook (ULONG parm);
433
434/* ---------------------------- global variables --------------------------- */
435
436extern char end_of_data; /* label at the end of all data segments */
437extern void _near end_of_code(); /* label at the end of all code segments */
438
439extern int debug; /* if != 0, print debug messages to COM1 */
440extern int thorough_scan; /* if != 0, perform thorough PCI scan */
441extern int init_reset; /* if != 0, reset ports during init */
442
443extern HDRIVER rm_drvh; /* resource manager driver handle */
444extern USHORT add_handle; /* adapter device driver handle */
445extern UCHAR timer_pool[]; /* timer pool */
446
447extern PCI_ID pci_ids[]; /* SATA adapter PCI IDs */
448extern ULONG drv_lock; /* driver-level spinlock */
449extern IORB_QUEUE driver_queue; /* driver-level IORB queue */
450extern AD_INFO ad_infos[]; /* adapter information list */
451extern int ad_info_cnt; /* number of entries in ad_infos[] */
452extern int init_complete; /* if != 0, initialization has completed */
453
454/* port restart context hook and input data */
455extern ULONG restart_ctxhook_h;
456extern volatile u32 ports_to_restart[MAX_AD];
457
458/* port reset context hook and input data */
459extern ULONG reset_ctxhook_h;
460extern volatile u32 ports_to_reset[MAX_AD];
461extern IORB_QUEUE abort_queue;
462
463/* trigger engine context hook and input data */
464extern ULONG engine_ctxhook_h;
465
466/* apapter/port-specific options saved when parsing the command line */
467extern int link_speed[MAX_AD][AHCI_MAX_PORTS];
468
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