source: trunk/src/ata.h@ 9

Last change on this file since 9 was 8, checked in by markus, 15 years ago

latest changes by Christian
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[4]1/******************************************************************************
2 * ata.h - ATA structures and macros for os2ahci driver
3 *
4 * Copyright (c) 2010 Christian Mueller. Parts copied from/inspired by the
5 * Linux AHCI driver; those parts are (c) Linux AHCI/ATA maintainers
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/* -------------------------- macros and constants ------------------------- */
23
24/******************************************************************************
25 * ATA IDENTIFY offsets and constants. The ATA IDENTIFY response is a bit of a
26 * mess and after struggling to put this into some structure, I discovered the
27 * Linux folks simply defined offsets and constants to those fields which are
28 * actually needed. Thus, I copied the relevant bits from ata.h, replacing
29 * the enum with precompiler definitions because our enums are signed 16 bits.
30 *
31 * Please note that strings such as the product name are stored using byte-
32 * swapped 16-bit words.
33 */
34#define ATA_ID_WORDS 256
35#define ATA_ID_CONFIG 0
36#define ATA_ID_CYLS 1
37#define ATA_ID_HEADS 3
38#define ATA_ID_SECTORS 6
39#define ATA_ID_SERNO 10
40#define ATA_ID_BUF_SIZE 21
41#define ATA_ID_FW_REV 23
42#define ATA_ID_PROD 27
43#define ATA_ID_MAX_MULTSECT 47
44#define ATA_ID_DWORD_IO 48
45#define ATA_ID_CAPABILITY 49
46#define ATA_ID_OLD_PIO_MODES 51
47#define ATA_ID_OLD_DMA_MODES 52
48#define ATA_ID_FIELD_VALID 53
49#define ATA_ID_CUR_CYLS 54
50#define ATA_ID_CUR_HEADS 55
51#define ATA_ID_CUR_SECTORS 56
52#define ATA_ID_MULTSECT 59
53#define ATA_ID_LBA_CAPACITY 60
54#define ATA_ID_SWDMA_MODES 62
55#define ATA_ID_MWDMA_MODES 63
56#define ATA_ID_PIO_MODES 64
57#define ATA_ID_EIDE_DMA_MIN 65
58#define ATA_ID_EIDE_DMA_TIME 66
59#define ATA_ID_EIDE_PIO 67
60#define ATA_ID_EIDE_PIO_IORDY 68
61#define ATA_ID_ADDITIONAL_SUPP 69
62#define ATA_ID_QUEUE_DEPTH 75
63#define ATA_ID_MAJOR_VER 80
64#define ATA_ID_COMMAND_SET_1 82
65#define ATA_ID_COMMAND_SET_2 83
66#define ATA_ID_CFSSE 84
67#define ATA_ID_CFSSE 84
68#define ATA_ID_CFS_ENABLE_1 85
69#define ATA_ID_CFS_ENABLE_2 86
70#define ATA_ID_CSF_DEFAULT 87
71#define ATA_ID_UDMA_MODES 88
72#define ATA_ID_HW_CONFIG 93
73#define ATA_ID_SPG 98
74#define ATA_ID_LBA_CAPACITY_2 100
75#define ATA_ID_SECTOR_SIZE 106
76#define ATA_ID_LAST_LUN 126
77#define ATA_ID_DLF 128
78#define ATA_ID_CSFO 129
79#define ATA_ID_CFA_POWER 160
80#define ATA_ID_CFA_KEY_MGMT 162
81#define ATA_ID_CFA_MODES 163
82#define ATA_ID_DATA_SET_MGMT 169
83#define ATA_ID_ROT_SPEED 217
84#define ATA_ID_PIO4 (1U << 1)
85
86#define ATA_ID_SERNO_LEN 20
87#define ATA_ID_FW_REV_LEN 8
88#define ATA_ID_PROD_LEN 40
89
90#define ATA_PCI_CTL_OFS 2
91
92#define ATA_PIO0 (1U << 0)
93#define ATA_PIO1 ATA_PIO0 | (1U << 1)
94#define ATA_PIO2 ATA_PIO1 | (1U << 2)
95#define ATA_PIO3 ATA_PIO2 | (1U << 3)
96#define ATA_PIO4 ATA_PIO3 | (1U << 4)
97#define ATA_PIO5 ATA_PIO4 | (1U << 5)
98#define ATA_PIO6 ATA_PIO5 | (1U << 6)
99
100#define ATA_PIO4_ONLY (1U << 4)
101
102#define ATA_SWDMA0 (1U << 0)
103#define ATA_SWDMA1 ATA_SWDMA0 | (1U << 1)
104#define ATA_SWDMA2 ATA_SWDMA1 | (1U << 2)
105
106#define ATA_SWDMA2_ONLY (1U << 2)
107
108#define ATA_MWDMA0 (1U << 0)
109#define ATA_MWDMA1 ATA_MWDMA0 | (1U << 1)
110#define ATA_MWDMA2 ATA_MWDMA1 | (1U << 2)
111#define ATA_MWDMA3 ATA_MWDMA2 | (1U << 3)
112#define ATA_MWDMA4 ATA_MWDMA3 | (1U << 4)
113
114#define ATA_MWDMA12_ONLY (1U << 1) | (1U << 2)
115#define ATA_MWDMA2_ONLY (1U << 2)
116
117#define ATA_UDMA0 (1U << 0)
118#define ATA_UDMA1 ATA_UDMA0 | (1U << 1)
119#define ATA_UDMA2 ATA_UDMA1 | (1U << 2)
120#define ATA_UDMA3 ATA_UDMA2 | (1U << 3)
121#define ATA_UDMA4 ATA_UDMA3 | (1U << 4)
122#define ATA_UDMA5 ATA_UDMA4 | (1U << 5)
123#define ATA_UDMA6 ATA_UDMA5 | (1U << 6)
124
125/******************************************************************************
126 * Miscellanous constants copied from the Linux LIBATA code. Again, the enums
127 * have been converted to preprocessor definitions to avoid problems with
128 * signed 16-bit integers.
129 *
130 * Please note that Linux supports all kinds of IDE/EIDE/ATA/SATA/... devices
131 * in LIBATA while we only need the ATA-8 bits, and those only as far as they
132 * are relevant to AHCI.
133 */
134
135/* bits in ATA command block registers */
136#define ATA_HOB (1U << 7) /* LBA48 selector */
137#define ATA_NIEN (1U << 1) /* disable-irq flag */
138#define ATA_LBA (1U << 6) /* LBA28 selector */
139#define ATA_DEV1 (1U << 4) /* Select Device 1 (slave) */
140#define ATA_DEVICE_OBS (1U << 7) | (1U << 5) /* obs bits in dev reg */
141#define ATA_DEVCTL_OBS (1U << 3) /* obsolete bit in devctl reg */
142#define ATA_BUSY (1U << 7) /* BSY status bit */
143#define ATA_DRDY (1U << 6) /* device ready */
144#define ATA_DF (1U << 5) /* device fault */
145#define ATA_DSC (1U << 4) /* drive seek complete */
146#define ATA_DRQ (1U << 3) /* data request i/o */
147#define ATA_CORR (1U << 2) /* corrected data error */
148#define ATA_IDX (1U << 1) /* index */
149#define ATA_ERR (1U << 0) /* have an error */
150#define ATA_SRST (1U << 2) /* software reset */
151#define ATA_ICRC (1U << 7) /* interface CRC error */
152#define ATA_BBK ATA_ICRC /* pre-EIDE: block marked bad */
153#define ATA_UNC (1U << 6) /* uncorrectable media error */
154#define ATA_MC (1U << 5) /* media changed */
155#define ATA_IDNF (1U << 4) /* ID not found */
156#define ATA_MCR (1U << 3) /* media change requested */
157#define ATA_ABORTED (1U << 2) /* command aborted */
158#define ATA_TRK0NF (1U << 1) /* track 0 not found */
159#define ATA_AMNF (1U << 0) /* address mark not found */
160#define ATAPI_LFS 0xF0U /* last failed sense */
161#define ATAPI_EOM ATA_TRK0NF /* end of media */
162#define ATAPI_ILI ATA_AMNF /* illegal length indication */
163#define ATAPI_IO (1U << 1)
164#define ATAPI_COD (1U << 0)
165
166/* ATA device commands */
167#define ATA_CMD_DEV_RESET 0x08 /* ATAPI device reset */
168#define ATA_CMD_CHK_POWER 0xE5 /* check power mode */
169#define ATA_CMD_STANDBY 0xE2 /* place in standby power mode */
170#define ATA_CMD_IDLE 0xE3 /* place in idle power mode */
171#define ATA_CMD_EDD 0x90 /* execute device diagnostic */
172#define ATA_CMD_DOWNLOAD_MICRO 0x92
173#define ATA_CMD_NOP 0x00
174#define ATA_CMD_FLUSH 0xE7
175#define ATA_CMD_FLUSH_EXT 0xEA
176#define ATA_CMD_ID_ATA 0xEC
177#define ATA_CMD_ID_ATAPI 0xA1
178#define ATA_CMD_SERVICE 0xA2
179#define ATA_CMD_READ 0xC8
180#define ATA_CMD_READ_EXT 0x25
181#define ATA_CMD_READ_QUEUED 0x26
182#define ATA_CMD_READ_STREAM_EXT 0x2B
183#define ATA_CMD_READ_STREAM_DMA_EXT 0x2A
184#define ATA_CMD_WRITE 0xCA
185#define ATA_CMD_WRITE_EXT 0x35
186#define ATA_CMD_WRITE_QUEUED 0x36
187#define ATA_CMD_WRITE_STREAM_EXT 0x3B
188#define ATA_CMD_WRITE_STREAM_DMA_EXT 0x3A
189#define ATA_CMD_WRITE_FUA_EXT 0x3D
190#define ATA_CMD_WRITE_QUEUED_FUA_EXT 0x3E
191#define ATA_CMD_FPDMA_READ 0x60
192#define ATA_CMD_FPDMA_WRITE 0x61
193#define ATA_CMD_PIO_READ 0x20
194#define ATA_CMD_PIO_READ_EXT 0x24
195#define ATA_CMD_PIO_WRITE 0x30
196#define ATA_CMD_PIO_WRITE_EXT 0x34
197#define ATA_CMD_READ_MULTI 0xC4
198#define ATA_CMD_READ_MULTI_EXT 0x29
199#define ATA_CMD_WRITE_MULTI 0xC5
200#define ATA_CMD_WRITE_MULTI_EXT 0x39
201#define ATA_CMD_WRITE_MULTI_FUA_EXT 0xCE
202#define ATA_CMD_SET_FEATURES 0xEF
203#define ATA_CMD_SET_MULTI 0xC6
204#define ATA_CMD_PACKET 0xA0
205#define ATA_CMD_VERIFY 0x40
206#define ATA_CMD_VERIFY_EXT 0x42
207#define ATA_CMD_WRITE_UNCORR_EXT 0x45
208#define ATA_CMD_STANDBYNOW1 0xE0
209#define ATA_CMD_IDLEIMMEDIATE 0xE1
210#define ATA_CMD_SLEEP 0xE6
211#define ATA_CMD_INIT_DEV_PARAMS 0x91
212#define ATA_CMD_READ_NATIVE_MAX 0xF8
213#define ATA_CMD_READ_NATIVE_MAX_EXT 0x27
214#define ATA_CMD_SET_MAX 0xF9
215#define ATA_CMD_SET_MAX_EXT 0x37
216#define ATA_CMD_READ_LOG_EXT 0x2F
217#define ATA_CMD_WRITE_LOG_EXT 0x3F
218#define ATA_CMD_READ_LOG_DMA_EXT 0x47
219#define ATA_CMD_WRITE_LOG_DMA_EXT 0x57
220#define ATA_CMD_TRUSTED_RCV 0x5C
221#define ATA_CMD_TRUSTED_RCV_DMA 0x5D
222#define ATA_CMD_TRUSTED_SND 0x5E
223#define ATA_CMD_TRUSTED_SND_DMA 0x5F
224#define ATA_CMD_PMP_READ 0xE4
225#define ATA_CMD_PMP_WRITE 0xE8
226#define ATA_CMD_CONF_OVERLAY 0xB1
227#define ATA_CMD_SEC_SET_PASS 0xF1
228#define ATA_CMD_SEC_UNLOCK 0xF2
229#define ATA_CMD_SEC_ERASE_PREP 0xF3
230#define ATA_CMD_SEC_ERASE_UNIT 0xF4
231#define ATA_CMD_SEC_FREEZE_LOCK 0xF5
232#define ATA_CMD_SEC_DISABLE_PASS 0xF6
233#define ATA_CMD_CONFIG_STREAM 0x51
234#define ATA_CMD_SMART 0xB0
235#define ATA_CMD_MEDIA_LOCK 0xDE
236#define ATA_CMD_MEDIA_UNLOCK 0xDF
237#define ATA_CMD_DSM 0x06
238#define ATA_CMD_CHK_MED_CRD_TYP 0xD1
239#define ATA_CMD_CFA_REQ_EXT_ERR 0x03
240#define ATA_CMD_CFA_WRITE_NE 0x38
241#define ATA_CMD_CFA_TRANS_SECT 0x87
242#define ATA_CMD_CFA_ERASE 0xC0
243#define ATA_CMD_CFA_WRITE_MULT_NE 0xCD
244/* marked obsolete in the ATA/ATAPI-7 spec */
245#define ATA_CMD_RESTORE 0x10
246
247/* READ_LOG_EXT pages */
248#define ATA_LOG_SATA_NCQ 0x10
249
250/* READ/WRITE LONG (obsolete) */
251#define ATA_CMD_READ_LONG 0x22
252#define ATA_CMD_READ_LONG_ONCE 0x23
253#define ATA_CMD_WRITE_LONG 0x32
254#define ATA_CMD_WRITE_LONG_ONCE 0x33
255
256/* SETFEATURES stuff */
257#define SETFEATURES_XFER 0x03
258#define XFER_UDMA_7 0x47
259#define XFER_UDMA_6 0x46
260#define XFER_UDMA_5 0x45
261#define XFER_UDMA_4 0x44
262#define XFER_UDMA_3 0x43
263#define XFER_UDMA_2 0x42
264#define XFER_UDMA_1 0x41
265#define XFER_UDMA_0 0x40
266#define XFER_MW_DMA_4 0x24 /* CFA only */
267#define XFER_MW_DMA_3 0x23 /* CFA only */
268#define XFER_MW_DMA_2 0x22
269#define XFER_MW_DMA_1 0x21
270#define XFER_MW_DMA_0 0x20
271#define XFER_SW_DMA_2 0x12
272#define XFER_SW_DMA_1 0x11
273#define XFER_SW_DMA_0 0x10
274#define XFER_PIO_6 0x0E /* CFA only */
275#define XFER_PIO_5 0x0D /* CFA only */
276#define XFER_PIO_4 0x0C
277#define XFER_PIO_3 0x0B
278#define XFER_PIO_2 0x0A
279#define XFER_PIO_1 0x09
280#define XFER_PIO_0 0x08
281#define XFER_PIO_SLOW 0x00
282
283#define SETFEATURES_WC_ON 0x02 /* Enable write cache */
284#define SETFEATURES_WC_OFF 0x82 /* Disable write cache */
285
286/* Enable/Disable Automatic Acoustic Management */
287#define SETFEATURES_AAM_ON 0x42
288#define SETFEATURES_AAM_OFF 0xC2
289
290#define SETFEATURES_SPINUP 0x07 /* Spin-up drive */
291
292#define SETFEATURES_SATA_ENABLE 0x10 /* Enable use of SATA feature */
293#define SETFEATURES_SATA_DISABLE 0x90 /* Disable use of SATA feature */
294
295/* SETFEATURE Sector counts for SATA features */
296#define SATA_FPDMA_OFFSET 0x01 /* FPDMA non-zero buffer offsets */
297#define SATA_FPDMA_AA 0x02 /* FPDMA Setup FIS Auto-Activate */
298#define SATA_DIPM 0x03 /* Device Initiated Power Management */
299#define SATA_FPDMA_IN_ORDER 0x04 /* FPDMA in-order data delivery */
300#define SATA_AN 0x05 /* Asynchronous Notification */
301#define SATA_SSP 0x06 /* Software Settings Preservation */
302
303/* feature values for SET_MAX */
304#define ATA_SET_MAX_ADDR 0x00
305#define ATA_SET_MAX_PASSWD 0x01
306#define ATA_SET_MAX_LOCK 0x02
307#define ATA_SET_MAX_UNLOCK 0x03
308#define ATA_SET_MAX_FREEZE_LOCK 0x04
309
310/* feature values for DEVICE CONFIGURATION OVERLAY */
311#define ATA_DCO_RESTORE 0xC0
312#define ATA_DCO_FREEZE_LOCK 0xC1
313#define ATA_DCO_IDENTIFY 0xC2
314#define ATA_DCO_SET 0xC3
315
316/* feature values for SMART */
317#define ATA_SMART_ENABLE 0xD8
318#define ATA_SMART_READ_VALUES 0xD0
319#define ATA_SMART_READ_THRESHOLDS 0xD1
320
321/* feature values for Data Set Management */
322#define ATA_DSM_TRIM 0x01
323
324/* password used in LBA Mid / LBA High for executing SMART commands */
325#define ATA_SMART_LBAM_PASS 0x4F
326#define ATA_SMART_LBAH_PASS 0xC2
327
328/* ATAPI stuff */
329#define ATAPI_PKT_DMA (1U << 0)
330#define ATAPI_DMADIR (1U << 2) /* ATAPI data dir:
331 0=to device, 1=to host */
332#define ATAPI_CDB_LEN 16
333
334/* PMP stuff */
335#define SATA_PMP_MAX_PORTS 15
336#define SATA_PMP_CTRL_PORT 15
337
338#define SATA_PMP_GSCR_DWORDS 128
339#define SATA_PMP_GSCR_PROD_ID 0
340#define SATA_PMP_GSCR_REV 1
341#define SATA_PMP_GSCR_PORT_INFO 2
342#define SATA_PMP_GSCR_ERROR 32
343#define SATA_PMP_GSCR_ERROR_EN 33
344#define SATA_PMP_GSCR_FEAT 64
345#define SATA_PMP_GSCR_FEAT_EN 96
346
347#define SATA_PMP_PSCR_STATUS 0
348#define SATA_PMP_PSCR_ERROR 1
349#define SATA_PMP_PSCR_CONTROL 2
350
351#define SATA_PMP_FEAT_BIST (1U << 0)
352#define SATA_PMP_FEAT_PMREQ (1U << 1)
353#define SATA_PMP_FEAT_DYNSSC (1U << 2)
354#define SATA_PMP_FEAT_NOTIFY (1U << 3)
355
356/* SATA Status and Control Registers */
357#define SCR_STATUS 0
358#define SCR_ERROR 1
359#define SCR_CONTROL 2
360#define SCR_ACTIVE 3
361#define SCR_NOTIFICATION 4
362
363/* SError bits */
364#define SERR_DATA_RECOVERED (1UL << 0) /* recovered data error */
365#define SERR_COMM_RECOVERED (1UL << 1) /* recovered comm failure */
366#define SERR_DATA (1UL << 8) /* unrecovered data error */
367#define SERR_PERSISTENT (1UL << 9) /* persistent data/comm error */
368#define SERR_PROTOCOL (1UL << 10) /* protocol violation */
369#define SERR_INTERNAL (1UL << 11) /* host internal error */
370#define SERR_PHYRDY_CHG (1UL << 16) /* PHY RDY changed */
371#define SERR_PHY_INT_ERR (1UL << 17) /* PHY internal error */
372#define SERR_COMM_WAKE (1UL << 18) /* Comm wake */
373#define SERR_10B_8B_ERR (1UL << 19) /* 10b to 8b decode error */
374#define SERR_DISPARITY (1UL << 20) /* Disparity */
375#define SERR_CRC (1UL << 21) /* CRC error */
376#define SERR_HANDSHAKE (1UL << 22) /* Handshake error */
377#define SERR_LINK_SEQ_ERR (1UL << 23) /* Link sequence error */
378#define SERR_TRANS_ST_ERROR (1UL << 24) /* Transport state trans. error */
379#define SERR_UNRECOG_FIS (1UL << 25) /* Unrecognized FIS */
380#define SERR_DEV_XCHG (1UL << 26) /* device exchanged */
381
382/******************************************************************************
383 * Parameters for ATA commands. Those parameters are passed in a variable
384 * argument list in the format:
385 *
386 * AP_xxx, [val, ...], AP_xxx, [val, ...]
387 *
388 * The values expected by each parameter are indicated within square brackets.
389 */
390typedef enum {
391 AP_FEATURES, /* [u16] ATA command features (read: flags) */
392 AP_COUNT, /* [u16] number of sectors (0 = 65536) */
393 AP_SECTOR_28, /* [u32] 28-bit sector address */
394 AP_SECTOR_48, /* [u32, u16] 48-bit sector address */
395 AP_DEVICE, /* [u16] ATA command "device" field (LSB ignored) */
396 AP_SGLIST, /* [void _far *, u16] buffer S/G (SCATGATENTRY/count) */
397 AP_VADDR, /* [void _far *, u16] buffer virtual address (buf/len) */
[8]398 AP_WRITE, /* [] indicates a DMA write operation */
[4]399 AP_AHCI_FLAGS, /* [u16] AHCI command header flags */
400 AP_ATAPI_CMD, /* [void _far *, u16] ATAPI command (CDB) and length */
401 AP_END /* [] end of variable argument list */
402} ATA_PARM;
403
404/* ------------------------ typedefs and structures ------------------------ */
405
406/******************************************************************************
407 * Generic ATA-8 command structure. This is based on ATA-8, i.e. we won't have
408 * to deal with different command structures depending on whether a device is
409 * 48-bit capable, etc. because this is handled by the transport (AHCI in our
410 * case). Unsupported bits have to be cleared to zero, of course (e.g. the
411 * high 20 bits of the LBA when talking to a device that supports only 28
412 * bits).
413 */
414typedef struct {
415 u16 features; /* feature bits */
416 u16 count; /* count register (e.g. number of sectors) */
417 u32 lba_l; /* low 28 bits of LBA (32 bits for 48-bit devices) */
418 u16 lba_h; /* high 16 bits of LBA for 48-bit devices */
419 u8 cmd; /* ATA command field */
420 u8 device; /* ATA device field */
421} ATA_CMD;
422
423/* generic ATA-8 response structure */
424typedef struct {
425 u16 error; /* error code, if any */
426 u16 count; /* count register (e.g. number of sectors) */
427 u32 lba_l; /* low 28 bits of LBA (32 bits for 48-bit devices) */
428 u16 lba_h; /* high 16 bits of LBA for 48-bit devices */
429 u16 status; /* response status bits */
430} ATA_RSP;
431
432/******************************************************************************
433 * Command-specific ATA-8 structures.
434 */
435
436/* -------------------------- function prototypes -------------------------- */
437
438extern int ata_cmd (AD_INFO *ai, int port, int device,
439 int slot, int cmd, ...);
440extern int v_ata_cmd (AD_INFO *ai, int port, int device,
441 int slot, int cmd, va_list va);
442extern void ata_cmd_to_fis (u8 _far *fis, ATA_CMD _far *cmd,
443 int device);
[8]444extern USHORT ata_get_sg_indx (IORB_EXECUTEIO _far *io);
445extern void ata_max_sg_cnt (IORB_EXECUTEIO _far *io, USHORT sg_indx,
446 USHORT sg_max, USHORT _far *sg_cnt,
447 USHORT _far *sector_cnt);
[4]448
449extern int ata_get_geometry (IORBH _far *iorb, int slot);
450extern void ata_get_geometry_pp (IORBH _far *iorb);
451extern int ata_unit_ready (IORBH _far *iorb, int slot);
452extern int ata_read (IORBH _far *iorb, int slot);
[8]453extern void ata_read_pp (IORBH _far *iorb);
[4]454extern int ata_verify (IORBH _far *iorb, int slot);
455extern int ata_write (IORBH _far *iorb, int slot);
[8]456extern void ata_write_pp (IORBH _far *iorb);
[4]457extern int ata_execute_ata (IORBH _far *iorb, int slot);
458extern int ata_req_sense (IORBH _far *iorb, int slot);
[8]459
[4]460extern char *ata_dev_name (u16 *id_buf);
[8]461
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