source: trunk/src/ata.c@ 4

Last change on this file since 4 was 4, checked in by root, 15 years ago

initial checkin of CM's code
File size: 19.8 KB
Line 
1/******************************************************************************
2 * ata.c - ATA command processing
3 *
4 * Copyright (c) 2010 Christian Mueller. Parts copied from/inspired by the
5 * Linux AHCI driver; those parts are (c) Linux AHCI/ATA maintainers
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include "os2ahci.h"
23#include "ata.h"
24
25/* -------------------------- macros and constants ------------------------- */
26
27/* ------------------------ typedefs and structures ------------------------ */
28
29/* -------------------------- function prototypes -------------------------- */
30
31/* ------------------------ global/static variables ------------------------ */
32
33/* ----------------------------- start of code ----------------------------- */
34
35/******************************************************************************
36 * Initialize AHCI command slot, FIS and S/G list for the specified ATA
37 * command. The command parameters are passed as a variable argument list
38 * of type and value(s). The list is terminated by AP_END.
39 *
40 * Notes:
41 *
42 * - The specified command slot is expected to be idle; no checks are
43 * performed to prevent messing with a busy port.
44 *
45 * - Port multipliers are not supported, yet, thus 'd' should always
46 * be 0 for the time being.
47 *
48 * - 'cmd' is passwd as 16-bit integer because the compiler would push
49 * a 'u8' as 16-bit value (it's a fixed argument) and the stdarg
50 * macros would screw up the address of the first variable argument
51 * if the size of the last fixed argument wouldn't match what the
52 * compiler pushed on the stack.
53 *
54 * Return values:
55 * 0 : success
56 * > 0 : could not map all S/G entries; the return value is the number of
57 * S/G entries that could be mapped.
58 * < 0 : other error
59 */
60int ata_cmd(AD_INFO *ai, int p, int d, int slot, int cmd, ...)
61{
62 va_list va;
63 va_start(va, cmd);
64 return(v_ata_cmd(ai, p, d, slot, cmd, va));
65}
66
67int v_ata_cmd(AD_INFO *ai, int p, int d, int slot, int cmd, va_list va)
68{
69 AHCI_PORT_DMA _far *dma_base_virt;
70 AHCI_CMD_HDR _far *cmd_hdr;
71 AHCI_CMD_TBL _far *cmd_tbl;
72 SCATGATENTRY _far *sg_list = NULL;
73 SCATGATENTRY sg_single;
74 ATA_PARM ap;
75 ATA_CMD ata_cmd;
76 void _far *atapi_cmd = NULL;
77 u32 dma_base_phys;
78 u16 atapi_cmd_len = 0;
79 u16 ahci_flags = 0;
80 u16 sg_cnt = 0;
81 int i;
82 int n;
83
84 /* --------------------------------------------------------------------------
85 * Initialize ATA command. The ATA command is set up with the main command
86 * value and a variable list of additional parameters such as the sector
87 * address, transfer count, ...
88 */
89 memset(&ata_cmd, 0x00, sizeof(ata_cmd));
90 ata_cmd.cmd = (u8) cmd;
91
92 /* parse variable arguments */
93 do {
94 switch ((ap = va_arg(va, ATA_PARM))) {
95
96 case AP_AHCI_FLAGS:
97 ahci_flags |= va_arg(va, u16);
98 break;
99
100 case AP_H2D:
101 ahci_flags |= AHCI_CMD_WRITE;
102 break;
103
104 case AP_FEATURES:
105 /* ATA features word */
106 ata_cmd.features = va_arg(va, u16);
107 break;
108
109 case AP_COUNT:
110 /* transfer count */
111 ata_cmd.count = va_arg(va, u16);
112 break;
113
114 case AP_SECTOR_28:
115 /* 28-bit sector address */
116 ata_cmd.lba_l = va_arg(va, u32);
117 if (ata_cmd.lba_l & 0xf0000000UL) {
118 dprintf("error: LBA-28 address %ld has more than 28 bits\n", ata_cmd.lba_l);
119 return(-1);
120 }
121 break;
122
123 case AP_SECTOR_48:
124 /* 48-bit sector address */
125 ata_cmd.lba_l = va_arg(va, u32);
126 ata_cmd.lba_h = va_arg(va, u16);
127 break;
128
129 case AP_DEVICE:
130 /* ATA device byte */
131 ata_cmd.device = va_arg(va, u16) >> 8;
132 break;
133
134 case AP_SGLIST:
135 /* scatter/gather list in SCATGATENTRY/count format */
136 sg_list = va_arg(va, void _far *);
137 sg_cnt = va_arg(va, u16);
138 break;
139
140 case AP_VADDR:
141 /* virtual buffer address in addr/len format (up to 4K) */
142 DevHelp_VirtToPhys(va_arg(va, void _far *), &sg_single.ppXferBuf);
143 sg_single.XferBufLen = va_arg(va, u16);
144 sg_list = &sg_single;
145 sg_cnt = 1;
146 break;
147
148 case AP_ATAPI_CMD:
149 atapi_cmd = va_arg(va, void _far *);
150 atapi_cmd_len = va_arg(va, u16);
151 ahci_flags |= AHCI_CMD_ATAPI;
152 break;
153
154 case AP_END:
155 break;
156
157 default:
158 dprintf("error: v_ata_cmd() called with invalid parameter type (%d)\n", (int) ap);
159 return(-1);
160 }
161
162 } while (ap != AP_END);
163
164 /* --------------------------------------------------------------------------
165 * Fill in AHCI ATA command information. This includes the port command slot,
166 * the corresponding command FIS and the S/G list. The layout of the AHCI
167 * port DMA region is based on the Linux AHCI driver and looks like this:
168 *
169 * - 32 AHCI command headers (AHCI_CMD_HDR) with 32 bytes, each
170 * - 1 FIS receive area with 256 bytes (AHCI_RX_FIS_SZ)
171 * - 32 AHCI command tables, each consisting of
172 * - 64 bytes for command FIS
173 * - 16 bytes for ATAPI comands
174 * - 48 bytes reserved
175 * - 48 S/G entries (AHCI_SG) with 32 bytes, each
176 *
177 * Since the whole DMA buffer for all ports is larger than 64KB and we need
178 * multiple segments to address all of them, there are no virtual pointers
179 * to the individual elements in AD_INFO. Instead, we're relying on macros
180 * for getting the base address of a particular port's DMA region, then
181 * map a structure on top of that for convenience (AHCI_PORT_DMA).
182 */
183 dma_base_virt = port_dma_base(ai, p);
184 dma_base_phys = port_dma_base_phys(ai, p);
185
186 /* AHCI command header */
187 cmd_hdr = dma_base_virt->cmd_hdr + slot;
188 memset(cmd_hdr, 0x00, sizeof(*cmd_hdr));
189 cmd_hdr->options = ((d & 0x0f) << 12);
190 cmd_hdr->options |= ahci_flags; /* AHCI commaand flags */
191 cmd_hdr->options |= 5; /* length of command FIS in 32-bit words */
192 cmd_hdr->tbl_addr = dma_base_phys + offsetof(AHCI_PORT_DMA, cmd_tbl[slot]);
193
194 /* AHCI command table */
195 cmd_tbl = dma_base_virt->cmd_tbl + slot;
196 memset(cmd_tbl, 0x00, sizeof(*cmd_tbl));
197 ata_cmd_to_fis(cmd_tbl->cmd_fis, &ata_cmd, d);
198
199 if (atapi_cmd != NULL) {
200 /* copy ATAPI command */
201 memcpy(cmd_tbl->atapi_cmd, atapi_cmd, atapi_cmd_len);
202 }
203
204 /* PRDT (S/G list)
205 *
206 * - The S/G list for AHCI adapters is limited to 22 bits for the transfer
207 * size of each element, thus we need to split S/G elements larger than
208 * 22 bits into 2 AHCI_SG elements.
209 *
210 * - The S/G element size for AHCI is what the spec calls "'0' based"
211 * (i.e. 0 means 1 bytes). On top of that, the spec requires S/G transfer
212 * sizes to be even in the context of 16-bit transfers, thus bit '1'
213 * always needs to be set.
214 *
215 * - AHCI_MAX_SG_ELEMENT_LEN defines the maximum size of an AHCI S/G
216 * element in bytes, ignoring the '0'-based methodology (i.e. 1 << 22).
217 *
218 * - There's a limit on the maximum number of S/G elements in the port DMA
219 * buffer (AHCI_MAX_SG) which is lower than the HW maximum. It's beyond
220 * the control of this function to split commands which require more
221 * than AHCI_MAX_SG entries. In order to help the caller, the return value
222 * of this function will indicate how many OS/2 S/G entries were
223 * successfully be mapped.
224 *
225 */
226 for (i = n = 0; i < sg_cnt; i++) {
227 u32 sg_addr = sg_list[i].ppXferBuf;
228 u32 sg_size = sg_list[i].XferBufLen;
229
230 do {
231 u32 chunk = (sg_size > AHCI_MAX_SG_ELEMENT_LEN) ? AHCI_MAX_SG_ELEMENT_LEN
232 : sg_size;
233 if (n >= AHCI_MAX_SG) {
234 /* couldn't store all S/G elements in our DMA buffer */
235 ddprintf("ata_cmd(): too many S/G elements\n");
236 return(i - 1);
237 }
238 ddprintf("s/g list element: addr = 0x%08lx, size = 0x%04lx\n", sg_addr, chunk);
239 cmd_tbl->sg_list[n].addr = sg_addr;
240 cmd_tbl->sg_list[n].size = chunk - 1;
241 sg_addr += chunk;
242 sg_size -= chunk;
243 n++;
244 } while (sg_size > 0);
245 }
246
247 /* set final S/G count in AHCI command header */
248 cmd_hdr->options |= (u32) n << 16;
249
250 if (debug >= 2) {
251 printf("ATA command for %d.%d.%d:\n", ad_no(ai), p, d);
252 phex(cmd_hdr, offsetof(AHCI_CMD_HDR, reserved), "cmd_hdr: ");
253 phex(&ata_cmd, sizeof(ata_cmd), "ata_cmd: ");
254 if (atapi_cmd != NULL) {
255 phex(atapi_cmd, atapi_cmd_len, "atapi_cmd: ");
256 }
257 if (n > 0) {
258 phex(cmd_tbl->sg_list, sizeof(*cmd_tbl->sg_list) * n, "sg_list: ");
259 }
260 }
261
262 return(0);
263}
264
265/******************************************************************************
266 * Fill SATA command FIS with values extracted from an ATA command structure.
267 * The command FIS buffer (fis) is expected to be initialized to 0s. The
268 * structure of the FIS maps to the ATA shadow register block, including
269 * registers which can be written twice to store 16 bits (called 'exp').
270 *
271 * The FIS structure looks like this (using LSB notation):
272 *
273 * +----------------+----------------+----------------+----------------+
274 * 00 | FIS type (27h) | C|R|R|R|PMP | Command | Features |
275 * +----------------+----------------+----------------+----------------+
276 * 04 | LBA 7:0 | LBA 15:8 | LBA 23:16 | R|R|R|D|Head |
277 * +----------------+----------------+----------------+----------------+
278 * 08 | LBA 31:24 | LBA 40:32 | LBA 47:40 | Features exp |
279 * +----------------+----------------+----------------+----------------+
280 * 12 | Count 7:0 | Count 15:8 | Reserved | Control |
281 * +----------------+----------------+----------------+----------------+
282 * 16 | Reserved | Reserved | Reserved | Reserved |
283 * +----------------+----------------+----------------+----------------+
284 */
285void ata_cmd_to_fis(u8 _far *fis, ATA_CMD _far *ata_cmd, int d)
286{
287 fis[0] = 0x27; /* register - host to device FIS */
288 fis[1] = (u8) (d & 0xf); /* port multiplier number */
289 fis[1] |= 0x80; /* bit 7 indicates Command FIS */
290 fis[2] = (u8) ata_cmd->cmd;
291 fis[3] = (u8) ata_cmd->features;
292
293 fis[4] = (u8) ata_cmd->lba_l;
294 fis[5] = (u8) (ata_cmd->lba_l >> 8);
295 fis[6] = (u8) (ata_cmd->lba_l >> 16);
296 fis[7] = (u8) ata_cmd->device;
297
298 fis[8] = (u8) (ata_cmd->lba_l >> 24);
299 fis[9] = (u8) ata_cmd->lba_h;
300 fis[10] = (u8) (ata_cmd->lba_h >> 8);
301 fis[11] = (u8) (ata_cmd->features >> 8);
302
303 fis[12] = (u8) ata_cmd->count;
304 fis[13] = (u8) (ata_cmd->count >> 8);
305}
306
307/******************************************************************************
308 * Get device or media geometry. Device and media geometry are expected to be
309 * the same for non-removable devices, which will always be the case for the
310 * ATA devices we're dealing with (hard disks). ATAPI is a different story
311 * and handled by atapi_get_geometry().
312 */
313int ata_get_geometry(IORBH _far *iorb, int slot)
314{
315 ADD_WORKSPACE _far *aws = add_workspace(iorb);
316 int rc;
317
318 /* allocate buffer for ATA identify information */
319 if ((aws->buf = malloc(ATA_ID_WORDS * sizeof(u16))) == NULL) {
320 iorb_seterr(iorb, IOERR_CMD_SW_RESOURCE);
321 return(-1);
322 }
323
324 /* request ATA identify information */
325 aws->ppfunc = ata_get_geometry_pp;
326 rc = ata_cmd(ad_infos + iorb_unit_adapter(iorb),
327 iorb_unit_port(iorb),
328 iorb_unit_device(iorb),
329 slot,
330 ATA_CMD_ID_ATA,
331 AP_VADDR, (void _far *) aws->buf, ATA_ID_WORDS * sizeof(u16),
332 AP_END);
333
334 if (rc != 0) {
335 free(aws->buf);
336 aws->buf = NULL;
337 iorb_seterr(iorb, IOERR_CMD_ADD_SOFTWARE_FAILURE);
338 }
339
340 return(rc);
341}
342
343/******************************************************************************
344 * Post processing function for ata_get_geometry(): convert the ATA identify
345 * information to OS/2 IOCC_GEOMETRY information.
346 */
347void ata_get_geometry_pp(IORBH _far *iorb)
348{
349 GEOMETRY _far *geometry = ((IORB_GEOMETRY _far *) iorb)->pGeometry;
350 USHORT geometry_len = ((IORB_GEOMETRY _far *) iorb)->GeometryLen;
351 u16 *id_buf = add_workspace(iorb)->buf;
352
353 /* Fill-in geometry information; os2ahci has been designed for devices
354 * adhering to the ATA spec v8 or later, thus the real geometry doesn't
355 * really matter (it's actually marked "obsolete" in the ATA 8 specs).
356 * In order to maintain compatibitily to the BIOS and partition tables,
357 * we'll use the same algorithm as used by typical PC BIOS versions:
358 *
359 * - 512 bytes per sector
360 * - 255 heads
361 * - 63 sectors per track
362 * - x cylinders (calculated)
363 *
364 * Please note that os2ahci currently does not support ATA sectors larger
365 * than 512 bytes, therefore relies on the translation logic built into the
366 * corresponding ATA disks. In theory, partitions should be aligned to the
367 * large sectors to prevent needless mapping all over the place but HPFS
368 * uses logical block sizes smaller than the typical large sectors found on
369 * modern hard disks so this won't make much of a difference. Large sector
370 * support will be evaluated at a later time (it's unclear right now whether
371 * HPFS would even support anything larger than 512 bytes).
372 *
373 * Another limitation is that OS/2 has a 32-bit variable for the total number
374 * of sectors, limiting the maximum capacity to roughly 2TB. This is another
375 * issue that needs to be addressed sooner or later; large sectors could
376 * raise this limit to something like 8TB but this is not really much of a
377 * difference. Maybe there's something in later DDKs that allows more than
378 * 32 bits?
379 */
380 memset(geometry, 0x00, geometry_len);
381
382 /* extract total number of sectors */
383 if (id_buf[ATA_ID_CFS_ENABLE_2] & 0x40) {
384 /* 48-bit LBA supported */
385 if (id_buf[ATA_ID_LBA_CAPACITY_2 + 2] != 0) {
386 /* more than 32 bits for number of sectors */
387 dprintf("warning: limiting disk %d.%d.%d to 2TB\n",
388 iorb_unit_adapter(iorb), iorb_unit_port(iorb),
389 iorb_unit_device(iorb));
390 geometry->TotalSectors = 0xffffffffUL;
391 } else {
392 geometry->TotalSectors = *((u32 *) (id_buf + ATA_ID_LBA_CAPACITY_2));
393 }
394 } else {
395 /* 28-bit LBA */
396 geometry->TotalSectors = *((u32 *) (id_buf + ATA_ID_LBA_CAPACITY)) &
397 0x0fffffffUL;
398 }
399
400 geometry->BytesPerSector = 512;
401 geometry->NumHeads = 255;
402 geometry->SectorsPerTrack = 63;
403 geometry->TotalCylinders = geometry->TotalSectors /
404 ((u32) geometry->NumHeads *
405 (u32) geometry->SectorsPerTrack);
406}
407
408/******************************************************************************
409 * Test whether unit is ready.
410 */
411int ata_unit_ready(IORBH _far *iorb, int slot)
412{
413 /* This is a NOP for ATA devices (at least right now); returning an error
414 * without setting an error code means ahci_exec_iorb() will not queue any
415 * HW command and the IORB will complete successfully.
416 */
417 ((IORB_UNIT_STATUS _far *) iorb)->UnitStatus = US_READY | US_POWER;
418 return(-1);
419}
420
421/******************************************************************************
422 * Read sectors from AHCI device.
423 */
424int ata_read(IORBH _far *iorb, int slot)
425{
426 IORB_EXECUTEIO _far *io = (IORB_EXECUTEIO _far *) iorb;
427 AD_INFO *ai = ad_infos + iorb_unit_adapter(iorb);
428 int p = iorb_unit_port(iorb);
429 int d = iorb_unit_device(iorb);
430 int rc;
431
432 /* prepare read command */
433 if (io->RBA >= (1UL << 28) || io->BlockCount > 256) {
434 /* need LBA48 for this command */
435 if (!ai->ports[p].devs[d].lba48) {
436 iorb_seterr(iorb, IOERR_RBA_LIMIT);
437 return(-1);
438 }
439 rc = ata_cmd(ai, p, d, slot, ATA_CMD_READ_EXT,
440 AP_SECTOR_48, (u32) io->RBA, (u16) 0,
441 AP_COUNT, (u16) io->BlockCount,
442 AP_SGLIST, io->pSGList, (u16) io->cSGList,
443 AP_DEVICE, 0x4000,
444 AP_END);
445 } else {
446 rc = ata_cmd(ai, p, d, slot, ATA_CMD_READ,
447 AP_SECTOR_28, (u32) io->RBA,
448 AP_COUNT, (u16) io->BlockCount & 0xffU,
449 AP_SGLIST, io->pSGList, (u16) io->cSGList,
450 AP_DEVICE, 0x4000,
451 AP_END);
452 }
453
454 return(rc);
455}
456
457/******************************************************************************
458 * Verify readability of sectors on AHCI device.
459 */
460int ata_verify(IORBH _far *iorb, int slot)
461{
462 IORB_EXECUTEIO _far *io = (IORB_EXECUTEIO _far *) iorb;
463 AD_INFO *ai = ad_infos + iorb_unit_adapter(iorb);
464 int p = iorb_unit_port(iorb);
465 int d = iorb_unit_device(iorb);
466 int rc;
467
468 /* prepare verify command */
469 if (io->RBA >= (1UL << 28) || io->BlockCount > 256) {
470 /* need LBA48 for this command */
471 if (!ai->ports[p].devs[d].lba48) {
472 iorb_seterr(iorb, IOERR_RBA_LIMIT);
473 return(-1);
474 }
475 rc = ata_cmd(ai, p, d, slot, ATA_CMD_VERIFY_EXT,
476 AP_SECTOR_48, (u32) io->RBA, (u16) 0,
477 AP_COUNT, (u16) io->BlockCount,
478 AP_SGLIST, io->pSGList, (u16) io->cSGList,
479 AP_DEVICE, 0x4000,
480 AP_END);
481 } else {
482 rc = ata_cmd(ai, p, d, slot, ATA_CMD_VERIFY,
483 AP_SECTOR_28, (u32) io->RBA,
484 AP_COUNT, (u16) io->BlockCount & 0xffU,
485 AP_SGLIST, io->pSGList, (u16) io->cSGList,
486 AP_END);
487 }
488
489 return(rc);
490}
491
492/******************************************************************************
493 * Write sectors to AHCI device.
494 */
495int ata_write(IORBH _far *iorb, int slot)
496{
497 IORB_EXECUTEIO _far *io = (IORB_EXECUTEIO _far *) iorb;
498 AD_INFO *ai = ad_infos + iorb_unit_adapter(iorb);
499 int p = iorb_unit_port(iorb);
500 int d = iorb_unit_device(iorb);
501 int rc;
502
503 /* prepare write command */
504 if (io->RBA >= (1UL << 28) || io->BlockCount > 256) {
505 /* need LBA48 for this command */
506 if (!ai->ports[p].devs[d].lba48) {
507 iorb_seterr(iorb, IOERR_RBA_LIMIT);
508 return(-1);
509 }
510 rc = ata_cmd(ai, p, d, slot, ATA_CMD_WRITE_EXT,
511 AP_SECTOR_48, (u32) io->RBA, (u16) 0,
512 AP_COUNT, (u16) io->BlockCount,
513 AP_SGLIST, io->pSGList, (u16) io->cSGList,
514 AP_DEVICE, 0x4000,
515 AP_END);
516 } else {
517 rc = ata_cmd(ai, p, d, slot, ATA_CMD_WRITE,
518 AP_SECTOR_28, (u32) io->RBA,
519 AP_COUNT, (u16) io->BlockCount & 0xffU,
520 AP_SGLIST, io->pSGList, (u16) io->cSGList,
521 AP_DEVICE, 0x4000,
522 AP_END);
523 }
524
525 return(rc);
526}
527
528/******************************************************************************
529 * Execute ATA command.
530 */
531int ata_execute_ata(IORBH _far *iorb, int slot)
532{
533 iorb_seterr(iorb, IOERR_CMD_NOT_SUPPORTED);
534 return(-1);
535}
536
537/******************************************************************************
538 * Request sense information (which means "read ATA log page" for ATA devices)
539 */
540int ata_req_sense(IORBH _far *iorb, int slot)
541{
542 iorb_seterr(iorb, IOERR_CMD_NOT_SUPPORTED);
543 return(-1);
544}
545
546/******************************************************************************
547 * Extract vendor and device name from an ATA INDENTIFY buffer. Since strings
548 * in the indentify buffer are byte-swapped, we need to swap them back.
549 */
550char *ata_dev_name(u16 *id_buf)
551{
552 static char dev_name[ATA_ID_PROD_LEN + 1];
553 char *t = dev_name;
554 char *s = (char *) (id_buf + ATA_ID_PROD);
555 int i;
556
557 dev_name[sizeof(dev_name)-1] = '\0';
558
559 for (i = 0; i < ATA_ID_PROD_LEN / 2; i++) {
560 *(t++) = s[1];
561 *(t++) = s[0];
562 s += 2;
563 }
564
565 return(dev_name);
566}
567
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