Article

Dynamic hardware plugins in an FPGA with partial run-time reconfiguration

Authors:

Edson L. Horta,

John W. Lockwood,

David E. Taylor,

David ParlourAuthors Info & Claims

DAC '02: Proceedings of the 39th annual Design Automation Conference

Pages 343 - 348

https://doi.org/10.1145/513918.514007

Published: 10 June 2002 Publication History

Abstract

Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet processing circuits on this platform are implemented as Dynamic Hardware Plugin (DHP) modules that fit within a specific region of an FPGA device. The PARBIT tool has been developed to transform and restructure bitfiles created by standard computer aided design tools into partial bitsteams that program DHPs. The methodology allows the platform to hot-swap application-specific DHP modules without disturbing the operation of the rest of the system.

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Cited By

Bailey D(2023)Design ConstraintsDesign for Embedded Image Processing on FPGAs10.1002/9781119819820.ch4(77-104)Online publication date: 5-Sep-2023
https://doi.org/10.1002/9781119819820.ch4
Bobda CMbongue JChow PEwais MTarafdar NVega JEguro KKoch DHandagala SLeeser MHerbordt MShahzad HHofste PRinglein BSzefer JSanaullah ATessier R(2022)The Future of FPGA Acceleration in Datacenters and the CloudACM Transactions on Reconfigurable Technology and Systems10.1145/350671315:3(1-42)Online publication date: 4-Feb-2022
https://dl.acm.org/doi/10.1145/3506713
Thomas JLavin CKaviani A(2021)Software-like Compilation for Data Center FPGA AcceleratorsProceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3468044.3468047(1-6)Online publication date: 21-Jun-2021
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Index Terms

Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
1. Hardware
2. Networks
  1. Network architectures

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Published In

cover image ACM Conferences

DAC '02: Proceedings of the 39th annual Design Automation Conference

June 2002

956 pages

ISBN:1581134614

DOI:10.1145/513918

General Chair:
Bryan Ackland
Agere Systems, Inc., Holmdel, NJ

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Published: 10 June 2002

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DAC02: 39th Design Automation Conference

June 10 - 14, 2002

Louisiana, New Orleans, USA

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DAC '02 Paper Acceptance Rate 147 of 491 submissions, 30%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Bailey D(2023)Design ConstraintsDesign for Embedded Image Processing on FPGAs10.1002/9781119819820.ch4(77-104)Online publication date: 5-Sep-2023
https://doi.org/10.1002/9781119819820.ch4
Bobda CMbongue JChow PEwais MTarafdar NVega JEguro KKoch DHandagala SLeeser MHerbordt MShahzad HHofste PRinglein BSzefer JSanaullah ATessier R(2022)The Future of FPGA Acceleration in Datacenters and the CloudACM Transactions on Reconfigurable Technology and Systems10.1145/350671315:3(1-42)Online publication date: 4-Feb-2022
https://dl.acm.org/doi/10.1145/3506713
Thomas JLavin CKaviani A(2021)Software-like Compilation for Data Center FPGA AcceleratorsProceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3468044.3468047(1-6)Online publication date: 21-Jun-2021
https://dl.acm.org/doi/10.1145/3468044.3468047
Isakovic HGrosu R(2018)A Mixed-Criticality Integration in Cyber-Physical SystemsSolutions for Cyber-Physical Systems Ubiquity10.4018/978-1-5225-2845-6.ch007(169-194)Online publication date: 2018
https://doi.org/10.4018/978-1-5225-2845-6.ch007
Hong CBenkrid KIsa NIturbe X(2014)A run-time reconfigurable system for adaptive high performance efficient computingACM SIGARCH Computer Architecture News10.1145/2641361.264138041:5(113-118)Online publication date: 18-Jun-2014
https://dl.acm.org/doi/10.1145/2641361.2641380
Dondo JBarba JRincóN FMoya FLóPez J(2013)Dynamic objectsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2012.09.00159:1(1-15)Online publication date: 1-Jan-2013
https://dl.acm.org/doi/10.1016/j.sysarc.2012.09.001
Liu MLu ZKuehn WJantsch A(2012)A Survey of FPGA Dynamic Reconfiguration Design Methodology and ApplicationsInternational Journal of Embedded and Real-Time Communication Systems10.4018/jertcs.20120401023:2(23-39)Online publication date: 1-Apr-2012
https://dl.acm.org/doi/10.4018/jertcs.2012040102
Oreifej RDemara R(2012)Intrinsic evolvable hardware platform for digital circuit design and repair using genetic algorithmsApplied Soft Computing10.1016/j.asoc.2012.03.03212:8(2470-2480)Online publication date: 1-Aug-2012
https://dl.acm.org/doi/10.1016/j.asoc.2012.03.032
Zhu GZhang Y(2011)Study on Key Technique of Reconfigurable CNC SystemAdvanced Materials Research10.4028/www.scientific.net/AMR.217-218.1590217-218(1590-1594)Online publication date: Mar-2011
https://doi.org/10.4028/www.scientific.net/AMR.217-218.1590
Unnikrishnan DLu JGao LTessier R(2011)ReClick - A Modular Dataplane Design Framework for FPGA-Based Network VirtualizationProceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems10.1109/ANCS.2011.31(145-155)Online publication date: 3-Oct-2011
https://dl.acm.org/doi/10.1109/ANCS.2011.31
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