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Heracles: a tool for fast RTL-based design space exploration of multicore processors

Authors:

Michel A. Kinsy,

Michael Pellauer,

Srinivas DevadasAuthors Info & Claims

FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

Pages 125 - 134

https://doi.org/10.1145/2435264.2435287

Published: 11 February 2013 Publication History

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Mascorro-Guardado EOrtega-Cisneros SBaungarten-Leon ELuna-Rodriguez LJaramillo-Toral UHernández-Aramburo MMurillo-García E(2024)Design and Test of Offset Quadrature Phase-Shift Keying Modulator with GF180MCU Open Source Process Design KitElectronics10.3390/electronics1309170513:9(1705)Online publication date: 28-Apr-2024
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Zhang YZhang ZWu C(2023)HierSyn: Fast Synthesis for Large Hierarchical Designs2023 IEEE 15th International Conference on ASIC (ASICON)10.1109/ASICON58565.2023.10396414(1-4)Online publication date: 24-Oct-2023
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Zulberti LDi Matteo SNannipieri PSaponara SFanucci L(2022)A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-CaseElectronics10.3390/electronics1122370411:22(3704)Online publication date: 12-Nov-2022
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Index Terms

Heracles: a tool for fast RTL-based design space exploration of multicore processors
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures
      2. Single instruction, multiple data

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Published In

FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

February 2013

294 pages

ISBN:9781450318877

DOI:10.1145/2435264

General Chair:
Brad Hutchings
Brigham Young University, USA
,
Program Chair:
Vaughn Betz
University of Toronto, Canada

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 11 February 2013

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FPGA '13: The 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 11 - 13, 2013

California, Monterey, USA

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Zhang YZhang ZWu C(2023)HierSyn: Fast Synthesis for Large Hierarchical Designs2023 IEEE 15th International Conference on ASIC (ASICON)10.1109/ASICON58565.2023.10396414(1-4)Online publication date: 24-Oct-2023
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Zulberti LDi Matteo SNannipieri PSaponara SFanucci L(2022)A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-CaseElectronics10.3390/electronics1122370411:22(3704)Online publication date: 12-Nov-2022
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Deb Nath ARaj KBhunia SRay S(2022)SoCCom: Automated Synthesis of System-on-Chip ArchitecturesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.314132630:4(449-462)Online publication date: Apr-2022
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