Abstract
Soft error in SRAM cell is one of the major reliability concern under aerospace radiation environment. A soft error occurs in SRAM cell due to charged particle strikes on sensitive nodes. In this paper a radiation hardened asymmetric 10T (AS10T) SRAM cell is presented to enhance the soft error hardening. The proposed cell uses read decoupled path to improve read static noise margin (RSNM) and voltage booster connected between storage nodes to improve node capacitance and hence enhanced radiation hardening. The proposed AS10T cell has a 75.83% higher critical charge as compared to 6T SRAM cell. For validation of soft error hardening of the proposed cell soft error rate ratio with supply voltage and temperature change is calculated and it is found that the AS10T has 6.41× and 3.2× less soft error rate ratio compared to 6T SRAM cell respectively. To better assess soft-error resilience and performance of the cell we introduce reliability stability to energy area product (RSEAP) ratio as a performance metric. Our analysis indicates that AS10T cell has 2.83× 1.6× and 1.36× higher RSEAP as compared to 6T RD8T and AS8T SRAM cells respectively.
Similar content being viewed by others
References
Ahmad S, Alam N, Hasan M (2018) Pseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications. AEU-Int J Electron Commun 83:366–375
Alouani I, Elsharkasy WM, Eltawil AM, Kurdahi FJ, Niar S (2017) AS8-static random access memory (SRAM): asymmetric sram architecture for soft error hardening enhancement. IET Circ Dev Syst 11(1):89–94
Chang L, Fried DM, Hergenrother J, Sleight JW, Dennard RH, Montoye RK, Sekaric L, McNab SJ, Topol AW, Adams CD, Guarini KW (2005) Stable SRAM cell design for the 32 nm node and beyond. In: Proc. of IEEE symposium on VLSI technology. Digest of Technical Papers 128–129
Ding Q, Luo R, Wang H, Yang H, Xie Y (2006) Modeling the impact of process variation on critical charge distribution. Proc IEEE Int SOC Conf 243–246
Dodd PE, Massengill LW (2003) Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Trans Nucl Sci 50(3):583–602
Granlund T, Granbom B, Olsson N (2003) Soft error rate increase for new generations of SRAMs. IEEE Trans Nucl Sci 50(6):2065–2068
Guo J, Zhu L, Sun Y, Cao H, Huang H, Wang T, Qi C, Zhang R, Cao X, Xiao L, Mao Z (2018) Design of area-efficient and highly reliable RHBD 10T memory cell for aerospace applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hughes H, Benedetto J (2003) Radiation effects and hardening of MOS technology: devices and circuits. IEEE Trans Nucl Sci 50(3):500–521
Ibe E, Taniguchi H, Yahagi Y, Shimbo Ki, Toba T (2010) Impact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule. IEEE Trans Electron Dev 57(7):1527– 1538
Jahinuzzaman SM, Sharifkhani M, Sachdev M (2009) An analytical model for soft error critical charge of nanometric SRAMs. IEEE Trans Very Large Scale Integr (VLSI) Syst 17(9):1187–1195
Kim JS, Chang IJ (2017) We-quatro: radiation-hardened SRAM cell with parametric process variation tolerance. IEEE Trans Nucl Sci 64(9):2489–2496
Kulkarni JP, Kim K, Roy K (2007) A 160 mV robust Schmitt trigger based subthreshold SRAM. IEEE J Solid State Circuits 42(10):2303–2313
Lin S, Kim YB, Lombardi F (2010) Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability. Integr VLSI J 43(2):176–187
Pasandi G, Fakhraie SM (2014) A 256-kB T near-threshold SRAM with 1K cells per bitline and enhanced write and read operations. IEEE Trans Very Large Scale Integr (VLSI) Syst 23(11):2438–2446
Predictive Technology Model (PTM) (2017). http://ptm.asu.edu/. Accessed on December 12 2017
Sanvale P, Gupta N, Neema V, Shah AP, Vishvakarma SK (2019) An improved read-assist energy efficient single ended PPN based 10T SRAM cell for wireless sensor network. Microelectron J 92(104):611
Shah AP, Waltl M (2020) Bias temperature instability aware and soft error tolerant radiation hardened 10T SRAM cell. Electronics 1–11
Shah AP, Yadav N, Beohar A, Vishvakarma SK (2018) An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells. Microelectron Reliab 87:15–23
Shah AP, Yadav N, Beohar A, Vishvakarma SK (2018) On-chip adaptive body bias for reducing the impact of NBTI on 6T SRAM cells. IEEE Trans Semicond Manuf 31(2):242– 249
Shah AP, Yadav N, Beohar A, Vishvakarma SK (2018) Process variation and NBTI resilient Schmitt trigger for stable and reliable circuits. IEEE Trans Dev Mater Reliab 1–9
Sharma V, Gopal M, Singh P, Vishvakarma SK (2018) A 220 mV robust read-decoupled partial feedback cutting based low-leakage 9T SRAM for internet of things (IoT) applications. AEU-Int J Electron Commun 87:144–157
Yan A, Huang Z, Yi M, Xu X, Ouyang Y, Liang H (2017) Double-node-upset-resilient latch design for nanoscale CMOS technology. IEEE Trans Very Large Scale Integr (VLSI) Syst 25(6):1978– 1982
Acknowledgments
The authors would like to thank the University Grant Commission (UGC) New Delhi Government of India under JRF scheme with award no. 3528/(NET-DEC. 2014) for providing financial support and CSIR Government of India with research project grant no. 22/0651 /14/EMR-II for simulation software.
Author information
Authors and Affiliations
Corresponding author
Additional information
Responsible Editor: K. K. Saluja
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Shah, A.P., Vishvakarma, S.K. & Hübner, M. Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications. J Electron Test 36, 255–269 (2020). https://doi.org/10.1007/s10836-020-05864-7
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-020-05864-7