Abstract
This paper is devoted to the original approach to block-level 3D IC layout design. The circuit components are modeled as autonomous mobile agents that explore their virtual world in order to find a globally near-optimal layout solution. The search space is defined by geometry features, wire connections, goals and constraints of the design task. The approach is illustrated by the example application to one of the MCNC benchmark circuits and implemented using Godot.
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Grzesiak-Kopeć, K., Nowak, L., Ogorzałek, M. (2017). 3D Integrated Circuits Layout Optimization Game. In: Rutkowski, L., Korytkowski, M., Scherer, R., Tadeusiewicz, R., Zadeh, L., Zurada, J. (eds) Artificial Intelligence and Soft Computing. ICAISC 2017. Lecture Notes in Computer Science(), vol 10246. Springer, Cham. https://doi.org/10.1007/978-3-319-59060-8_40
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DOI: https://doi.org/10.1007/978-3-319-59060-8_40
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