"A high-level synthesis flow for the implementation of iterative stencil ..."

Alessandro Antonio Nacci et al. (2013)

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DOI: 10.1145/2463209.2488797

access: closed

type: Conference or Workshop Paper

metadata version: 2019-10-19

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Alessandro Antonio Nacci, Vincenzo Rana, Francesco Bruschi, Donatella Sciuto, Ivan Beretta, David Atienza:
A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices. DAC 2013: 52:1-52:6

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