- Valencia, Spain
- http://mattvenn.net
- @matthewvenn
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basic-ecp5-pcb Public
Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs
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teensy-audio-fx Public
Playable effects modeled on the Teenage Engineering Pocket operator series. Featuring Teensy 4 for audio processing.
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caravel_user_project Public
Forked from efabless/caravel_user_project
Zero to ASIC group submission for MPW2
Verilog 12
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multi_project_tools Public
tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
2,153 contributions in the last year
Activity overview
Contribution activity
September 2022
Created 68 commits in 19 repositories
Created 9 repositories
- mattvenn/tinytapeout_spin0 Verilog
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mattvenn/tt001
Verilog
•
Built by
- mattvenn/tt_000
- mattvenn/tinytapeout-341802655228625490 Verilog
- mattvenn/tinytapeout-341802448429515346 Verilog
- mattvenn/tinytapeout_m_segments Verilog
- mattvenn/tinytapeout-laura Verilog
- mattvenn/tinytapeout-all-one Verilog
- mattvenn/tinytapeout-all-zero Verilog
Opened 1 pull request in 1 repository
jix/tinytapeout-from-template
1
open
Created an issue in mattvenn/tinytapeout-mpw7 that received 1 comment
Run a full chip simulation
Using iverilog is too slow to easily test the whole chain with all the contributed designs I do the testing with a chain of about 20. https://githu…




