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Pinned

  1. Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs

    Verilog 60 18

  2. vga-clock Public

    Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

    Verilog 42 8

  3. Playable effects modeled on the Teenage Engineering Pocket operator series. Featuring Teensy 4 for audio processing.

    C++ 39 4

  4. Forked from efabless/caravel_user_project

    Zero to ASIC group submission for MPW2

    Verilog 12

  5. logLUTs Public

    Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.

    Python 16 2

  6. tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles

    Python 24 14

2,153 contributions in the last year

Sep Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Mon Wed Fri

Contribution activity

September 2022

Opened 1 pull request in 1 repository
jix/tinytapeout-from-template 1 open

Created an issue in mattvenn/tinytapeout-mpw7 that received 1 comment

Run a full chip simulation

Using iverilog is too slow to easily test the whole chain with all the contributed designs I do the testing with a chain of about 20. https://githu…

1 comment
Opened 4 other issues in 4 repositories
mattvenn/tinytapeout-mpw7 1 open
MC-SecPat/tinytapeout_chiDOM 1 open
andars/universal-turing-machine-aw7s8 1 closed
coralmw/tinytapeout-css-feedback 1 closed

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