LLHD currently does not allow for RTL modules to be instantiated. Being able to so will be an important step towards co-simulating SystemVerilog/LLHD and RTL Dialect designs. This is likely just a modification in the verifier for the llhd.inst operation.

Eventually the following should work:

rtl.module @Foo(%a: i1) -> (%b: i1) {
  rtl.output %a : i1
 }

llhd.entity @Bar() -> () {
 

@honglh added optimized kernels for ARM32 in #432. It would be great if we could add support for bitpacked activations to them to match the AArch64 optimized bgemm kernels.