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Chris Lattner lattner

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Arctic Code Vault Contributor

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llvm/circt

Circuit IR Compilers and Tools

C++ 494 59
llvm/llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at…

8k 3.2k
apple/swift

The Swift Programming Language

C++ 55.4k 8.9k
tensorflow/swift

Swift for TensorFlow

Jupyter Notebook 6k 596
SwiftCommunityPodcast/podcast

About For and By the Swift Community

509 23

1,052 contributions in the last year

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Contribution activity

March 2021

Created 58 commits in 2 repositories

Reviewed 38 pull requests in 2 repositories

llvm/circt 36 pull requests

[FIRRTL] Parse CircuitTarget and ModuleTarget Annotations Mar 19
Update LLVM Mar 19
[FIR Parsing] Use int64 to parse integers instead of 32 Mar 18
A Utility pass to convert external modules to empty modules Mar 18
[Comb] Constant folding hook for comb.sub Mar 18
[SV] Check IfDefProceduralOp is in a procedural region Mar 17
[SV] Add RTL name legalization pass Mar 16
[firtool] Add option to emit one file per Verilog module Mar 16
[Seq] Proposal for dialect and reg op Mar 16
[SV] Verify behavioral constructs are in procedural regions Mar 15
[FIRRTL] Type Lowering of subaccess op Mar 13
[FIRRTL LowerTypes] Lower bundle wire connects in lower-types Mar 13
out-of-block uses shouldn't always force temporaries Mar 12
[SV] Invert IfOp if thenBlock is empty Mar 12
[ExportVerilog] Add option to control alwaysff printing Mar 12
Canonicalize partial connects Mar 12
[ExportVerilog] Replace . in names with _ Mar 12
[Handshake] Added temporary support for memory data with handshake-runner Mar 10
[Seq] Creating the new sequential dialect Mar 10
[FIRRTL LowerTypes] Add FExtModule type lowering Mar 10
Alias not supported by verilator Mar 10
Can't depend on the op to elide parenthesis Mar 9
[SV] Add NonProceduralOp trait Mar 7
Constant to generate 'x and 'z Mar 6
Rename module name keywords Mar 6
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apple/swift-evolution 2 pull requests

Created an issue in llvm/circt that received 3 comments

`comb.merge` verilog emission needs to be looked at

comb.merge emission always prints as a wire (see getVerilogDeclWord) but this won't work in a procedural region. We need to figure out how to emit …

3 comments

Opened 7 other issues in 1 repository

llvm/circt

5 closed 2 open