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March 2021
Created 33 commits in 1 repository
Reviewed 28 pull requests in 2 repositories
llvm/circt 27 pull requests
- [FIRRTL] Type Lowering of subaccess op
- [FIRRTL LowerTypes] Lower bundle wire connects in lower-types
- out-of-block uses shouldn't always force temporaries
- [SV] Invert IfOp if thenBlock is empty
- [ExportVerilog] Add option to control alwaysff printing
- Canonicalize partial connects
- [ExportVerilog] Replace `.` in names with `_`
- [Handshake] Added temporary support for memory data with handshake-runner
- [Seq] Creating the new sequential dialect
- [Seq] Proposal for dialect and `reg` op
- [FIRRTL LowerTypes] Add FExtModule type lowering
- Alias not supported by verilator
- Can't depend on the op to elide parenthesis
- [SV] Add NonProceduralOp trait
- Constant to generate 'x and 'z
- Rename module name keywords
- [SV] Verify if/fatal/casez/finish are in procedural regions
- [SV] Verify fwrite/bpassign/passign are in a procedural region
- [FIRRTL] Simpler read port lowering
- [ExportVerilog] Fixed struct printing in interfaces
- [RTL/Comb] Move bitcast back to RTL dialect
- [FIRRTL] Remove use of FunctionLike helpers in LowerTypes.
- [LowerToRTL] Handle register reset values narrower than register
- [ExportVerilog] Fix GCC error when using OpTraits
- [SV] Remove if/ifdef/always/initial op if they are empty
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apple/swift-evolution 1 pull request
Created an issue in llvm/circt that received 2 comments
`comb.merge` verilog emission needs to be looked at
comb.merge emission always prints as a wire (see getVerilogDeclWord) but this won't work in a procedural region. We need to figure out how to emit …
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comments
Opened 6 other issues in 1 repository
llvm/circt
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3
closed
- comb.and should handle `and(x, -1)` -> `x` in `fold()`
- [testsuite] tests shouldn't use firtool unless they are testing firtool itself
- [FIRRTL] Fix the syntax of `firrtl.constant` to match `rtl.constant`
- Add `sv.z` and `sv.x` ops
- [SV] Canonicalize sv.if blocks with empty then's into inverted conditions
- RTLCleanup is slow