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161 Open 489 Closed
161 Open 489 Closed
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Quadratic naming with recursive functions bug
#1606 opened Oct 8, 2020 by jackkoenig
4
Change in behavior between 3.3.2 and 3.4.0-RC3 for naming
#1603 opened Sep 30, 2020 by jackkoenig
1
Get reset value from RegInit
#1599 opened Sep 22, 2020 by lsteveol
Reassigning implicit clock and reset for DFT purposes
#1598 opened Sep 22, 2020 by lsteveol
4
Mixing ChiselStage with ChirrtlEmitter does not work in 3.4.0-RC2 bug
#1592 opened Sep 18, 2020 by jackkoenig
Why does FixedPoint get interpreted as Double when printing?
#1588 opened Sep 10, 2020 by HappyQuark
Vec.reduceTree leads to java.lang.OutOfMemoryError
#1576 opened Sep 2, 2020 by zhangkunta
[3.4.0-RC1] missing reference
#1569 opened Aug 25, 2020 by ekiwi
6
Request for multithreading support for verilator backend
#1567 opened Aug 25, 2020 by Entropy-xcy
1
Chisel tester with newest verilator as backend got a compile error
#1565 opened Aug 24, 2020 by name1e5s
1
chisel emitts expensive verilog
#1564 opened Aug 23, 2020 by sajjadahmed677
2
Add CONTRIBUTING.md
#1559 opened Aug 20, 2020 by jackkoenig
Static Right shift of SInt is inconsistent: neither arithmetic nor logical
#1528 opened Jul 29, 2020 by johnsbrew
1
Printable should adopt a `f"`-like handling of `%`
#1522 opened Jul 25, 2020 by jackkoenig
Some recommendations on stop
#1521 opened Jul 22, 2020 by davidmlw
4
Bundle asUInt ignores structural width
#1510 opened Jul 13, 2020 by ducky64
2
Does chisel plan to support full-featured SVA?
#1508 opened Jul 8, 2020 by MichaelYuan89
Interval literal creation is inconsistent API Modification bug
#1507 opened Jul 7, 2020 by chick 3.4.0
@chick
3
Propose Binary operator for Bool and Bits.
#1503 opened Jul 1, 2020 by davidmlw
1
Using "Flipped" on singleton Bundle results in unexpected behavior
#1497 opened Jun 24, 2020 by danielkasza
4
CloneModuleAsRecord needs a macro
#1478 opened Jun 18, 2020 by seldridge
There is VecInit.tabulate, why not VecInit.fill?
#1472 opened Jun 10, 2020 by mwachs5
1
java.util.NoSuchElementException: None.get encountered in `HasId`
#1466 opened Jun 7, 2020 by mwachs5
1
Bad error reporting on wrong (subword) assignments good first issue
#1465 opened Jun 6, 2020 by crepererum 3.3.x
5
Vec generates unreasonably large verilog with unnecesarry wires
#1456 opened May 30, 2020 by arun13e
2
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