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  1. The root repo for lowRISC project and FPGA demos.

    SystemVerilog 123 31 Built by @wsong83 @wallento @jrrk @furkanturan @asb
  2. training labs and examples

    SystemVerilog 61 45 Built by @mramdas @mayur13
  3. Contains the code examples from The UVM Primer Book sorted by chapters.

    SystemVerilog 52 39 Built by @rdsalemi
  4. SystemVerilog 32 14 Built by @atraber @svenstucki @FrancescoConti @gautschimi @be4web
  5. Ultimate multigame cartridge for Nintendo Famicom

    SystemVerilog 30 7 Built by @ClusterM
  6. a playground for xilinx zynq fpga experiments

    SystemVerilog 28 5 Built by @swetland @travisg
  7. Reference examples and short projects using UVM Methodology

    SystemVerilog 25 40 Built by @mramdas @robingarg89
  8. Source code repo for UVM Tutorial for Candy Lovers

    SystemVerilog 23 17 Built by @cluelogic
  9. SystemVerilog 21 8 Built by @nosnhojn @jesseprusi @tudortimi @daveread4 @chris-n-johnson
  10. RISC-V port to Parallella Board

    SystemVerilog 21 8 Built by @eliaskousk
  11. Examples and reference for System Verilog Assertions

    SystemVerilog 18 14 Built by @mramdas @mayur13
  12. SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)

    SystemVerilog 17 3 Built by @amiq-consulting
  13. openHMC - an open source Hybrid Memory Cube Controller

    SystemVerilog 16 6 Built by @jurischmidt
  14. a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially

    SystemVerilog 16 1 Built by @Poofjunior
  15. Collection of my presentations

    SystemVerilog 14 5 Built by @Obijuan
  16. Advanced Encryption Standard (AES) SystemVerilog Core

    SystemVerilog 13 5 Built by @cjdrake
  17. UVM agents

    SystemVerilog 12 8 Built by @dovstamler
  18. An attribute grammar-based meta-programming language for composable language extensions

    SystemVerilog 10 2 Built by @tedinski @krame505 @ericvanwyk @TravisCarlson @remexre
  19. SystemVerilog 10 3 Built by @ar-sc
  20. SystemVerilog VIP for AMBA APB protocol

    SystemVerilog 10 4 Built by @amiq-consulting
  21. Universal Advanced JTAG Debug Interface

    SystemVerilog 9 Built by @rherveille
  22. SystemVerilog 9 1 Built by @nosnhojn @kgover
  23. A collection of portable hardware modules

    SystemVerilog 8 8 Built by @Poofjunior
  24. SystemVerilog Extension Library -- a library of utilities for generic programming and increased productivity

    SystemVerilog 8 1 Built by @mxg
  25. Replica of micro-BESM computer

    SystemVerilog 8 1 Built by @sergev
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