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High Rate Soft Output Viterbi Decoder

Published: 11 March 1996 Publication History

Abstract

This paper presents the architecture of a high rate soft output Viterbi decoder (100 Mb/s for worst case process conditions, 8 states, coding rate R=1/2, using a 0.6ym CMOS technology), using the "radix" trellis method (collapsed trellis) to speed up the rate of a soft output decoder using the Viterbi algorithm and the a posteriori weighting algorithm. The size of this circuit is roughly twice that of the original soft output Viterbi decoder while the speed is increased by a factor of 2. Because of its performances, this circuit is very attractive for satellite digital communication systems and is at the root of "turbo-codes", which are a new class of convolutional codes whose performances, in terms of bit error rate, are close to the Shannon limit.

References

[1]
[1] C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit error correcting coding and decoding: turbo-codes", IEEE ICC'93, Vol. 2/3, pp. 1064-1070, Geneva, May 1993.
[2]
[2] A. J. Viterbi, "Error bounds for convolutional codes and an asymptotically optimum decoding algorithm", IEEE Trans. Inform. Theory, Vol. IT-13, pp. 260-269, April 1967.
[3]
[3] G. Battail, "Pondération des symboles décodés par l'algorithme de Viterbi" (in French), Annales des Télécommunications, No. 1-2, pp. 31-38, Jan.-Feb. 1987.
[4]
[4] J. Hagenauer, P. Hoeher, "A Viterbi algorithm with soft-decision outputs and its applications", Proc. GLOBECOM '89, pp. 4711-4717, Dallas, Texas, Nov. 1989.
[5]
[5] C. Berrou, P. Adde, "Procédé de décodage d'un code convolutif à maximum de vraisemblance et pondération des décisions, et décodeur correspondant" (in French), French patent No. 91 05279, 23 April 1991.
[6]
[6] "CAS5093: turbo encoder/decoder" Data sheet, COMATLAS, Chateaubourg, France, Nov. 1993.
[7]
[7] P. J. Black, H. Meng, "A 140-Mb/s, 32-State, Radix-4 Viterbi Decoder", IEEE Journal of solid-state circuits, VOL. 27, No. 12, Dec. 1992.
[8]
[8] E. Paaske, S. Pedersen, J. Sparso, "An area-efficient path memory structure for VLSI implementation of high speed Viterbi decoders", Integration, the VLSI journal, No. 12, pp. 79-91, Dee 1991.

Cited By

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  • (1999)Energy efficient data transfer and storage organization for a MAP turbo decoder moduleProceedings of the 1999 international symposium on Low power electronics and design10.1145/313817.313863(76-81)Online publication date: 17-Aug-1999
  1. High Rate Soft Output Viterbi Decoder

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    cover image ACM Conferences
    EDTC '96: Proceedings of the 1996 European conference on Design and Test
    March 1996
    585 pages
    ISBN:0818674237

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    IEEE Computer Society

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    Publication History

    Published: 11 March 1996

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    Author Tags

    1. VLSI design
    2. Viterbi decoding
    3. collapsed trellis
    4. digital communication systems
    5. high data rates
    6. soft output Viterbi decoding

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    • (1999)Energy efficient data transfer and storage organization for a MAP turbo decoder moduleProceedings of the 1999 international symposium on Low power electronics and design10.1145/313817.313863(76-81)Online publication date: 17-Aug-1999

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