skip to main content
10.5555/1766851.1766870guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
Article

Evaluating the performance of space plasma simulations using FPGA's

Published: 26 June 2002 Publication History

Abstract

This paper analyses the performance of a custom compute machine, that performs electrostatic plasma simulations, using Field Programmable Gate Array's (FPGAs). Although FPGA's run at slower clock speeds than their off-the-shelf counterparts, the processing power lost in the reduced number of clock cycles per second is quickly recovered in the high degree of spatial parallelism that is achievable within the devices. We describe the development of the architecture of the machine and its support for the C-programming language via the use of a cross-compiler. Results are presented and a discussion is given on the constraints of FPGAs in particular and the hardware design process in general.

References

[1]
Altera Corporation, San Jose, CA. The APEX 20K Programmable Logic Device Family Data Book, 2001. 243
[2]
Altera Corporation, San Jose, CA. The Stratix Programmable Logic Device Family Data Book, 2002. 253
[3]
J Bala, V Bruck. A portable and tunable collective communication library for scalable parallel computers. Technical report, IBM T. J Watson Research Center, 1993. 243
[4]
A.B Birdsall, C.K Langdon. Plasma Physics via Computer Simulation. Institute of Physics Publishing Ltd, 1991. 244
[5]
R Buyya, editor. High Performance Cluster Computing: Architectures and Systems. Prentice Hall, 1999. 243
[6]
J W Cooley, J W Tukey. An algorithm for the machine calculation of complex fourier series. Math. Comp. 19., pages 297-301, 1965. 245
[7]
D R Fraser, CW Hanson. A code generation interface for ansi c. Software-Practice and Experience, 21(9):963-988, Sept 1991. 249
[8]
R Freeman. User programmable gate arrays. IEEE Spectrum, December 1988. 243
[9]
D Goldberg. What every computer scientist should know about floating-point arithmetic. ACM Computing Surveys, 23(1):5-48, 1991. 246
[10]
C W Hanson, D R Fraser. A Retargetable C Compiler: Design and Implementation. Addison-Wesley Publishing Co, 1995. 249
[11]
WT Hauck, S Fry. The chimaera reconfigurable functional unit. IEEE Symposium on Field-Programmable Custom Computing Machines, 1997. 245
[12]
J Hauser, J Wawrzynek. Garp: A mips processor with a reconfigurable coprocessor. In Proceedings of the IEEE Symposium on Field Programable Custom Computing Machines, FCCM'97, April 1997. 245
[13]
D Hempel, R Walker. The emergence of the mpi message passing standard for parallel computing. Computer Standards and Interfaces, 7:51-62, 1999. 243
[14]
D Hennessy, J Patterson. Computer Organisation and Design - The Hardware Software Interface. Morgan Kaufman, 1998. 246
[15]
J W Hockney, R W Eastwood. Computer Simulations using Particles. Institute of Physics Publishing Ltd, 1999. 242
[16]
IEEE. ANSI/IEEE Standard 754 - 1985, Standard for Binary Floating Point Arithmetic. Institute for Electrical and Electronic Engineerings. 246
[17]
G Kane. MIPS RISC Architecture. Prentice Hall, 1988. 246
[18]
R E Kessler. The alpha 21264 microprocessor. IEEE Micro, March/April 1999. 246
[19]
Micron Technology Inc. Designing with ZBT SRAM, 2002. Micron technology app. notes. 246
[20]
D Patterson. Reduced instruction set computers. Comm. ACM, 28(1):8-21, Jan 1985. 246
[21]
M C Pease. An adaptation of the fast fourier transform for parallel processing. Journal of the ACM, 15:252-264, 1968. 245
[22]
R Russell. The cray-1 computer system. Communications of the ACM, 21(1), 1978. 243
[23]
P S Song, M Denman, and J Chang. The powerpc 604 risc microprocessor. IEEE Micro, October 1994. 246
[24]
R M Stallman. Using and Porting GNU CC - Cross Compiler. Free Software Foundation Inc, 1998. 249
[25]
C Temperton. Direct methods for the solution of the discrete poisson equation: Some comparissons. Journal of Computational Physics, 31:1-20, 1979. 245
[26]
J Walker, D Dongarra. Mpi: A standard message passing interface. Supercomputer, 12(1):56-68, January 1996. 243
[27]
P Wittig, R Chow. Onechip: An fpga processor with reconfigurable logic. IEEE Symposium on FPGA's for Custom Computing Machine, pages 126-135, 1996. 245

Index Terms

  1. Evaluating the performance of space plasma simulations using FPGA's
    Index terms have been assigned to the content through auto-classification.

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image Guide Proceedings
    VECPAR'02: Proceedings of the 5th international conference on High performance computing for computational science
    June 2002
    732 pages
    ISBN:3540008527
    • Editors:
    • José M. L. M. Palma,
    • A. Augusto Sousa,
    • Jack Dongarra,
    • Vicente Hernández

    Publisher

    Springer-Verlag

    Berlin, Heidelberg

    Publication History

    Published: 26 June 2002

    Qualifiers

    • Article

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • 0
      Total Citations
    • 1
      Total Downloads
    • Downloads (Last 12 months)0
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 22 Sep 2024

    Other Metrics

    Citations

    View Options

    View options

    Get Access

    Login options

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media