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Clock-Aware FPGA Placement Contest

Authors:

Srinivasan Dasasathyan,

Mehrdad E. Dehkordi,

Marvin Tom,

Rajat AggarwalAuthors Info & Claims

ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical Design

Pages 159 - 164

https://doi.org/10.1145/3036669.3038241

Published: 19 March 2017 Publication History

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Abstract

Modern FPGA device contains complex clocking architecture on top of FPGA logic fabric. To best utilize FPGA clocking architecture, both FPGA designers and EDA tool developers need to understand the clocking architecture and design best methodology/algorithm for various design styles. Clock legalization and clock aware placement become one of the key factors in FPGA design flow. They can greatly influence FPGA design performance and routability. FPGA placement problem can get very difficult with clock legalization constraints. This year's contest is a continuous challenge based on last year's routability driven placement. Contestants need to design best-in-class clock aware placement approach to excel in the contest.

References

[1]

R. Aggarwal, FPGA Place and Route Challenges, International Symposium on Physical Design. 2014

Digital Library

Google Scholar

[2]

S. Yang, A. Gayasen, C. Mulpuri, S. Reddy, and R. Aggarwal, Routability-Driven FPGA Placement Contest, International Symposium on Physical Design, 2016

Digital Library

Google Scholar

[3]

Xilinx, "UltraScale Architecture", http://www.xilinx.com/products/technology/ultrascale.html

Google Scholar

[4]

Xilinx, "Virtex UltraScale FPGAs", http://www.xilinx.com/publications/prod_mktg/ultrascalevirtex-product-table

Google Scholar

[5]

Xilinx, "UltraScale Architecture Configurable Logic Block User Guide", http://www.xilinx.com/support/documentation/user_guides/ug574-ultrascale-clb.pdf

Google Scholar

[6]

Xilinx, "UltraScale Architecture and Product Overview", http://www.xilinx.com/support/documentation/data_sheets/ds890-ultrascale-overview.pdf

Google Scholar

[7]

GNL: http://users.elis.ugent.be/~dstrooba/gnl/

Google Scholar

[8]

W. Li, S. Dhah, and D. Z. Pan, "UTPlaceF: A Routability-Driven FPGA Placer with Physical and Congestion Aware Packing", International Conference on Computer-Aided Design (ICCAD), 2016

Digital Library

Google Scholar

[9]

C.W. Pui, G. Chen, W.K. Chow, K.C. Lam, J. Kuang, P. Tu, H. Zhang, F.Y. Young, B. Yu, "RippleFPGA: A Routability-Driven Placement for Large-Scale Heterogeneous FPGAs", International Conference on Computer-Aided Design (ICCAD), 2016

Digital Library

Google Scholar

[10]

R. Pattison, Z. Abuowaimer, S. Areibi, G. Grewal, A. Vannelli, "GPlace -- A Congestion-aware Placement tool for UltraScale FPGAs", International Conference on Computer-Aided Design (ICCAD), 2016

Google Scholar

[11]

S. Dhah, S. Adya, L. Singhal, M. A. Iyer and D. Z. Pan "Detailed Placement for Modern FPGAs using 2D Dynamic Programming", International Conference on Computer-Aided Design (ICCAD), 2016

Google Scholar

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Liang TChen GZhao JSinha SZhang W(2024)AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGAIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337335743:9(2769-2782)Online publication date: Sep-2024
https://doi.org/10.1109/TCAD.2024.3373357
Zhu ZMei YDeng KHe HChen JYang JChang Y(2024)High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332977443:3(956-969)Online publication date: Mar-2024
https://doi.org/10.1109/TCAD.2023.3329774
Mai JWang JDi ZLin Y(2024)Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.331310143:2(641-653)Online publication date: Feb-2024
https://doi.org/10.1109/TCAD.2023.3313101
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Index Terms

Clock-Aware FPGA Placement Contest
1. Hardware
  1. Integrated circuits
    1. Reconfigurable logic and FPGAs

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Published In

ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical Design

March 2017

176 pages

ISBN:9781450346962

DOI:10.1145/3036669

General Chair:
Mustafa Ozdal
Bilkent University
,
Program Chair:
Chris Chu
Iowa State University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 March 2017

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ISPD '17

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SIGDA

ISPD '17: International Symposium on Physical Design

March 19 - 22, 2017

Oregon, Portland, USA

Acceptance Rates

Overall Acceptance Rate 62 of 172 submissions, 36%

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ISPD '25

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sigda

International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

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Liang TChen GZhao JSinha SZhang W(2024)AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGAIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337335743:9(2769-2782)Online publication date: Sep-2024
https://doi.org/10.1109/TCAD.2024.3373357
Zhu ZMei YDeng KHe HChen JYang JChang Y(2024)High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332977443:3(956-969)Online publication date: Mar-2024
https://doi.org/10.1109/TCAD.2023.3329774
Mai JWang JDi ZLin Y(2024)Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.331310143:2(641-653)Online publication date: Feb-2024
https://doi.org/10.1109/TCAD.2023.3313101
Mai JWang JChen YGuo ZJiang XLiang YLin Y(2024)OpenPARF 3.0: Robust Multi-Electrostatics Based FPGA Macro Placement Considering Cascaded Macros Groups and Fence Regions2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617535(374-379)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617535
Luo QZang XWang QWang FYoung EWong M(2024)A Routability-Driven Ultrascale FPGA Macro Placer with Complex Design Constraints2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM60383.2024.00024(1-7)Online publication date: 5-May-2024
https://doi.org/10.1109/FCCM60383.2024.00024
Li ZZhu ZHe HChen J(2024)An effective routability-driven packing algorithm for large-scale heterogeneous FPGAsIntegration10.1016/j.vlsi.2023.10209894(102098)Online publication date: Jan-2024
https://doi.org/10.1016/j.vlsi.2023.102098
Wei MTong XWen YChen JYu JZhu WChang Y(2023)Analytical Placement with 3D Poisson’s Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAsACM Transactions on Design Automation of Electronic Systems10.1145/358255428:5(1-24)Online publication date: 31-Jan-2023
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Mai JWang JDi ZLuo GLiang YLin Y(2023)OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit2023 IEEE 15th International Conference on ASIC (ASICON)10.1109/ASICON58565.2023.10396248(1-4)Online publication date: 24-Oct-2023
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Yu TDarav NBustany IDehkordi MBadaroglu MDutt S(2022)A Machine Learning Approach for Accelerating SimPL-Based Global Placement for FPGA'sProceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding10.1145/3557988.3569714(1-7)Online publication date: 3-Nov-2022
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Zhu ZMei YLi ZLin JChen JYang JChang YOshana R(2022)High-performance placement for large-scale heterogeneous FPGAs with clock constraintsProceedings of the 59th ACM/IEEE Design Automation Conference10.1145/3489517.3530567(643-648)Online publication date: 10-Jul-2022
https://dl.acm.org/doi/10.1145/3489517.3530567
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Routability-Driven FPGA Placement Contest

Routability-Driven Blockage-Aware Macro Placement

Routability-driven placement for hierarchical mixed-size circuit designs

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Routability-Driven FPGA Placement Contest

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Routability-driven placement for hierarchical mixed-size circuit designs

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