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- invited-talkMarch 2024
PANEL: EDA Challenges at Advanced Technology Nodes A
ISPD '24: Proceedings of the 2024 International Symposium on Physical DesignMarch 2024, Page 67https://doi.org/10.1145/3626184.3639698Le-Chin Eugene Liu received a Bachelor's and a Master's degree in electronics engineering from the National Chao Tung University, Hsinchu, Taiwan, and a Ph.D. from the Department of Electrical Engineering, University of Washington, Seattle, Washington, ...
- research-articleMarch 2023
Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature Distribution
- Armen Kteyan,
- Valeriy Sukharev,
- Alexander Volkov,
- Jun Ho Choy,
- Farid N. Najm,
- Yong Hyeon Yi,
- Chris H. Kim,
- Stephane Moreau
ISPD '23: Proceedings of the 2023 International Symposium on Physical DesignMarch 2023, Pages 124–132https://doi.org/10.1145/3569052.3578922A recently proposed methodology for electromigration (EM) assessment in on-chip power/ground grid of integrated circuits has been validated by means of measurements, performed on dedicated test grids. IR drop degradation in the grid is used for defining ...
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- research-articleApril 2022
Novel Methodology for Assessing Chip-Package Interaction Effects onChip Performance
- Armen Kteyan,
- Jun-Ho Choy,
- Valeriy Sukharev,
- Massimo Bertoletti,
- Carmelo Maiorca,
- Rossana Zadra,
- Massimo Inzaghi,
- Gabriele Gattere,
- Giancarlo Zinco,
- Paolo Valente,
- Roberto Bardelli,
- Alessandro Valerio,
- Pierluigi Rolandi,
- Mattia Monetti,
- Valentina Cuomo,
- Salvatore Santapà
ISPD '22: Proceedings of the 2022 International Symposium on Physical DesignApril 2022, Pages 83–89https://doi.org/10.1145/3505170.3511798The paper presents a multiscale simulation methodology and EDA tool that assesses the effect of thermal mechanical stresses arising after die assembly on chip performance. Existing non uniformities of feature geometries and composite nature of on-chip ...
- keynoteMarch 2021
Physical Verification at Advanced Technology Nodes and the Road Ahead
ISPD '21: Proceedings of the 2021 International Symposium on Physical DesignMarch 2021, Page 113https://doi.org/10.1145/3439706.3446901In spite of "doomsday" expectations, Moore's Law is alive and well. Semiconductor manufacturing and design companies, as well as the Electronic Design Automation (EDA) industry have been pushing ahead to bring more functionality to satisfy more ...
- research-articleApril 2019
Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach
ISPD '19: Proceedings of the 2019 International Symposium on Physical DesignApril 2019, Pages 129–137https://doi.org/10.1145/3299902.3309746Recent work has established Lagrangian relaxation (LR) based gate sizing as state-of-the-art providing the best power reduction with low run time. Gate sizing has limited potential to reduce the power when the timing constraints are tight. By adjusting ...
- research-articleMarch 2017
A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement
ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical DesignMarch 2017, Pages 141–148https://doi.org/10.1145/3036669.3036680The standard-cell placement legalization problem has become critical due to increasing design rule complexity and design utilization at 16nm and lower technology nodes. An ideal legalization approach should preserve the quality of the input placement in ...
- research-articleMarch 2017
DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment
ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical DesignMarch 2017, Pages 91–98https://doi.org/10.1145/3036669.3036677Directed self-assembly (DSA) is a promising solution for fabrication of contacts and vias for advanced technology nodes. In this paper, we study a DSA aware detailed routing problem, where DSA guiding pattern assignment and guiding pattern double ...
- invited-talkMarch 2015
From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges
- Olivier Billoint,
- Hossam Sarhan,
- Iyad Rayane,
- Maud Vinet,
- Perrine Batude,
- Claire Fenouillet-Beranger,
- Olivier Rozeau,
- Gerald Cibrario,
- Fabien Deprat,
- Ogun Turkyilmaz,
- Sebastien Thuries,
- Fabien Clermidy
ISPD '15: Proceedings of the 2015 Symposium on International Symposium on Physical DesignMarch 2015, Page 127https://doi.org/10.1145/2717764.2723573Design of conventional 2D integrated circuits is becoming more and more challenging as we strive to keep on following Moore's law. Cost, thermal behavior, multiple patterning, increasing number of design rules, transistor characteristics, variability ...
- research-articleMarch 2015
ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement
ISPD '15: Proceedings of the 2015 Symposium on International Symposium on Physical DesignMarch 2015, Pages 157–164https://doi.org/10.1145/2717764.2723572The ISPD~2015 placement-contest benchmarks include all the detailed pin, cell, and wire geometry constraints from the 2014 release, plus
(a) added fence regions and placement blockages,
(b) altered netlists including fixed macro blocks,
(c) reduced ...
- research-articleMarch 2014
ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement
ISPD '14: Proceedings of the 2014 on International symposium on physical designMarch 2014, Pages 161–168https://doi.org/10.1145/2560519.2565877The public release of realistic industrial placement benchmarks by IBM and Intel Corporations from 1998--2013 has been crucial to the progress in physical-design algorithms during those years. Direct comparisons of academic tools on these test cases, ...
- keynoteMarch 2014
Hardware cyber security
ISPD '14: Proceedings of the 2014 on International symposium on physical designMarch 2014, Pages 1–2https://doi.org/10.1145/2560519.2565868The attacks targeting hardware range from IP piracy to data theft to intentional hardware compromise and sabotage. Of particular concern are systemic, or combined, attacks that include both software and hardware elements: as the secure computing ...
- research-articleMarch 2014
Clock tree resynthesis for multi-corner multi-mode timing closure
ISPD '14: Proceedings of the 2014 on International symposium on physical designMarch 2014, Pages 69–76https://doi.org/10.1145/2560519.2560524With aggressive technology scaling and complex design scenarios, timing closure has become a challenging and tedious job for the designers. Timing violations persist for multi- corner, multi-mode designs in the deep-routing stage although careful ...
- extended-abstractMarch 2013
Variability aware hierarchical implementation of big chips
ISPD '13: Proceedings of the 2013 ACM International symposium on Physical DesignMarch 2013, Page 181https://doi.org/10.1145/2451916.2451965Over the last decade, transistor dimensions have shrunk rapidly by a factor of ten, while chip sizes have increased many folds and so have the scenarios in which they are expected to function. Silo technology development of yester years has all but ...
- research-articleMarch 2013
High performance and low power design techniques for ASIC and custom in nanometer technologies
ISPD '13: Proceedings of the 2013 ACM International symposium on Physical DesignMarch 2013, Pages 25–32https://doi.org/10.1145/2451916.2451923Traditionally, synthesized application-specific integrated circuits (ASICs) have been slower and higher power than custom integrated circuits due to a variety of factors. This paper details how this gap has decreased in the past few years. ASICs have ...
- research-articleMarch 2012
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip
ISPD '12: Proceedings of the 2012 ACM international symposium on International Symposium on Physical DesignMarch 2012, Pages 187–192https://doi.org/10.1145/2160916.2160957Floorplanning, as an early stage of the physical design flow, has been extensively studied in literature and developed into several branches. Recently, hierarchical floorplanning is regaining attention due to the rising scale of systems-on-chip, which ...
- research-articleMarch 2012
Construction of minimal functional skew clock trees
ISPD '12: Proceedings of the 2012 ACM international symposium on International Symposium on Physical DesignMarch 2012, Pages 119–120https://doi.org/10.1145/2160916.2160943Power is the number one implementation challenge for many consumer SoCs, especially in the telecommunications and mobile space. A large portion of that, 30% or more, can be directly attributed to the clock tree. 10-20% additional power can additionally ...