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Unified Component Integration Flow for Multi-Processor SoC Design and Validation

Published: 16 February 2004 Publication History

Abstract

Most system-on-Chip (SoC) design methodologies promote the reuse of pre-designed (hardware, software, and functional) components. However, as these components are heterogeneous, their integration requires complex interface sub-systems. These sub-systems can also be constructed by assembling pre-designed basic interface components. Hence, SoC design and validation involves component composition techniques to create hardware, software, and functional interface sub-systems by assembling basic interface components. We propose a unified methodology for automatic component integration that allows designers to reuse pre-designed components effectively. We also present ROSES, a design flow that uses this methodology to generate hardware, software, and functional interface sub-systems automatically starting from a system-level architectural model.

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Cited By

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  • (2006)A SW performance estimation framework for early system-level-design using fine-grained instrumentationProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131607(468-473)Online publication date: 6-Mar-2006
  • (2005)A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC PlatformsProceedings of the conference on Design, Automation and Test in Europe - Volume 210.1109/DATE.2005.21(876-881)Online publication date: 7-Mar-2005
  • (2004)Heterogeneous MP-SoCProceedings of the 41st annual Design Automation Conference10.1145/996566.996754(686-691)Online publication date: 7-Jun-2004
  • Show More Cited By

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  1. Unified Component Integration Flow for Multi-Processor SoC Design and Validation

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      cover image ACM Conferences
      DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 2
      February 2004
      606 pages
      ISBN:0769520855

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      Published: 16 February 2004

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      View all
      • (2006)A SW performance estimation framework for early system-level-design using fine-grained instrumentationProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131607(468-473)Online publication date: 6-Mar-2006
      • (2005)A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC PlatformsProceedings of the conference on Design, Automation and Test in Europe - Volume 210.1109/DATE.2005.21(876-881)Online publication date: 7-Mar-2005
      • (2004)Heterogeneous MP-SoCProceedings of the 41st annual Design Automation Conference10.1145/996566.996754(686-691)Online publication date: 7-Jun-2004
      • (2004)Design and programming of embedded multiprocessorsProceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/1016720.1016771(206-217)Online publication date: 8-Sep-2004

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