skip to main content
10.5555/2133429.2133570acmconferencesArticle/Chapter ViewAbstractPublication PagesiccadConference Proceedingsconference-collections
research-article

Design-hierarchy aware mixed-size placement for routability optimization

Published: 07 November 2010 Publication History

Abstract

Routability is a mandatory metric for modern large-scale mixed-size circuit placement which typically needs to handle hundreds of large macros and millions of small standard cells. However, most existing academic mixed-size placers either focus on wirelength minimization alone, or do not consider the impact of movable macros on routing. To remedy these insufficiencies, this paper formulates design-hierarchy information as a novel fence force in an analytical placement framework. Unlike a state-of-the-art routability-driven placer that simply removes net bounding boxes during placement, this paper utilizes two different optimization forces, the global fence force and the local spreading force, to determine the positions of both standard cells and macros. We utilize design-hierarchy information to determine block distributions globally, and locally we add additional spreading forces to preserve sufficient free space among blocks by a net-topology estimation. With the interactions between these two forces, our placer can well balance routability and wirelength. Experimental results show that our placer can achieve the best routability and routing time among all published works.

References

[1]
C. Alpert, A. Kahng, G.-J. Nam, S. Reda, and P. Villarrubia. A semi-persistent clustering technique for VLSI circuit placement. In Proc. of ISPD, 2005.
[2]
T. Chan, J. Cong, J. Shinnerl, K. Sze, and M. Xie. mPL6: Enhanced multilevel mixed-size placement. In Proc. of ISPD, 2006.
[3]
T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang. NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. In IEEE TCAD, 2008.
[4]
T.-C. Chen, M. Cho, D. Z. Pan, and Y.-W. Chang. Metal-density driven placement for CMP variation and routability. In Proc. of ISPD, 2008.
[5]
Y. Cheon and D. F. Wong. Design hierarchy guided multilevel circuit partitioning. In Proc. of ISPD, 2002.
[6]
C. Chu and Y.-C. Wong. Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design. In Proc. of ISPD, 2005.
[7]
J. Fischer and V. Heun. Theoretical and practical improvements on the RMQ-problem, with applications to LCA and LCE. In Proc. of CPM, 2006.
[8]
J. Hu, J. A. Roy, and I. L. Markov. Completing high-quality global routes. In Proc. of ISPD, 2010.
[9]
ISPD 2005 Placement Contest. http://www.sigda.org/ispd2005/contest.htm.
[10]
ISPD 2007 Routing Contest. http://www.sigda.org/ispd2007/contest.html.
[11]
Z.-W. Jiang, B.-Y. Su, and Y.-W. Chang. Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. In Proc. of DAC, 2008.
[12]
A. B. Kahng and Q. Wang. Implementation and extensibility of an analytic placer. In IEEE TCAD, 2005.
[13]
W. C. Naylor, R. Donelly, and L. Sha. Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer. U. S. Patent 6 301 693, 2001.
[14]
J. A. Roy, S. N. Adya, D. A. Papa, and I. L. Markov. Min-cut floorplacement. In Proc. of TCAD, 2006.
[15]
J. A. Roy and I. L. Markov. High-performance routing at the nanometer scale. In Proc. of ICCAD, 2007.
[16]
J. A. Roy, J. F. Lu, and I. L. Markov. Seeing the forest and the trees: Steiner wirelength optimization in placement. In IEEE TCAD, 2007.
[17]
J. Westra, C. Bartels, and P. Geoeneveld. Probabilistic congestion prediction. In Proc. of ISPD, 2004.
[18]
J. Z. Yan, N. Viswanathan, and C. Chu. Handling complexities in modern large-scale mixed-size placement. In Proc. of DAC, 2009.

Cited By

View all
  • (2019)Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between MacrosProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317901(1-6)Online publication date: 2-Jun-2019
  • (2016)Ripple 2.0ACM Transactions on Design Automation of Electronic Systems10.1145/292598922:1(1-26)Online publication date: 2-Sep-2016
  • (2013)Ripple 2.0Proceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488922(1-6)Online publication date: 29-May-2013
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
ICCAD '10: Proceedings of the International Conference on Computer-Aided Design
November 2010
863 pages
ISBN:9781424481927
  • General Chair:
  • Louis Scheffer,
  • Program Chairs:
  • Joel Phillips,
  • Alan J. Hu

Sponsors

Publisher

IEEE Press

Publication History

Published: 07 November 2010

Check for updates

Qualifiers

  • Research-article

Conference

ICCAD '10
Sponsor:

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Upcoming Conference

ICCAD '24
IEEE/ACM International Conference on Computer-Aided Design
October 27 - 31, 2024
New York , NY , USA

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)4
  • Downloads (Last 6 weeks)1
Reflects downloads up to 14 Sep 2024

Other Metrics

Citations

Cited By

View all
  • (2019)Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between MacrosProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317901(1-6)Online publication date: 2-Jun-2019
  • (2016)Ripple 2.0ACM Transactions on Design Automation of Electronic Systems10.1145/292598922:1(1-26)Online publication date: 2-Sep-2016
  • (2013)Ripple 2.0Proceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488922(1-6)Online publication date: 29-May-2013
  • (2013)Routability-driven placement for hierarchical mixed-size circuit designsProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488921(1-6)Online publication date: 29-May-2013
  • (2013)SRPProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451943(108-113)Online publication date: 24-Mar-2013
  • (2012)Progress and challenges in VLSI placement researchProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429441(275-282)Online publication date: 5-Nov-2012
  • (2012)ComPLx: A Competitive Primal-dual Lagrange Optimization for Global PlacementProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228496(747-752)Online publication date: 3-Jun-2012
  • (2012)Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chipProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160957(187-192)Online publication date: 25-Mar-2012
  • (2011)Implementation of pulsed-latch and pulsed-register circuits to minimize clocking powerProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132469(640-646)Online publication date: 7-Nov-2011
  • (2011)RippleProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132347(74-79)Online publication date: 7-Nov-2011

View Options

Get Access

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media